1 /* 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/clkdev.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/delay.h> 24 #include <linux/export.h> 25 #include <linux/clk/tegra.h> 26 #include <dt-bindings/clock/tegra210-car.h> 27 28 #include "clk.h" 29 #include "clk-id.h" 30 31 /* 32 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register 33 * banks present in the Tegra210 CAR IP block. The banks are 34 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See 35 * periph_regs[] in drivers/clk/tegra/clk.c 36 */ 37 #define TEGRA210_CAR_BANK_COUNT 7 38 39 #define CLK_SOURCE_CSITE 0x1d4 40 #define CLK_SOURCE_EMC 0x19c 41 42 #define PLLC_BASE 0x80 43 #define PLLC_OUT 0x84 44 #define PLLC_MISC0 0x88 45 #define PLLC_MISC1 0x8c 46 #define PLLC_MISC2 0x5d0 47 #define PLLC_MISC3 0x5d4 48 49 #define PLLC2_BASE 0x4e8 50 #define PLLC2_MISC0 0x4ec 51 #define PLLC2_MISC1 0x4f0 52 #define PLLC2_MISC2 0x4f4 53 #define PLLC2_MISC3 0x4f8 54 55 #define PLLC3_BASE 0x4fc 56 #define PLLC3_MISC0 0x500 57 #define PLLC3_MISC1 0x504 58 #define PLLC3_MISC2 0x508 59 #define PLLC3_MISC3 0x50c 60 61 #define PLLM_BASE 0x90 62 #define PLLM_MISC1 0x98 63 #define PLLM_MISC2 0x9c 64 #define PLLP_BASE 0xa0 65 #define PLLP_MISC0 0xac 66 #define PLLP_MISC1 0x680 67 #define PLLA_BASE 0xb0 68 #define PLLA_MISC0 0xbc 69 #define PLLA_MISC1 0xb8 70 #define PLLA_MISC2 0x5d8 71 #define PLLD_BASE 0xd0 72 #define PLLD_MISC0 0xdc 73 #define PLLD_MISC1 0xd8 74 #define PLLU_BASE 0xc0 75 #define PLLU_OUTA 0xc4 76 #define PLLU_MISC0 0xcc 77 #define PLLU_MISC1 0xc8 78 #define PLLX_BASE 0xe0 79 #define PLLX_MISC0 0xe4 80 #define PLLX_MISC1 0x510 81 #define PLLX_MISC2 0x514 82 #define PLLX_MISC3 0x518 83 #define PLLX_MISC4 0x5f0 84 #define PLLX_MISC5 0x5f4 85 #define PLLE_BASE 0xe8 86 #define PLLE_MISC0 0xec 87 #define PLLD2_BASE 0x4b8 88 #define PLLD2_MISC0 0x4bc 89 #define PLLD2_MISC1 0x570 90 #define PLLD2_MISC2 0x574 91 #define PLLD2_MISC3 0x578 92 #define PLLE_AUX 0x48c 93 #define PLLRE_BASE 0x4c4 94 #define PLLRE_MISC0 0x4c8 95 #define PLLDP_BASE 0x590 96 #define PLLDP_MISC 0x594 97 98 #define PLLC4_BASE 0x5a4 99 #define PLLC4_MISC0 0x5a8 100 #define PLLC4_OUT 0x5e4 101 #define PLLMB_BASE 0x5e8 102 #define PLLMB_MISC1 0x5ec 103 #define PLLA1_BASE 0x6a4 104 #define PLLA1_MISC0 0x6a8 105 #define PLLA1_MISC1 0x6ac 106 #define PLLA1_MISC2 0x6b0 107 #define PLLA1_MISC3 0x6b4 108 109 #define PLLU_IDDQ_BIT 31 110 #define PLLCX_IDDQ_BIT 27 111 #define PLLRE_IDDQ_BIT 24 112 #define PLLA_IDDQ_BIT 25 113 #define PLLD_IDDQ_BIT 20 114 #define PLLSS_IDDQ_BIT 18 115 #define PLLM_IDDQ_BIT 5 116 #define PLLMB_IDDQ_BIT 17 117 #define PLLXP_IDDQ_BIT 3 118 119 #define PLLCX_RESET_BIT 30 120 121 #define PLL_BASE_LOCK BIT(27) 122 #define PLLCX_BASE_LOCK BIT(26) 123 #define PLLE_MISC_LOCK BIT(11) 124 #define PLLRE_MISC_LOCK BIT(27) 125 126 #define PLL_MISC_LOCK_ENABLE 18 127 #define PLLC_MISC_LOCK_ENABLE 24 128 #define PLLDU_MISC_LOCK_ENABLE 22 129 #define PLLU_MISC_LOCK_ENABLE 29 130 #define PLLE_MISC_LOCK_ENABLE 9 131 #define PLLRE_MISC_LOCK_ENABLE 30 132 #define PLLSS_MISC_LOCK_ENABLE 30 133 #define PLLP_MISC_LOCK_ENABLE 18 134 #define PLLM_MISC_LOCK_ENABLE 4 135 #define PLLMB_MISC_LOCK_ENABLE 16 136 #define PLLA_MISC_LOCK_ENABLE 28 137 #define PLLU_MISC_LOCK_ENABLE 29 138 #define PLLD_MISC_LOCK_ENABLE 18 139 140 #define PLLA_SDM_DIN_MASK 0xffff 141 #define PLLA_SDM_EN_MASK BIT(26) 142 143 #define PLLD_SDM_EN_MASK BIT(16) 144 145 #define PLLD2_SDM_EN_MASK BIT(31) 146 #define PLLD2_SSC_EN_MASK BIT(30) 147 148 #define PLLDP_SS_CFG 0x598 149 #define PLLDP_SDM_EN_MASK BIT(31) 150 #define PLLDP_SSC_EN_MASK BIT(30) 151 #define PLLDP_SS_CTRL1 0x59c 152 #define PLLDP_SS_CTRL2 0x5a0 153 154 #define PMC_PLLM_WB0_OVERRIDE 0x1dc 155 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 156 157 #define UTMIP_PLL_CFG2 0x488 158 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) 159 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 160 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) 162 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 163 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) 164 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 165 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) 166 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) 167 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) 168 169 #define UTMIP_PLL_CFG1 0x484 170 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 171 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 172 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 173 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 174 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 175 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 176 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 177 178 #define UTMIPLL_HW_PWRDN_CFG0 0x52c 179 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) 180 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 181 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 182 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7) 183 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 184 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 185 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 186 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 187 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 188 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 189 190 #define PLLU_HW_PWRDN_CFG0 0x530 191 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) 192 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 193 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) 194 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 195 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 196 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) 197 198 #define XUSB_PLL_CFG0 0x534 199 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff 200 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14) 201 202 #define SPARE_REG0 0x55c 203 #define CLK_M_DIVISOR_SHIFT 2 204 #define CLK_M_DIVISOR_MASK 0x3 205 206 /* 207 * SDM fractional divisor is 16-bit 2's complement signed number within 208 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned 209 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to 210 * indicate that SDM is disabled. 211 * 212 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 213 */ 214 #define PLL_SDM_COEFF BIT(13) 215 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 216 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 217 218 /* Tegra CPU clock and reset control regs */ 219 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 220 221 #ifdef CONFIG_PM_SLEEP 222 static struct cpu_clk_suspend_context { 223 u32 clk_csite_src; 224 } tegra210_cpu_clk_sctx; 225 #endif 226 227 static void __iomem *clk_base; 228 static void __iomem *pmc_base; 229 230 static unsigned long osc_freq; 231 static unsigned long pll_ref_freq; 232 233 static DEFINE_SPINLOCK(pll_d_lock); 234 static DEFINE_SPINLOCK(pll_e_lock); 235 static DEFINE_SPINLOCK(pll_re_lock); 236 static DEFINE_SPINLOCK(pll_u_lock); 237 static DEFINE_SPINLOCK(emc_lock); 238 239 /* possible OSC frequencies in Hz */ 240 static unsigned long tegra210_input_freq[] = { 241 [5] = 38400000, 242 [8] = 12000000, 243 }; 244 245 static const char *mux_pllmcp_clkm[] = { 246 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", 247 "pll_p", 248 }; 249 #define mux_pllmcp_clkm_idx NULL 250 251 #define PLL_ENABLE (1 << 30) 252 253 #define PLLCX_MISC1_IDDQ (1 << 27) 254 #define PLLCX_MISC0_RESET (1 << 30) 255 256 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000 257 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb 258 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000 259 #define PLLCX_MISC1_WRITE_MASK 0x08003cff 260 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05 261 #define PLLCX_MISC2_WRITE_MASK 0xffffff17 262 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4 263 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff 264 265 /* PLLA */ 266 #define PLLA_BASE_IDDQ (1 << 25) 267 #define PLLA_BASE_LOCK (1 << 27) 268 269 #define PLLA_MISC0_LOCK_ENABLE (1 << 28) 270 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27) 271 272 #define PLLA_MISC2_EN_SDM (1 << 26) 273 #define PLLA_MISC2_EN_DYNRAMP (1 << 25) 274 275 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020 276 #define PLLA_MISC0_WRITE_MASK 0x7fffffff 277 #define PLLA_MISC2_DEFAULT_VALUE 0x0 278 #define PLLA_MISC2_WRITE_MASK 0x06ffffff 279 280 /* PLLD */ 281 #define PLLD_MISC0_EN_SDM (1 << 16) 282 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17) 283 #define PLLD_MISC0_LOCK_ENABLE (1 << 18) 284 #define PLLD_MISC0_IDDQ (1 << 20) 285 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21) 286 287 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000 288 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff 289 #define PLLD_MISC1_DEFAULT_VALUE 0x20 290 #define PLLD_MISC1_WRITE_MASK 0x00ffffff 291 292 /* PLLD2 and PLLDP and PLLC4 */ 293 #define PLLDSS_BASE_LOCK (1 << 27) 294 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24) 295 #define PLLDSS_BASE_IDDQ (1 << 18) 296 #define PLLDSS_BASE_REF_SEL_SHIFT 25 297 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT) 298 299 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30) 300 301 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31) 302 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30) 303 304 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020 305 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000 306 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0 307 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0 308 309 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020 310 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000 311 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da 312 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400 313 314 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff 315 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000 316 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff 317 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff 318 319 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000 320 321 /* PLLRE */ 322 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30) 323 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29) 324 #define PLLRE_MISC0_LOCK (1 << 27) 325 #define PLLRE_MISC0_IDDQ (1 << 24) 326 327 #define PLLRE_BASE_DEFAULT_VALUE 0x0 328 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000 329 330 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000 331 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff 332 333 /* PLLX */ 334 #define PLLX_USE_DYN_RAMP 1 335 #define PLLX_BASE_LOCK (1 << 27) 336 337 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28) 338 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18) 339 340 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24 341 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT) 342 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16 343 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT) 344 #define PLLX_MISC2_NDIV_NEW_SHIFT 8 345 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT) 346 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4) 347 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2) 348 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0) 349 350 #define PLLX_MISC3_IDDQ (0x1 << 3) 351 352 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE 353 #define PLLX_MISC0_WRITE_MASK 0x10c40000 354 #define PLLX_MISC1_DEFAULT_VALUE 0x20 355 #define PLLX_MISC1_WRITE_MASK 0x00ffffff 356 #define PLLX_MISC2_DEFAULT_VALUE 0x0 357 #define PLLX_MISC2_WRITE_MASK 0xffffff11 358 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ 359 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f 360 #define PLLX_MISC4_DEFAULT_VALUE 0x0 361 #define PLLX_MISC4_WRITE_MASK 0x8000ffff 362 #define PLLX_MISC5_DEFAULT_VALUE 0x0 363 #define PLLX_MISC5_WRITE_MASK 0x0000ffff 364 365 #define PLLX_HW_CTRL_CFG 0x548 366 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0) 367 368 /* PLLMB */ 369 #define PLLMB_BASE_LOCK (1 << 27) 370 371 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18) 372 #define PLLMB_MISC1_IDDQ (1 << 17) 373 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16) 374 375 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000 376 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff 377 378 /* PLLP */ 379 #define PLLP_BASE_OVERRIDE (1 << 28) 380 #define PLLP_BASE_LOCK (1 << 27) 381 382 #define PLLP_MISC0_LOCK_ENABLE (1 << 18) 383 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17) 384 #define PLLP_MISC0_IDDQ (1 << 3) 385 386 #define PLLP_MISC1_HSIO_EN_SHIFT 29 387 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT) 388 #define PLLP_MISC1_XUSB_EN_SHIFT 28 389 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT) 390 391 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008 392 #define PLLP_MISC1_DEFAULT_VALUE 0x0 393 394 #define PLLP_MISC0_WRITE_MASK 0xdc6000f 395 #define PLLP_MISC1_WRITE_MASK 0x70ffffff 396 397 /* PLLU */ 398 #define PLLU_BASE_LOCK (1 << 27) 399 #define PLLU_BASE_OVERRIDE (1 << 24) 400 #define PLLU_BASE_CLKENABLE_USB (1 << 21) 401 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22) 402 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23) 403 #define PLLU_BASE_CLKENABLE_48M (1 << 25) 404 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\ 405 PLLU_BASE_CLKENABLE_HSIC |\ 406 PLLU_BASE_CLKENABLE_ICUSB |\ 407 PLLU_BASE_CLKENABLE_48M) 408 409 #define PLLU_MISC0_IDDQ (1 << 31) 410 #define PLLU_MISC0_LOCK_ENABLE (1 << 29) 411 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0) 412 413 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000 414 #define PLLU_MISC1_DEFAULT_VALUE 0x0 415 416 #define PLLU_MISC0_WRITE_MASK 0xbfffffff 417 #define PLLU_MISC1_WRITE_MASK 0x00000007 418 419 static inline void _pll_misc_chk_default(void __iomem *base, 420 struct tegra_clk_pll_params *params, 421 u8 misc_num, u32 default_val, u32 mask) 422 { 423 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); 424 425 boot_val &= mask; 426 default_val &= mask; 427 if (boot_val != default_val) { 428 pr_warn("boot misc%d 0x%x: expected 0x%x\n", 429 misc_num, boot_val, default_val); 430 pr_warn(" (comparison mask = 0x%x)\n", mask); 431 params->defaults_set = false; 432 } 433 } 434 435 /* 436 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1 437 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition 438 * that changes NDIV only, while PLL is already locked. 439 */ 440 static void pllcx_check_defaults(struct tegra_clk_pll_params *params) 441 { 442 u32 default_val; 443 444 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET); 445 _pll_misc_chk_default(clk_base, params, 0, default_val, 446 PLLCX_MISC0_WRITE_MASK); 447 448 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ); 449 _pll_misc_chk_default(clk_base, params, 1, default_val, 450 PLLCX_MISC1_WRITE_MASK); 451 452 default_val = PLLCX_MISC2_DEFAULT_VALUE; 453 _pll_misc_chk_default(clk_base, params, 2, default_val, 454 PLLCX_MISC2_WRITE_MASK); 455 456 default_val = PLLCX_MISC3_DEFAULT_VALUE; 457 _pll_misc_chk_default(clk_base, params, 3, default_val, 458 PLLCX_MISC3_WRITE_MASK); 459 } 460 461 static void tegra210_pllcx_set_defaults(const char *name, 462 struct tegra_clk_pll *pllcx) 463 { 464 pllcx->params->defaults_set = true; 465 466 if (readl_relaxed(clk_base + pllcx->params->base_reg) & 467 PLL_ENABLE) { 468 /* PLL is ON: only check if defaults already set */ 469 pllcx_check_defaults(pllcx->params); 470 pr_warn("%s already enabled. Postponing set full defaults\n", 471 name); 472 return; 473 } 474 475 /* Defaults assert PLL reset, and set IDDQ */ 476 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE, 477 clk_base + pllcx->params->ext_misc_reg[0]); 478 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE, 479 clk_base + pllcx->params->ext_misc_reg[1]); 480 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE, 481 clk_base + pllcx->params->ext_misc_reg[2]); 482 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE, 483 clk_base + pllcx->params->ext_misc_reg[3]); 484 udelay(1); 485 } 486 487 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx) 488 { 489 tegra210_pllcx_set_defaults("PLL_C", pllcx); 490 } 491 492 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) 493 { 494 tegra210_pllcx_set_defaults("PLL_C2", pllcx); 495 } 496 497 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) 498 { 499 tegra210_pllcx_set_defaults("PLL_C3", pllcx); 500 } 501 502 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx) 503 { 504 tegra210_pllcx_set_defaults("PLL_A1", pllcx); 505 } 506 507 /* 508 * PLLA 509 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. 510 * Fractional SDM is allowed to provide exact audio rates. 511 */ 512 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) 513 { 514 u32 mask; 515 u32 val = readl_relaxed(clk_base + plla->params->base_reg); 516 517 plla->params->defaults_set = true; 518 519 if (val & PLL_ENABLE) { 520 /* 521 * PLL is ON: check if defaults already set, then set those 522 * that can be updated in flight. 523 */ 524 if (val & PLLA_BASE_IDDQ) { 525 pr_warn("PLL_A boot enabled with IDDQ set\n"); 526 plla->params->defaults_set = false; 527 } 528 529 pr_warn("PLL_A already enabled. Postponing set full defaults\n"); 530 531 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */ 532 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE; 533 _pll_misc_chk_default(clk_base, plla->params, 0, val, 534 ~mask & PLLA_MISC0_WRITE_MASK); 535 536 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */ 537 _pll_misc_chk_default(clk_base, plla->params, 2, val, 538 PLLA_MISC2_EN_DYNRAMP); 539 540 /* Enable lock detect */ 541 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); 542 val &= ~mask; 543 val |= PLLA_MISC0_DEFAULT_VALUE & mask; 544 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); 545 udelay(1); 546 547 return; 548 } 549 550 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */ 551 val |= PLLA_BASE_IDDQ; 552 writel_relaxed(val, clk_base + plla->params->base_reg); 553 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE, 554 clk_base + plla->params->ext_misc_reg[0]); 555 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE, 556 clk_base + plla->params->ext_misc_reg[2]); 557 udelay(1); 558 } 559 560 /* 561 * PLLD 562 * PLL with fractional SDM. 563 */ 564 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) 565 { 566 u32 val; 567 u32 mask = 0xffff; 568 569 plld->params->defaults_set = true; 570 571 if (readl_relaxed(clk_base + plld->params->base_reg) & 572 PLL_ENABLE) { 573 pr_warn("PLL_D already enabled. Postponing set full defaults\n"); 574 575 /* 576 * PLL is ON: check if defaults already set, then set those 577 * that can be updated in flight. 578 */ 579 val = PLLD_MISC1_DEFAULT_VALUE; 580 _pll_misc_chk_default(clk_base, plld->params, 1, 581 val, PLLD_MISC1_WRITE_MASK); 582 583 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */ 584 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ); 585 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE | 586 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM; 587 _pll_misc_chk_default(clk_base, plld->params, 0, val, 588 ~mask & PLLD_MISC0_WRITE_MASK); 589 590 /* Enable lock detect */ 591 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; 592 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); 593 val &= ~mask; 594 val |= PLLD_MISC0_DEFAULT_VALUE & mask; 595 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); 596 udelay(1); 597 598 return; 599 } 600 601 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); 602 val &= PLLD_MISC0_DSI_CLKENABLE; 603 val |= PLLD_MISC0_DEFAULT_VALUE; 604 /* set IDDQ, enable lock detect, disable SDM */ 605 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); 606 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + 607 plld->params->ext_misc_reg[1]); 608 udelay(1); 609 } 610 611 /* 612 * PLLD2, PLLDP 613 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used). 614 */ 615 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, 616 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val) 617 { 618 u32 default_val; 619 u32 val = readl_relaxed(clk_base + plldss->params->base_reg); 620 621 plldss->params->defaults_set = true; 622 623 if (val & PLL_ENABLE) { 624 pr_warn("%s already enabled. Postponing set full defaults\n", 625 pll_name); 626 627 /* 628 * PLL is ON: check if defaults already set, then set those 629 * that can be updated in flight. 630 */ 631 if (val & PLLDSS_BASE_IDDQ) { 632 pr_warn("plldss boot enabled with IDDQ set\n"); 633 plldss->params->defaults_set = false; 634 } 635 636 /* ignore lock enable */ 637 default_val = misc0_val; 638 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, 639 PLLDSS_MISC0_WRITE_MASK & 640 (~PLLDSS_MISC0_LOCK_ENABLE)); 641 642 /* 643 * If SSC is used, check all settings, otherwise just confirm 644 * that SSC is not used on boot as well. Do nothing when using 645 * this function for PLLC4 that has only MISC0. 646 */ 647 if (plldss->params->ssc_ctrl_en_mask) { 648 default_val = misc1_val; 649 _pll_misc_chk_default(clk_base, plldss->params, 1, 650 default_val, PLLDSS_MISC1_CFG_WRITE_MASK); 651 default_val = misc2_val; 652 _pll_misc_chk_default(clk_base, plldss->params, 2, 653 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK); 654 default_val = misc3_val; 655 _pll_misc_chk_default(clk_base, plldss->params, 3, 656 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK); 657 } else if (plldss->params->ext_misc_reg[1]) { 658 default_val = misc1_val; 659 _pll_misc_chk_default(clk_base, plldss->params, 1, 660 default_val, PLLDSS_MISC1_CFG_WRITE_MASK & 661 (~PLLDSS_MISC1_CFG_EN_SDM)); 662 } 663 664 /* Enable lock detect */ 665 if (val & PLLDSS_BASE_LOCK_OVERRIDE) { 666 val &= ~PLLDSS_BASE_LOCK_OVERRIDE; 667 writel_relaxed(val, clk_base + 668 plldss->params->base_reg); 669 } 670 671 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); 672 val &= ~PLLDSS_MISC0_LOCK_ENABLE; 673 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE; 674 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); 675 udelay(1); 676 677 return; 678 } 679 680 /* set IDDQ, enable lock detect, configure SDM/SSC */ 681 val |= PLLDSS_BASE_IDDQ; 682 val &= ~PLLDSS_BASE_LOCK_OVERRIDE; 683 writel_relaxed(val, clk_base + plldss->params->base_reg); 684 685 /* When using this function for PLLC4 exit here */ 686 if (!plldss->params->ext_misc_reg[1]) { 687 writel_relaxed(misc0_val, clk_base + 688 plldss->params->ext_misc_reg[0]); 689 udelay(1); 690 return; 691 } 692 693 writel_relaxed(misc0_val, clk_base + 694 plldss->params->ext_misc_reg[0]); 695 /* if SSC used set by 1st enable */ 696 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC), 697 clk_base + plldss->params->ext_misc_reg[1]); 698 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); 699 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); 700 udelay(1); 701 } 702 703 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) 704 { 705 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, 706 PLLD2_MISC1_CFG_DEFAULT_VALUE, 707 PLLD2_MISC2_CTRL1_DEFAULT_VALUE, 708 PLLD2_MISC3_CTRL2_DEFAULT_VALUE); 709 } 710 711 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) 712 { 713 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, 714 PLLDP_MISC1_CFG_DEFAULT_VALUE, 715 PLLDP_MISC2_CTRL1_DEFAULT_VALUE, 716 PLLDP_MISC3_CTRL2_DEFAULT_VALUE); 717 } 718 719 /* 720 * PLLC4 721 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. 722 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. 723 */ 724 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) 725 { 726 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); 727 } 728 729 /* 730 * PLLRE 731 * VCO is exposed to the clock tree directly along with post-divider output 732 */ 733 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) 734 { 735 u32 mask; 736 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); 737 738 pllre->params->defaults_set = true; 739 740 if (val & PLL_ENABLE) { 741 pr_warn("PLL_RE already enabled. Postponing set full defaults\n"); 742 743 /* 744 * PLL is ON: check if defaults already set, then set those 745 * that can be updated in flight. 746 */ 747 val &= PLLRE_BASE_DEFAULT_MASK; 748 if (val != PLLRE_BASE_DEFAULT_VALUE) { 749 pr_warn("pllre boot base 0x%x : expected 0x%x\n", 750 val, PLLRE_BASE_DEFAULT_VALUE); 751 pr_warn("(comparison mask = 0x%x)\n", 752 PLLRE_BASE_DEFAULT_MASK); 753 pllre->params->defaults_set = false; 754 } 755 756 /* Ignore lock enable */ 757 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ); 758 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE; 759 _pll_misc_chk_default(clk_base, pllre->params, 0, val, 760 ~mask & PLLRE_MISC0_WRITE_MASK); 761 762 /* Enable lock detect */ 763 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); 764 val &= ~mask; 765 val |= PLLRE_MISC0_DEFAULT_VALUE & mask; 766 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); 767 udelay(1); 768 769 return; 770 } 771 772 /* set IDDQ, enable lock detect */ 773 val &= ~PLLRE_BASE_DEFAULT_MASK; 774 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK; 775 writel_relaxed(val, clk_base + pllre->params->base_reg); 776 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE, 777 clk_base + pllre->params->ext_misc_reg[0]); 778 udelay(1); 779 } 780 781 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b) 782 { 783 unsigned long input_rate; 784 785 /* cf rate */ 786 if (!IS_ERR_OR_NULL(hw->clk)) 787 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 788 else 789 input_rate = 38400000; 790 791 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); 792 793 switch (input_rate) { 794 case 12000000: 795 case 12800000: 796 case 13000000: 797 *step_a = 0x2B; 798 *step_b = 0x0B; 799 return; 800 case 19200000: 801 *step_a = 0x12; 802 *step_b = 0x08; 803 return; 804 case 38400000: 805 *step_a = 0x04; 806 *step_b = 0x05; 807 return; 808 default: 809 pr_err("%s: Unexpected reference rate %lu\n", 810 __func__, input_rate); 811 BUG(); 812 } 813 } 814 815 static void pllx_check_defaults(struct tegra_clk_pll *pll) 816 { 817 u32 default_val; 818 819 default_val = PLLX_MISC0_DEFAULT_VALUE; 820 /* ignore lock enable */ 821 _pll_misc_chk_default(clk_base, pll->params, 0, default_val, 822 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE)); 823 824 default_val = PLLX_MISC1_DEFAULT_VALUE; 825 _pll_misc_chk_default(clk_base, pll->params, 1, default_val, 826 PLLX_MISC1_WRITE_MASK); 827 828 /* ignore all but control bit */ 829 default_val = PLLX_MISC2_DEFAULT_VALUE; 830 _pll_misc_chk_default(clk_base, pll->params, 2, 831 default_val, PLLX_MISC2_EN_DYNRAMP); 832 833 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ); 834 _pll_misc_chk_default(clk_base, pll->params, 3, default_val, 835 PLLX_MISC3_WRITE_MASK); 836 837 default_val = PLLX_MISC4_DEFAULT_VALUE; 838 _pll_misc_chk_default(clk_base, pll->params, 4, default_val, 839 PLLX_MISC4_WRITE_MASK); 840 841 default_val = PLLX_MISC5_DEFAULT_VALUE; 842 _pll_misc_chk_default(clk_base, pll->params, 5, default_val, 843 PLLX_MISC5_WRITE_MASK); 844 } 845 846 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) 847 { 848 u32 val; 849 u32 step_a, step_b; 850 851 pllx->params->defaults_set = true; 852 853 /* Get ready dyn ramp state machine settings */ 854 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b); 855 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) & 856 (~PLLX_MISC2_DYNRAMP_STEPB_MASK); 857 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; 858 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; 859 860 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { 861 pr_warn("PLL_X already enabled. Postponing set full defaults\n"); 862 863 /* 864 * PLL is ON: check if defaults already set, then set those 865 * that can be updated in flight. 866 */ 867 pllx_check_defaults(pllx); 868 869 /* Configure dyn ramp, disable lock override */ 870 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 871 872 /* Enable lock detect */ 873 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); 874 val &= ~PLLX_MISC0_LOCK_ENABLE; 875 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE; 876 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); 877 udelay(1); 878 879 return; 880 } 881 882 /* Enable lock detect and CPU output */ 883 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + 884 pllx->params->ext_misc_reg[0]); 885 886 /* Setup */ 887 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + 888 pllx->params->ext_misc_reg[1]); 889 890 /* Configure dyn ramp state machine, disable lock override */ 891 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 892 893 /* Set IDDQ */ 894 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + 895 pllx->params->ext_misc_reg[3]); 896 897 /* Disable SDM */ 898 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + 899 pllx->params->ext_misc_reg[4]); 900 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + 901 pllx->params->ext_misc_reg[5]); 902 udelay(1); 903 } 904 905 /* PLLMB */ 906 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) 907 { 908 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); 909 910 pllmb->params->defaults_set = true; 911 912 if (val & PLL_ENABLE) { 913 pr_warn("PLL_MB already enabled. Postponing set full defaults\n"); 914 915 /* 916 * PLL is ON: check if defaults already set, then set those 917 * that can be updated in flight. 918 */ 919 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); 920 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; 921 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, 922 ~mask & PLLMB_MISC1_WRITE_MASK); 923 924 /* Enable lock detect */ 925 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); 926 val &= ~mask; 927 val |= PLLMB_MISC1_DEFAULT_VALUE & mask; 928 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); 929 udelay(1); 930 931 return; 932 } 933 934 /* set IDDQ, enable lock detect */ 935 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE, 936 clk_base + pllmb->params->ext_misc_reg[0]); 937 udelay(1); 938 } 939 940 /* 941 * PLLP 942 * VCO is exposed to the clock tree directly along with post-divider output. 943 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz, 944 * respectively. 945 */ 946 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) 947 { 948 u32 val, mask; 949 950 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */ 951 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ); 952 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; 953 if (!enabled) 954 mask |= PLLP_MISC0_IDDQ; 955 _pll_misc_chk_default(clk_base, pll->params, 0, val, 956 ~mask & PLLP_MISC0_WRITE_MASK); 957 958 /* Ignore branch controls */ 959 val = PLLP_MISC1_DEFAULT_VALUE; 960 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; 961 _pll_misc_chk_default(clk_base, pll->params, 1, val, 962 ~mask & PLLP_MISC1_WRITE_MASK); 963 } 964 965 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) 966 { 967 u32 mask; 968 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); 969 970 pllp->params->defaults_set = true; 971 972 if (val & PLL_ENABLE) { 973 pr_warn("PLL_P already enabled. Postponing set full defaults\n"); 974 975 /* 976 * PLL is ON: check if defaults already set, then set those 977 * that can be updated in flight. 978 */ 979 pllp_check_defaults(pllp, true); 980 981 /* Enable lock detect */ 982 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); 983 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; 984 val &= ~mask; 985 val |= PLLP_MISC0_DEFAULT_VALUE & mask; 986 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); 987 udelay(1); 988 989 return; 990 } 991 992 /* set IDDQ, enable lock detect */ 993 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE, 994 clk_base + pllp->params->ext_misc_reg[0]); 995 996 /* Preserve branch control */ 997 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); 998 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; 999 val &= mask; 1000 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE; 1001 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); 1002 udelay(1); 1003 } 1004 1005 /* 1006 * PLLU 1007 * VCO is exposed to the clock tree directly along with post-divider output. 1008 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz, 1009 * respectively. 1010 */ 1011 static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control) 1012 { 1013 u32 val, mask; 1014 1015 /* Ignore lock enable (will be set) and IDDQ if under h/w control */ 1016 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); 1017 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); 1018 _pll_misc_chk_default(clk_base, pll->params, 0, val, 1019 ~mask & PLLU_MISC0_WRITE_MASK); 1020 1021 val = PLLU_MISC1_DEFAULT_VALUE; 1022 mask = PLLU_MISC1_LOCK_OVERRIDE; 1023 _pll_misc_chk_default(clk_base, pll->params, 1, val, 1024 ~mask & PLLU_MISC1_WRITE_MASK); 1025 } 1026 1027 static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) 1028 { 1029 u32 val = readl_relaxed(clk_base + pllu->params->base_reg); 1030 1031 pllu->params->defaults_set = true; 1032 1033 if (val & PLL_ENABLE) { 1034 pr_warn("PLL_U already enabled. Postponing set full defaults\n"); 1035 1036 /* 1037 * PLL is ON: check if defaults already set, then set those 1038 * that can be updated in flight. 1039 */ 1040 pllu_check_defaults(pllu, false); 1041 1042 /* Enable lock detect */ 1043 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]); 1044 val &= ~PLLU_MISC0_LOCK_ENABLE; 1045 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; 1046 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[0]); 1047 1048 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[1]); 1049 val &= ~PLLU_MISC1_LOCK_OVERRIDE; 1050 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; 1051 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[1]); 1052 udelay(1); 1053 1054 return; 1055 } 1056 1057 /* set IDDQ, enable lock detect */ 1058 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE, 1059 clk_base + pllu->params->ext_misc_reg[0]); 1060 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE, 1061 clk_base + pllu->params->ext_misc_reg[1]); 1062 udelay(1); 1063 } 1064 1065 #define mask(w) ((1 << (w)) - 1) 1066 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 1067 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 1068 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 1069 mask(p->params->div_nmp->divp_width)) 1070 1071 #define divm_shift(p) ((p)->params->div_nmp->divm_shift) 1072 #define divn_shift(p) ((p)->params->div_nmp->divn_shift) 1073 #define divp_shift(p) ((p)->params->div_nmp->divp_shift) 1074 1075 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 1076 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 1077 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 1078 1079 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */ 1080 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll, 1081 u32 reg, u32 mask) 1082 { 1083 int i; 1084 u32 val = 0; 1085 1086 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { 1087 udelay(PLL_LOCKDET_DELAY); 1088 val = readl_relaxed(clk_base + reg); 1089 if ((val & mask) == mask) { 1090 udelay(PLL_LOCKDET_DELAY); 1091 return 0; 1092 } 1093 } 1094 return -ETIMEDOUT; 1095 } 1096 1097 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx, 1098 struct tegra_clk_pll_freq_table *cfg) 1099 { 1100 u32 val, base, ndiv_new_mask; 1101 1102 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift) 1103 << PLLX_MISC2_NDIV_NEW_SHIFT; 1104 1105 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); 1106 val &= (~ndiv_new_mask); 1107 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT; 1108 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1109 udelay(1); 1110 1111 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); 1112 val |= PLLX_MISC2_EN_DYNRAMP; 1113 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1114 udelay(1); 1115 1116 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], 1117 PLLX_MISC2_DYNRAMP_DONE); 1118 1119 base = readl_relaxed(clk_base + pllx->params->base_reg) & 1120 (~divn_mask_shifted(pllx)); 1121 base |= cfg->n << pllx->params->div_nmp->divn_shift; 1122 writel_relaxed(base, clk_base + pllx->params->base_reg); 1123 udelay(1); 1124 1125 val &= ~PLLX_MISC2_EN_DYNRAMP; 1126 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1127 udelay(1); 1128 1129 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n", 1130 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p, 1131 cfg->input_rate / cfg->m * cfg->n / 1132 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); 1133 1134 return 0; 1135 } 1136 1137 /* 1138 * Common configuration for PLLs with fixed input divider policy: 1139 * - always set fixed M-value based on the reference rate 1140 * - always set P-value value 1:1 for output rates above VCO minimum, and 1141 * choose minimum necessary P-value for output rates below VCO maximum 1142 * - calculate N-value based on selected M and P 1143 * - calculate SDM_DIN fractional part 1144 */ 1145 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, 1146 struct tegra_clk_pll_freq_table *cfg, 1147 unsigned long rate, unsigned long input_rate) 1148 { 1149 struct tegra_clk_pll *pll = to_clk_pll(hw); 1150 struct tegra_clk_pll_params *params = pll->params; 1151 int p; 1152 unsigned long cf, p_rate; 1153 u32 pdiv; 1154 1155 if (!rate) 1156 return -EINVAL; 1157 1158 if (!(params->flags & TEGRA_PLL_VCO_OUT)) { 1159 p = DIV_ROUND_UP(params->vco_min, rate); 1160 p = params->round_p_to_pdiv(p, &pdiv); 1161 } else { 1162 p = rate >= params->vco_min ? 1 : -EINVAL; 1163 } 1164 1165 if (IS_ERR_VALUE(p)) 1166 return -EINVAL; 1167 1168 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); 1169 cfg->p = p; 1170 1171 /* Store P as HW value, as that is what is expected */ 1172 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p); 1173 1174 p_rate = rate * p; 1175 if (p_rate > params->vco_max) 1176 p_rate = params->vco_max; 1177 cf = input_rate / cfg->m; 1178 cfg->n = p_rate / cf; 1179 1180 cfg->sdm_data = 0; 1181 if (params->sdm_ctrl_reg) { 1182 unsigned long rem = p_rate - cf * cfg->n; 1183 /* If ssc is enabled SDM enabled as well, even for integer n */ 1184 if (rem || params->ssc_ctrl_reg) { 1185 u64 s = rem * PLL_SDM_COEFF; 1186 1187 do_div(s, cf); 1188 s -= PLL_SDM_COEFF / 2; 1189 cfg->sdm_data = sdin_din_to_data(s); 1190 } 1191 } 1192 1193 cfg->input_rate = input_rate; 1194 cfg->output_rate = rate; 1195 1196 return 0; 1197 } 1198 1199 /* 1200 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate 1201 * 1202 * @cfg: struct tegra_clk_pll_freq_table * cfg 1203 * 1204 * For Normal mode: 1205 * Fvco = Fref * NDIV / MDIV 1206 * 1207 * For fractional mode: 1208 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV 1209 */ 1210 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) 1211 { 1212 cfg->n = cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 + 1213 sdin_data_to_din(cfg->sdm_data); 1214 cfg->m *= PLL_SDM_COEFF; 1215 } 1216 1217 static unsigned long 1218 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, 1219 unsigned long parent_rate) 1220 { 1221 unsigned long vco_min = params->vco_min; 1222 1223 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF); 1224 vco_min = min(vco_min, params->vco_min); 1225 1226 return vco_min; 1227 } 1228 1229 static struct div_nmp pllx_nmp = { 1230 .divm_shift = 0, 1231 .divm_width = 8, 1232 .divn_shift = 8, 1233 .divn_width = 8, 1234 .divp_shift = 20, 1235 .divp_width = 5, 1236 }; 1237 /* 1238 * PLL post divider maps - two types: quasi-linear and exponential 1239 * post divider. 1240 */ 1241 #define PLL_QLIN_PDIV_MAX 16 1242 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = { 1243 { .pdiv = 1, .hw_val = 0 }, 1244 { .pdiv = 2, .hw_val = 1 }, 1245 { .pdiv = 3, .hw_val = 2 }, 1246 { .pdiv = 4, .hw_val = 3 }, 1247 { .pdiv = 5, .hw_val = 4 }, 1248 { .pdiv = 6, .hw_val = 5 }, 1249 { .pdiv = 8, .hw_val = 6 }, 1250 { .pdiv = 9, .hw_val = 7 }, 1251 { .pdiv = 10, .hw_val = 8 }, 1252 { .pdiv = 12, .hw_val = 9 }, 1253 { .pdiv = 15, .hw_val = 10 }, 1254 { .pdiv = 16, .hw_val = 11 }, 1255 { .pdiv = 18, .hw_val = 12 }, 1256 { .pdiv = 20, .hw_val = 13 }, 1257 { .pdiv = 24, .hw_val = 14 }, 1258 { .pdiv = 30, .hw_val = 15 }, 1259 { .pdiv = 32, .hw_val = 16 }, 1260 }; 1261 1262 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv) 1263 { 1264 int i; 1265 1266 if (p) { 1267 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) { 1268 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) { 1269 if (pdiv) 1270 *pdiv = i; 1271 return pll_qlin_pdiv_to_hw[i].pdiv; 1272 } 1273 } 1274 } 1275 1276 return -EINVAL; 1277 } 1278 1279 #define PLL_EXPO_PDIV_MAX 7 1280 static const struct pdiv_map pll_expo_pdiv_to_hw[] = { 1281 { .pdiv = 1, .hw_val = 0 }, 1282 { .pdiv = 2, .hw_val = 1 }, 1283 { .pdiv = 4, .hw_val = 2 }, 1284 { .pdiv = 8, .hw_val = 3 }, 1285 { .pdiv = 16, .hw_val = 4 }, 1286 { .pdiv = 32, .hw_val = 5 }, 1287 { .pdiv = 64, .hw_val = 6 }, 1288 { .pdiv = 128, .hw_val = 7 }, 1289 }; 1290 1291 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) 1292 { 1293 if (p) { 1294 u32 i = fls(p); 1295 1296 if (i == ffs(p)) 1297 i--; 1298 1299 if (i <= PLL_EXPO_PDIV_MAX) { 1300 if (pdiv) 1301 *pdiv = i; 1302 return 1 << i; 1303 } 1304 } 1305 return -EINVAL; 1306 } 1307 1308 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 1309 /* 1 GHz */ 1310 { 12000000, 1000000000, 166, 1, 1, 0 }, /* actual: 996.0 MHz */ 1311 { 13000000, 1000000000, 153, 1, 1, 0 }, /* actual: 994.0 MHz */ 1312 { 38400000, 1000000000, 156, 3, 1, 0 }, /* actual: 998.4 MHz */ 1313 { 0, 0, 0, 0, 0, 0 }, 1314 }; 1315 1316 static struct tegra_clk_pll_params pll_x_params = { 1317 .input_min = 12000000, 1318 .input_max = 800000000, 1319 .cf_min = 12000000, 1320 .cf_max = 38400000, 1321 .vco_min = 1350000000, 1322 .vco_max = 3000000000UL, 1323 .base_reg = PLLX_BASE, 1324 .misc_reg = PLLX_MISC0, 1325 .lock_mask = PLL_BASE_LOCK, 1326 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 1327 .lock_delay = 300, 1328 .ext_misc_reg[0] = PLLX_MISC0, 1329 .ext_misc_reg[1] = PLLX_MISC1, 1330 .ext_misc_reg[2] = PLLX_MISC2, 1331 .ext_misc_reg[3] = PLLX_MISC3, 1332 .ext_misc_reg[4] = PLLX_MISC4, 1333 .ext_misc_reg[5] = PLLX_MISC5, 1334 .iddq_reg = PLLX_MISC3, 1335 .iddq_bit_idx = PLLXP_IDDQ_BIT, 1336 .max_p = PLL_QLIN_PDIV_MAX, 1337 .mdiv_default = 2, 1338 .dyn_ramp_reg = PLLX_MISC2, 1339 .stepa_shift = 16, 1340 .stepb_shift = 24, 1341 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1342 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1343 .div_nmp = &pllx_nmp, 1344 .freq_table = pll_x_freq_table, 1345 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1346 .dyn_ramp = tegra210_pllx_dyn_ramp, 1347 .set_defaults = tegra210_pllx_set_defaults, 1348 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1349 }; 1350 1351 static struct div_nmp pllc_nmp = { 1352 .divm_shift = 0, 1353 .divm_width = 8, 1354 .divn_shift = 10, 1355 .divn_width = 8, 1356 .divp_shift = 20, 1357 .divp_width = 5, 1358 }; 1359 1360 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 1361 { 12000000, 510000000, 85, 1, 1, 0 }, 1362 { 13000000, 510000000, 78, 1, 1, 0 }, /* actual: 507.0 MHz */ 1363 { 38400000, 510000000, 79, 3, 1, 0 }, /* actual: 505.6 MHz */ 1364 { 0, 0, 0, 0, 0, 0 }, 1365 }; 1366 1367 static struct tegra_clk_pll_params pll_c_params = { 1368 .input_min = 12000000, 1369 .input_max = 700000000, 1370 .cf_min = 12000000, 1371 .cf_max = 50000000, 1372 .vco_min = 600000000, 1373 .vco_max = 1200000000, 1374 .base_reg = PLLC_BASE, 1375 .misc_reg = PLLC_MISC0, 1376 .lock_mask = PLL_BASE_LOCK, 1377 .lock_delay = 300, 1378 .iddq_reg = PLLC_MISC1, 1379 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1380 .reset_reg = PLLC_MISC0, 1381 .reset_bit_idx = PLLCX_RESET_BIT, 1382 .max_p = PLL_QLIN_PDIV_MAX, 1383 .ext_misc_reg[0] = PLLC_MISC0, 1384 .ext_misc_reg[1] = PLLC_MISC1, 1385 .ext_misc_reg[2] = PLLC_MISC2, 1386 .ext_misc_reg[3] = PLLC_MISC3, 1387 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1388 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1389 .mdiv_default = 3, 1390 .div_nmp = &pllc_nmp, 1391 .freq_table = pll_cx_freq_table, 1392 .flags = TEGRA_PLL_USE_LOCK, 1393 .set_defaults = _pllc_set_defaults, 1394 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1395 }; 1396 1397 static struct div_nmp pllcx_nmp = { 1398 .divm_shift = 0, 1399 .divm_width = 8, 1400 .divn_shift = 10, 1401 .divn_width = 8, 1402 .divp_shift = 20, 1403 .divp_width = 5, 1404 }; 1405 1406 static struct tegra_clk_pll_params pll_c2_params = { 1407 .input_min = 12000000, 1408 .input_max = 700000000, 1409 .cf_min = 12000000, 1410 .cf_max = 50000000, 1411 .vco_min = 600000000, 1412 .vco_max = 1200000000, 1413 .base_reg = PLLC2_BASE, 1414 .misc_reg = PLLC2_MISC0, 1415 .iddq_reg = PLLC2_MISC1, 1416 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1417 .reset_reg = PLLC2_MISC0, 1418 .reset_bit_idx = PLLCX_RESET_BIT, 1419 .lock_mask = PLLCX_BASE_LOCK, 1420 .lock_delay = 300, 1421 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1422 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1423 .mdiv_default = 3, 1424 .div_nmp = &pllcx_nmp, 1425 .max_p = PLL_QLIN_PDIV_MAX, 1426 .ext_misc_reg[0] = PLLC2_MISC0, 1427 .ext_misc_reg[1] = PLLC2_MISC1, 1428 .ext_misc_reg[2] = PLLC2_MISC2, 1429 .ext_misc_reg[3] = PLLC2_MISC3, 1430 .freq_table = pll_cx_freq_table, 1431 .flags = TEGRA_PLL_USE_LOCK, 1432 .set_defaults = _pllc2_set_defaults, 1433 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1434 }; 1435 1436 static struct tegra_clk_pll_params pll_c3_params = { 1437 .input_min = 12000000, 1438 .input_max = 700000000, 1439 .cf_min = 12000000, 1440 .cf_max = 50000000, 1441 .vco_min = 600000000, 1442 .vco_max = 1200000000, 1443 .base_reg = PLLC3_BASE, 1444 .misc_reg = PLLC3_MISC0, 1445 .lock_mask = PLLCX_BASE_LOCK, 1446 .lock_delay = 300, 1447 .iddq_reg = PLLC3_MISC1, 1448 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1449 .reset_reg = PLLC3_MISC0, 1450 .reset_bit_idx = PLLCX_RESET_BIT, 1451 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1452 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1453 .mdiv_default = 3, 1454 .div_nmp = &pllcx_nmp, 1455 .max_p = PLL_QLIN_PDIV_MAX, 1456 .ext_misc_reg[0] = PLLC3_MISC0, 1457 .ext_misc_reg[1] = PLLC3_MISC1, 1458 .ext_misc_reg[2] = PLLC3_MISC2, 1459 .ext_misc_reg[3] = PLLC3_MISC3, 1460 .freq_table = pll_cx_freq_table, 1461 .flags = TEGRA_PLL_USE_LOCK, 1462 .set_defaults = _pllc3_set_defaults, 1463 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1464 }; 1465 1466 static struct div_nmp pllss_nmp = { 1467 .divm_shift = 0, 1468 .divm_width = 8, 1469 .divn_shift = 8, 1470 .divn_width = 8, 1471 .divp_shift = 19, 1472 .divp_width = 5, 1473 }; 1474 1475 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = { 1476 { 12000000, 600000000, 50, 1, 0, 0 }, 1477 { 13000000, 600000000, 46, 1, 0, 0 }, /* actual: 598.0 MHz */ 1478 { 38400000, 600000000, 62, 4, 0, 0 }, /* actual: 595.2 MHz */ 1479 { 0, 0, 0, 0, 0, 0 }, 1480 }; 1481 1482 static const struct clk_div_table pll_vco_post_div_table[] = { 1483 { .val = 0, .div = 1 }, 1484 { .val = 1, .div = 2 }, 1485 { .val = 2, .div = 3 }, 1486 { .val = 3, .div = 4 }, 1487 { .val = 4, .div = 5 }, 1488 { .val = 5, .div = 6 }, 1489 { .val = 6, .div = 8 }, 1490 { .val = 7, .div = 10 }, 1491 { .val = 8, .div = 12 }, 1492 { .val = 9, .div = 16 }, 1493 { .val = 10, .div = 12 }, 1494 { .val = 11, .div = 16 }, 1495 { .val = 12, .div = 20 }, 1496 { .val = 13, .div = 24 }, 1497 { .val = 14, .div = 32 }, 1498 { .val = 0, .div = 0 }, 1499 }; 1500 1501 static struct tegra_clk_pll_params pll_c4_vco_params = { 1502 .input_min = 9600000, 1503 .input_max = 800000000, 1504 .cf_min = 9600000, 1505 .cf_max = 19200000, 1506 .vco_min = 500000000, 1507 .vco_max = 1080000000, 1508 .base_reg = PLLC4_BASE, 1509 .misc_reg = PLLC4_MISC0, 1510 .lock_mask = PLL_BASE_LOCK, 1511 .lock_delay = 300, 1512 .max_p = PLL_QLIN_PDIV_MAX, 1513 .ext_misc_reg[0] = PLLC4_MISC0, 1514 .iddq_reg = PLLC4_BASE, 1515 .iddq_bit_idx = PLLSS_IDDQ_BIT, 1516 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1517 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1518 .mdiv_default = 3, 1519 .div_nmp = &pllss_nmp, 1520 .freq_table = pll_c4_vco_freq_table, 1521 .set_defaults = tegra210_pllc4_set_defaults, 1522 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1523 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1524 }; 1525 1526 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 1527 { 12000000, 800000000, 66, 1, 0, 0 }, /* actual: 792.0 MHz */ 1528 { 13000000, 800000000, 61, 1, 0, 0 }, /* actual: 793.0 MHz */ 1529 { 38400000, 297600000, 93, 4, 2, 0 }, 1530 { 38400000, 400000000, 125, 4, 2, 0 }, 1531 { 38400000, 532800000, 111, 4, 1, 0 }, 1532 { 38400000, 665600000, 104, 3, 1, 0 }, 1533 { 38400000, 800000000, 125, 3, 1, 0 }, 1534 { 38400000, 931200000, 97, 4, 0, 0 }, 1535 { 38400000, 1065600000, 111, 4, 0, 0 }, 1536 { 38400000, 1200000000, 125, 4, 0, 0 }, 1537 { 38400000, 1331200000, 104, 3, 0, 0 }, 1538 { 38400000, 1459200000, 76, 2, 0, 0 }, 1539 { 38400000, 1600000000, 125, 3, 0, 0 }, 1540 { 0, 0, 0, 0, 0, 0 }, 1541 }; 1542 1543 static struct div_nmp pllm_nmp = { 1544 .divm_shift = 0, 1545 .divm_width = 8, 1546 .override_divm_shift = 0, 1547 .divn_shift = 8, 1548 .divn_width = 8, 1549 .override_divn_shift = 8, 1550 .divp_shift = 20, 1551 .divp_width = 5, 1552 .override_divp_shift = 27, 1553 }; 1554 1555 static struct tegra_clk_pll_params pll_m_params = { 1556 .input_min = 9600000, 1557 .input_max = 500000000, 1558 .cf_min = 9600000, 1559 .cf_max = 19200000, 1560 .vco_min = 800000000, 1561 .vco_max = 1866000000, 1562 .base_reg = PLLM_BASE, 1563 .misc_reg = PLLM_MISC2, 1564 .lock_mask = PLL_BASE_LOCK, 1565 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, 1566 .lock_delay = 300, 1567 .iddq_reg = PLLM_MISC2, 1568 .iddq_bit_idx = PLLM_IDDQ_BIT, 1569 .max_p = PLL_QLIN_PDIV_MAX, 1570 .ext_misc_reg[0] = PLLM_MISC2, 1571 .ext_misc_reg[1] = PLLM_MISC1, 1572 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1573 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1574 .div_nmp = &pllm_nmp, 1575 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 1576 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 1577 .freq_table = pll_m_freq_table, 1578 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1579 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1580 }; 1581 1582 static struct tegra_clk_pll_params pll_mb_params = { 1583 .input_min = 9600000, 1584 .input_max = 500000000, 1585 .cf_min = 9600000, 1586 .cf_max = 19200000, 1587 .vco_min = 800000000, 1588 .vco_max = 1866000000, 1589 .base_reg = PLLMB_BASE, 1590 .misc_reg = PLLMB_MISC1, 1591 .lock_mask = PLL_BASE_LOCK, 1592 .lock_delay = 300, 1593 .iddq_reg = PLLMB_MISC1, 1594 .iddq_bit_idx = PLLMB_IDDQ_BIT, 1595 .max_p = PLL_QLIN_PDIV_MAX, 1596 .ext_misc_reg[0] = PLLMB_MISC1, 1597 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1598 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1599 .div_nmp = &pllm_nmp, 1600 .freq_table = pll_m_freq_table, 1601 .flags = TEGRA_PLL_USE_LOCK, 1602 .set_defaults = tegra210_pllmb_set_defaults, 1603 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1604 }; 1605 1606 1607 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 1608 /* PLLE special case: use cpcon field to store cml divider value */ 1609 { 672000000, 100000000, 125, 42, 0, 13 }, 1610 { 624000000, 100000000, 125, 39, 0, 13 }, 1611 { 336000000, 100000000, 125, 21, 0, 13 }, 1612 { 312000000, 100000000, 200, 26, 0, 14 }, 1613 { 38400000, 100000000, 125, 2, 0, 14 }, 1614 { 12000000, 100000000, 200, 1, 0, 14 }, 1615 { 0, 0, 0, 0, 0, 0 }, 1616 }; 1617 1618 static struct div_nmp plle_nmp = { 1619 .divm_shift = 0, 1620 .divm_width = 8, 1621 .divn_shift = 8, 1622 .divn_width = 8, 1623 .divp_shift = 24, 1624 .divp_width = 5, 1625 }; 1626 1627 static struct tegra_clk_pll_params pll_e_params = { 1628 .input_min = 12000000, 1629 .input_max = 800000000, 1630 .cf_min = 12000000, 1631 .cf_max = 38400000, 1632 .vco_min = 1600000000, 1633 .vco_max = 2500000000U, 1634 .base_reg = PLLE_BASE, 1635 .misc_reg = PLLE_MISC0, 1636 .aux_reg = PLLE_AUX, 1637 .lock_mask = PLLE_MISC_LOCK, 1638 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 1639 .lock_delay = 300, 1640 .div_nmp = &plle_nmp, 1641 .freq_table = pll_e_freq_table, 1642 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK | 1643 TEGRA_PLL_HAS_LOCK_ENABLE, 1644 .fixed_rate = 100000000, 1645 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1646 }; 1647 1648 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = { 1649 { 12000000, 672000000, 56, 1, 0, 0 }, 1650 { 13000000, 672000000, 51, 1, 0, 0 }, /* actual: 663.0 MHz */ 1651 { 38400000, 672000000, 70, 4, 0, 0 }, 1652 { 0, 0, 0, 0, 0, 0 }, 1653 }; 1654 1655 static struct div_nmp pllre_nmp = { 1656 .divm_shift = 0, 1657 .divm_width = 8, 1658 .divn_shift = 8, 1659 .divn_width = 8, 1660 .divp_shift = 16, 1661 .divp_width = 5, 1662 }; 1663 1664 static struct tegra_clk_pll_params pll_re_vco_params = { 1665 .input_min = 9600000, 1666 .input_max = 800000000, 1667 .cf_min = 9600000, 1668 .cf_max = 19200000, 1669 .vco_min = 350000000, 1670 .vco_max = 700000000, 1671 .base_reg = PLLRE_BASE, 1672 .misc_reg = PLLRE_MISC0, 1673 .lock_mask = PLLRE_MISC_LOCK, 1674 .lock_delay = 300, 1675 .max_p = PLL_QLIN_PDIV_MAX, 1676 .ext_misc_reg[0] = PLLRE_MISC0, 1677 .iddq_reg = PLLRE_MISC0, 1678 .iddq_bit_idx = PLLRE_IDDQ_BIT, 1679 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1680 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1681 .div_nmp = &pllre_nmp, 1682 .freq_table = pll_re_vco_freq_table, 1683 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT, 1684 .set_defaults = tegra210_pllre_set_defaults, 1685 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1686 }; 1687 1688 static struct div_nmp pllp_nmp = { 1689 .divm_shift = 0, 1690 .divm_width = 8, 1691 .divn_shift = 10, 1692 .divn_width = 8, 1693 .divp_shift = 20, 1694 .divp_width = 5, 1695 }; 1696 1697 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 1698 { 12000000, 408000000, 34, 1, 0, 0 }, 1699 { 38400000, 408000000, 85, 8, 0, 0 }, /* cf = 4.8MHz, allowed exception */ 1700 { 0, 0, 0, 0, 0, 0 }, 1701 }; 1702 1703 static struct tegra_clk_pll_params pll_p_params = { 1704 .input_min = 9600000, 1705 .input_max = 800000000, 1706 .cf_min = 9600000, 1707 .cf_max = 19200000, 1708 .vco_min = 350000000, 1709 .vco_max = 700000000, 1710 .base_reg = PLLP_BASE, 1711 .misc_reg = PLLP_MISC0, 1712 .lock_mask = PLL_BASE_LOCK, 1713 .lock_delay = 300, 1714 .iddq_reg = PLLP_MISC0, 1715 .iddq_bit_idx = PLLXP_IDDQ_BIT, 1716 .ext_misc_reg[0] = PLLP_MISC0, 1717 .ext_misc_reg[1] = PLLP_MISC1, 1718 .div_nmp = &pllp_nmp, 1719 .freq_table = pll_p_freq_table, 1720 .fixed_rate = 408000000, 1721 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1722 .set_defaults = tegra210_pllp_set_defaults, 1723 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1724 }; 1725 1726 static struct tegra_clk_pll_params pll_a1_params = { 1727 .input_min = 12000000, 1728 .input_max = 700000000, 1729 .cf_min = 12000000, 1730 .cf_max = 50000000, 1731 .vco_min = 600000000, 1732 .vco_max = 1200000000, 1733 .base_reg = PLLA1_BASE, 1734 .misc_reg = PLLA1_MISC0, 1735 .lock_mask = PLLCX_BASE_LOCK, 1736 .lock_delay = 300, 1737 .iddq_reg = PLLA1_MISC0, 1738 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1739 .reset_reg = PLLA1_MISC0, 1740 .reset_bit_idx = PLLCX_RESET_BIT, 1741 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1742 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1743 .div_nmp = &pllc_nmp, 1744 .ext_misc_reg[0] = PLLA1_MISC0, 1745 .ext_misc_reg[1] = PLLA1_MISC1, 1746 .ext_misc_reg[2] = PLLA1_MISC2, 1747 .ext_misc_reg[3] = PLLA1_MISC3, 1748 .freq_table = pll_cx_freq_table, 1749 .flags = TEGRA_PLL_USE_LOCK, 1750 .set_defaults = _plla1_set_defaults, 1751 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1752 }; 1753 1754 static struct div_nmp plla_nmp = { 1755 .divm_shift = 0, 1756 .divm_width = 8, 1757 .divn_shift = 8, 1758 .divn_width = 8, 1759 .divp_shift = 20, 1760 .divp_width = 5, 1761 }; 1762 1763 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 1764 { 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */ 1765 { 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */ 1766 { 12000000, 240000000, 60, 1, 2, 1, 0 }, 1767 { 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */ 1768 { 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */ 1769 { 13000000, 240000000, 55, 1, 2, 1, 0 }, /* actual: 238.3 MHz */ 1770 { 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */ 1771 { 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */ 1772 { 38400000, 240000000, 75, 3, 3, 1, 0 }, 1773 { 0, 0, 0, 0, 0, 0, 0 }, 1774 }; 1775 1776 static struct tegra_clk_pll_params pll_a_params = { 1777 .input_min = 12000000, 1778 .input_max = 800000000, 1779 .cf_min = 12000000, 1780 .cf_max = 19200000, 1781 .vco_min = 500000000, 1782 .vco_max = 1000000000, 1783 .base_reg = PLLA_BASE, 1784 .misc_reg = PLLA_MISC0, 1785 .lock_mask = PLL_BASE_LOCK, 1786 .lock_delay = 300, 1787 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1788 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1789 .iddq_reg = PLLA_BASE, 1790 .iddq_bit_idx = PLLA_IDDQ_BIT, 1791 .div_nmp = &plla_nmp, 1792 .sdm_din_reg = PLLA_MISC1, 1793 .sdm_din_mask = PLLA_SDM_DIN_MASK, 1794 .sdm_ctrl_reg = PLLA_MISC2, 1795 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK, 1796 .ext_misc_reg[0] = PLLA_MISC0, 1797 .ext_misc_reg[1] = PLLA_MISC1, 1798 .ext_misc_reg[2] = PLLA_MISC2, 1799 .freq_table = pll_a_freq_table, 1800 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW, 1801 .set_defaults = tegra210_plla_set_defaults, 1802 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1803 .set_gain = tegra210_clk_pll_set_gain, 1804 .adjust_vco = tegra210_clk_adjust_vco_min, 1805 }; 1806 1807 static struct div_nmp plld_nmp = { 1808 .divm_shift = 0, 1809 .divm_width = 8, 1810 .divn_shift = 11, 1811 .divn_width = 8, 1812 .divp_shift = 20, 1813 .divp_width = 3, 1814 }; 1815 1816 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 1817 { 12000000, 594000000, 99, 1, 1, 0, 0 }, 1818 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */ 1819 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 }, 1820 { 0, 0, 0, 0, 0, 0, 0 }, 1821 }; 1822 1823 static struct tegra_clk_pll_params pll_d_params = { 1824 .input_min = 12000000, 1825 .input_max = 800000000, 1826 .cf_min = 12000000, 1827 .cf_max = 38400000, 1828 .vco_min = 750000000, 1829 .vco_max = 1500000000, 1830 .base_reg = PLLD_BASE, 1831 .misc_reg = PLLD_MISC0, 1832 .lock_mask = PLL_BASE_LOCK, 1833 .lock_delay = 1000, 1834 .iddq_reg = PLLD_MISC0, 1835 .iddq_bit_idx = PLLD_IDDQ_BIT, 1836 .round_p_to_pdiv = pll_expo_p_to_pdiv, 1837 .pdiv_tohw = pll_expo_pdiv_to_hw, 1838 .div_nmp = &plld_nmp, 1839 .sdm_din_reg = PLLD_MISC0, 1840 .sdm_din_mask = PLLA_SDM_DIN_MASK, 1841 .sdm_ctrl_reg = PLLD_MISC0, 1842 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK, 1843 .ext_misc_reg[0] = PLLD_MISC0, 1844 .ext_misc_reg[1] = PLLD_MISC1, 1845 .freq_table = pll_d_freq_table, 1846 .flags = TEGRA_PLL_USE_LOCK, 1847 .mdiv_default = 1, 1848 .set_defaults = tegra210_plld_set_defaults, 1849 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1850 .set_gain = tegra210_clk_pll_set_gain, 1851 .adjust_vco = tegra210_clk_adjust_vco_min, 1852 }; 1853 1854 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = { 1855 { 12000000, 594000000, 99, 1, 1, 0, 0xf000 }, 1856 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */ 1857 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 }, 1858 { 0, 0, 0, 0, 0, 0, 0 }, 1859 }; 1860 1861 /* s/w policy, always tegra_pll_ref */ 1862 static struct tegra_clk_pll_params pll_d2_params = { 1863 .input_min = 12000000, 1864 .input_max = 800000000, 1865 .cf_min = 12000000, 1866 .cf_max = 38400000, 1867 .vco_min = 750000000, 1868 .vco_max = 1500000000, 1869 .base_reg = PLLD2_BASE, 1870 .misc_reg = PLLD2_MISC0, 1871 .lock_mask = PLL_BASE_LOCK, 1872 .lock_delay = 300, 1873 .iddq_reg = PLLD2_BASE, 1874 .iddq_bit_idx = PLLSS_IDDQ_BIT, 1875 .sdm_din_reg = PLLD2_MISC3, 1876 .sdm_din_mask = PLLA_SDM_DIN_MASK, 1877 .sdm_ctrl_reg = PLLD2_MISC1, 1878 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK, 1879 .ssc_ctrl_reg = PLLD2_MISC1, 1880 .ssc_ctrl_en_mask = PLLD2_SSC_EN_MASK, 1881 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1882 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1883 .div_nmp = &pllss_nmp, 1884 .ext_misc_reg[0] = PLLD2_MISC0, 1885 .ext_misc_reg[1] = PLLD2_MISC1, 1886 .ext_misc_reg[2] = PLLD2_MISC2, 1887 .ext_misc_reg[3] = PLLD2_MISC3, 1888 .max_p = PLL_QLIN_PDIV_MAX, 1889 .mdiv_default = 1, 1890 .freq_table = tegra210_pll_d2_freq_table, 1891 .set_defaults = tegra210_plld2_set_defaults, 1892 .flags = TEGRA_PLL_USE_LOCK, 1893 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1894 .set_gain = tegra210_clk_pll_set_gain, 1895 .adjust_vco = tegra210_clk_adjust_vco_min, 1896 }; 1897 1898 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 1899 { 12000000, 270000000, 90, 1, 3, 0, 0xf000 }, 1900 { 13000000, 270000000, 83, 1, 3, 0, 0xf000 }, /* actual: 269.8 MHz */ 1901 { 38400000, 270000000, 28, 1, 3, 0, 0xf400 }, 1902 { 0, 0, 0, 0, 0, 0, 0 }, 1903 }; 1904 1905 static struct tegra_clk_pll_params pll_dp_params = { 1906 .input_min = 12000000, 1907 .input_max = 800000000, 1908 .cf_min = 12000000, 1909 .cf_max = 38400000, 1910 .vco_min = 750000000, 1911 .vco_max = 1500000000, 1912 .base_reg = PLLDP_BASE, 1913 .misc_reg = PLLDP_MISC, 1914 .lock_mask = PLL_BASE_LOCK, 1915 .lock_delay = 300, 1916 .iddq_reg = PLLDP_BASE, 1917 .iddq_bit_idx = PLLSS_IDDQ_BIT, 1918 .sdm_din_reg = PLLDP_SS_CTRL2, 1919 .sdm_din_mask = PLLA_SDM_DIN_MASK, 1920 .sdm_ctrl_reg = PLLDP_SS_CFG, 1921 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK, 1922 .ssc_ctrl_reg = PLLDP_SS_CFG, 1923 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK, 1924 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1925 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1926 .div_nmp = &pllss_nmp, 1927 .ext_misc_reg[0] = PLLDP_MISC, 1928 .ext_misc_reg[1] = PLLDP_SS_CFG, 1929 .ext_misc_reg[2] = PLLDP_SS_CTRL1, 1930 .ext_misc_reg[3] = PLLDP_SS_CTRL2, 1931 .max_p = PLL_QLIN_PDIV_MAX, 1932 .mdiv_default = 1, 1933 .freq_table = pll_dp_freq_table, 1934 .set_defaults = tegra210_plldp_set_defaults, 1935 .flags = TEGRA_PLL_USE_LOCK, 1936 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1937 .set_gain = tegra210_clk_pll_set_gain, 1938 .adjust_vco = tegra210_clk_adjust_vco_min, 1939 }; 1940 1941 static struct div_nmp pllu_nmp = { 1942 .divm_shift = 0, 1943 .divm_width = 8, 1944 .divn_shift = 8, 1945 .divn_width = 8, 1946 .divp_shift = 16, 1947 .divp_width = 5, 1948 }; 1949 1950 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 1951 { 12000000, 480000000, 40, 1, 0, 0 }, 1952 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */ 1953 { 38400000, 480000000, 25, 2, 0, 0 }, 1954 { 0, 0, 0, 0, 0, 0 }, 1955 }; 1956 1957 static struct tegra_clk_pll_params pll_u_vco_params = { 1958 .input_min = 9600000, 1959 .input_max = 800000000, 1960 .cf_min = 9600000, 1961 .cf_max = 19200000, 1962 .vco_min = 350000000, 1963 .vco_max = 700000000, 1964 .base_reg = PLLU_BASE, 1965 .misc_reg = PLLU_MISC0, 1966 .lock_mask = PLL_BASE_LOCK, 1967 .lock_delay = 1000, 1968 .iddq_reg = PLLU_MISC0, 1969 .iddq_bit_idx = PLLU_IDDQ_BIT, 1970 .ext_misc_reg[0] = PLLU_MISC0, 1971 .ext_misc_reg[1] = PLLU_MISC1, 1972 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1973 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1974 .div_nmp = &pllu_nmp, 1975 .freq_table = pll_u_freq_table, 1976 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1977 .set_defaults = tegra210_pllu_set_defaults, 1978 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1979 }; 1980 1981 struct utmi_clk_param { 1982 /* Oscillator Frequency in KHz */ 1983 u32 osc_frequency; 1984 /* UTMIP PLL Enable Delay Count */ 1985 u8 enable_delay_count; 1986 /* UTMIP PLL Stable count */ 1987 u16 stable_count; 1988 /* UTMIP PLL Active delay count */ 1989 u8 active_delay_count; 1990 /* UTMIP PLL Xtal frequency count */ 1991 u16 xtal_freq_count; 1992 }; 1993 1994 static const struct utmi_clk_param utmi_parameters[] = { 1995 { 1996 .osc_frequency = 38400000, .enable_delay_count = 0x0, 1997 .stable_count = 0x0, .active_delay_count = 0x6, 1998 .xtal_freq_count = 0x80 1999 }, { 2000 .osc_frequency = 13000000, .enable_delay_count = 0x02, 2001 .stable_count = 0x33, .active_delay_count = 0x05, 2002 .xtal_freq_count = 0x7f 2003 }, { 2004 .osc_frequency = 19200000, .enable_delay_count = 0x03, 2005 .stable_count = 0x4b, .active_delay_count = 0x06, 2006 .xtal_freq_count = 0xbb 2007 }, { 2008 .osc_frequency = 12000000, .enable_delay_count = 0x02, 2009 .stable_count = 0x2f, .active_delay_count = 0x08, 2010 .xtal_freq_count = 0x76 2011 }, { 2012 .osc_frequency = 26000000, .enable_delay_count = 0x04, 2013 .stable_count = 0x66, .active_delay_count = 0x09, 2014 .xtal_freq_count = 0xfe 2015 }, { 2016 .osc_frequency = 16800000, .enable_delay_count = 0x03, 2017 .stable_count = 0x41, .active_delay_count = 0x0a, 2018 .xtal_freq_count = 0xa4 2019 }, 2020 }; 2021 2022 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 2023 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true }, 2024 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true }, 2025 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true }, 2026 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true }, 2027 [tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true }, 2028 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true }, 2029 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true }, 2030 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true }, 2031 [tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true }, 2032 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true }, 2033 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true }, 2034 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true }, 2035 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true }, 2036 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true }, 2037 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true }, 2038 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true }, 2039 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true }, 2040 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true }, 2041 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true }, 2042 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true }, 2043 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true }, 2044 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true }, 2045 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true }, 2046 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true }, 2047 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true }, 2048 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true }, 2049 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true }, 2050 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true }, 2051 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true }, 2052 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true }, 2053 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true }, 2054 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true }, 2055 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true }, 2056 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true }, 2057 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true }, 2058 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true }, 2059 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true }, 2060 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true }, 2061 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true }, 2062 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true }, 2063 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true }, 2064 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true }, 2065 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true }, 2066 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true }, 2067 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true }, 2068 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true }, 2069 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true }, 2070 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true }, 2071 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true }, 2072 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true }, 2073 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true }, 2074 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true }, 2075 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true }, 2076 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true }, 2077 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true }, 2078 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true }, 2079 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true }, 2080 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true }, 2081 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true }, 2082 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true }, 2083 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true }, 2084 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true }, 2085 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true }, 2086 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true }, 2087 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true }, 2088 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true }, 2089 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true }, 2090 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true }, 2091 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true }, 2092 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true }, 2093 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true }, 2094 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true }, 2095 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true }, 2096 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true }, 2097 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true }, 2098 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, }, 2099 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true }, 2100 [tegra_clk_vfir] = { .dt_id = TEGRA210_CLK_VFIR, .present = true }, 2101 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true }, 2102 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true }, 2103 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true }, 2104 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true }, 2105 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true }, 2106 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true }, 2107 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true }, 2108 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, 2109 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true }, 2110 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true }, 2111 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true }, 2112 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true }, 2113 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true }, 2114 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, 2115 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, 2116 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, 2117 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true }, 2118 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, 2119 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, 2120 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, 2121 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true }, 2122 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true }, 2123 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true }, 2124 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true }, 2125 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true }, 2126 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true }, 2127 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true }, 2128 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true }, 2129 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true }, 2130 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true }, 2131 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true }, 2132 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true }, 2133 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true }, 2134 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true }, 2135 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true }, 2136 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true }, 2137 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true }, 2138 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true }, 2139 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true }, 2140 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true }, 2141 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true }, 2142 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true }, 2143 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true }, 2144 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true }, 2145 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true }, 2146 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true }, 2147 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true }, 2148 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true }, 2149 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true }, 2150 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true }, 2151 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true }, 2152 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true }, 2153 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true }, 2154 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true }, 2155 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true }, 2156 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true }, 2157 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true }, 2158 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true }, 2159 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true }, 2160 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true }, 2161 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true }, 2162 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true }, 2163 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true }, 2164 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true }, 2165 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true }, 2166 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true }, 2167 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true }, 2168 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true }, 2169 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true }, 2170 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true }, 2171 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true }, 2172 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true }, 2173 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true }, 2174 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true }, 2175 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true }, 2176 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true }, 2177 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true }, 2178 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true }, 2179 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true }, 2180 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true }, 2181 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true }, 2182 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true }, 2183 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true }, 2184 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true }, 2185 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true }, 2186 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true }, 2187 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true }, 2188 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true }, 2189 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true }, 2190 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true }, 2191 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true }, 2192 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true }, 2193 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true }, 2194 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true }, 2195 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true }, 2196 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true }, 2197 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true }, 2198 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true }, 2199 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true }, 2200 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true }, 2201 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true }, 2202 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true }, 2203 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true }, 2204 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true }, 2205 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true }, 2206 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true }, 2207 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, 2208 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, 2209 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, 2210 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, 2211 }; 2212 2213 static struct tegra_devclk devclks[] __initdata = { 2214 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M }, 2215 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF }, 2216 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, 2217 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 }, 2218 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 }, 2219 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C }, 2220 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 }, 2221 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 }, 2222 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 }, 2223 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P }, 2224 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 }, 2225 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 }, 2226 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, 2227 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, 2228 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, 2229 { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 }, 2230 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, 2231 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, 2232 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, 2233 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT }, 2234 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 }, 2235 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 }, 2236 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M }, 2237 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M }, 2238 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M }, 2239 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D }, 2240 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 }, 2241 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 }, 2242 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 }, 2243 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A }, 2244 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 }, 2245 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO }, 2246 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT }, 2247 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC }, 2248 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC }, 2249 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC }, 2250 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC }, 2251 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC }, 2252 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC }, 2253 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC }, 2254 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 }, 2255 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 }, 2256 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 }, 2257 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 }, 2258 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 }, 2259 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF }, 2260 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X }, 2261 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 }, 2262 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 }, 2263 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 }, 2264 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK }, 2265 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G }, 2266 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP }, 2267 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK }, 2268 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK }, 2269 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK }, 2270 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE }, 2271 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC }, 2272 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER }, 2273 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 }, 2274 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 }, 2275 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 }, 2276 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 }, 2277 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX }, 2278 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 }, 2279 }; 2280 2281 static struct tegra_audio_clk_info tegra210_audio_plls[] = { 2282 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" }, 2283 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" }, 2284 }; 2285 2286 static struct clk **clks; 2287 2288 static void tegra210_utmi_param_configure(void __iomem *clk_base) 2289 { 2290 u32 reg; 2291 int i; 2292 2293 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 2294 if (osc_freq == utmi_parameters[i].osc_frequency) 2295 break; 2296 } 2297 2298 if (i >= ARRAY_SIZE(utmi_parameters)) { 2299 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 2300 osc_freq); 2301 return; 2302 } 2303 2304 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); 2305 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 2306 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 2307 PLLU_HW_PWRDN_CFG0_USE_LOCKDET; 2308 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 2309 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 2310 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); 2311 2312 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); 2313 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; 2314 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); 2315 udelay(1); 2316 2317 reg = readl_relaxed(clk_base + PLLU_BASE); 2318 reg &= ~PLLU_BASE_CLKENABLE_USB; 2319 writel_relaxed(reg, clk_base + PLLU_BASE); 2320 2321 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2322 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 2323 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2324 2325 udelay(10); 2326 2327 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 2328 2329 /* Program UTMIP PLL stable and active counts */ 2330 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 2331 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 2332 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 2333 2334 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 2335 2336 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 2337 active_delay_count); 2338 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 2339 2340 /* Program UTMIP PLL delay and oscillator frequency counts */ 2341 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2342 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 2343 2344 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 2345 enable_delay_count); 2346 2347 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 2348 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 2349 xtal_freq_count); 2350 2351 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 2352 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2353 2354 /* Remove power downs from UTMIP PLL control bits */ 2355 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2356 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 2357 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 2358 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2359 udelay(1); 2360 2361 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ 2362 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 2363 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; 2364 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; 2365 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; 2366 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 2367 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 2368 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; 2369 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 2370 2371 /* Setup HW control of UTMIPLL */ 2372 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2373 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 2374 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 2375 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2376 2377 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2378 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 2379 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 2380 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2381 2382 udelay(1); 2383 2384 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); 2385 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; 2386 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); 2387 2388 udelay(1); 2389 2390 /* Enable HW control UTMIPLL */ 2391 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2392 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 2393 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2394 } 2395 2396 static __init void tegra210_periph_clk_init(void __iomem *clk_base, 2397 void __iomem *pmc_base) 2398 { 2399 struct clk *clk; 2400 2401 /* xusb_ss_div2 */ 2402 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 2403 1, 2); 2404 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; 2405 2406 /* pll_d_dsi_out */ 2407 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, 2408 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); 2409 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk; 2410 2411 /* dsia */ 2412 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, 2413 clk_base, 0, 48, 2414 periph_clk_enb_refcnt); 2415 clks[TEGRA210_CLK_DSIA] = clk; 2416 2417 /* dsib */ 2418 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, 2419 clk_base, 0, 82, 2420 periph_clk_enb_refcnt); 2421 clks[TEGRA210_CLK_DSIB] = clk; 2422 2423 /* emc mux */ 2424 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2425 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2426 clk_base + CLK_SOURCE_EMC, 2427 29, 3, 0, &emc_lock); 2428 2429 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 2430 &emc_lock); 2431 clks[TEGRA210_CLK_MC] = clk; 2432 2433 /* cml0 */ 2434 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 2435 0, 0, &pll_e_lock); 2436 clk_register_clkdev(clk, "cml0", NULL); 2437 clks[TEGRA210_CLK_CML0] = clk; 2438 2439 /* cml1 */ 2440 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 2441 1, 0, &pll_e_lock); 2442 clk_register_clkdev(clk, "cml1", NULL); 2443 clks[TEGRA210_CLK_CML1] = clk; 2444 2445 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); 2446 } 2447 2448 static void __init tegra210_pll_init(void __iomem *clk_base, 2449 void __iomem *pmc) 2450 { 2451 u32 val; 2452 struct clk *clk; 2453 2454 /* PLLC */ 2455 clk = tegra_clk_register_pllxc_tegra210("pll_c", "pll_ref", clk_base, 2456 pmc, 0, &pll_c_params, NULL); 2457 if (!WARN_ON(IS_ERR(clk))) 2458 clk_register_clkdev(clk, "pll_c", NULL); 2459 clks[TEGRA210_CLK_PLL_C] = clk; 2460 2461 /* PLLC_OUT1 */ 2462 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 2463 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 2464 8, 8, 1, NULL); 2465 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 2466 clk_base + PLLC_OUT, 1, 0, 2467 CLK_SET_RATE_PARENT, 0, NULL); 2468 clk_register_clkdev(clk, "pll_c_out1", NULL); 2469 clks[TEGRA210_CLK_PLL_C_OUT1] = clk; 2470 2471 /* PLLC_UD */ 2472 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", 2473 CLK_SET_RATE_PARENT, 1, 1); 2474 clk_register_clkdev(clk, "pll_c_ud", NULL); 2475 clks[TEGRA210_CLK_PLL_C_UD] = clk; 2476 2477 /* PLLC2 */ 2478 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, 2479 pmc, 0, &pll_c2_params, NULL); 2480 clk_register_clkdev(clk, "pll_c2", NULL); 2481 clks[TEGRA210_CLK_PLL_C2] = clk; 2482 2483 /* PLLC3 */ 2484 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, 2485 pmc, 0, &pll_c3_params, NULL); 2486 clk_register_clkdev(clk, "pll_c3", NULL); 2487 clks[TEGRA210_CLK_PLL_C3] = clk; 2488 2489 /* PLLM */ 2490 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, 2491 CLK_SET_RATE_GATE, &pll_m_params, NULL); 2492 clk_register_clkdev(clk, "pll_m", NULL); 2493 clks[TEGRA210_CLK_PLL_M] = clk; 2494 2495 /* PLLMB */ 2496 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, 2497 CLK_SET_RATE_GATE, &pll_mb_params, NULL); 2498 clk_register_clkdev(clk, "pll_mb", NULL); 2499 clks[TEGRA210_CLK_PLL_MB] = clk; 2500 2501 clk_register_clkdev(clk, "pll_m_out1", NULL); 2502 clks[TEGRA210_CLK_PLL_M_OUT1] = clk; 2503 2504 /* PLLM_UD */ 2505 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 2506 CLK_SET_RATE_PARENT, 1, 1); 2507 clk_register_clkdev(clk, "pll_m_ud", NULL); 2508 clks[TEGRA210_CLK_PLL_M_UD] = clk; 2509 2510 /* PLLU_VCO */ 2511 val = readl(clk_base + pll_u_vco_params.base_reg); 2512 val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */ 2513 writel(val, clk_base + pll_u_vco_params.base_reg); 2514 2515 clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc, 2516 0, &pll_u_vco_params, &pll_u_lock, pll_ref_freq); 2517 clk_register_clkdev(clk, "pll_u_vco", NULL); 2518 clks[TEGRA210_CLK_PLL_U] = clk; 2519 2520 /* PLLU_OUT */ 2521 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, 2522 clk_base + PLLU_BASE, 16, 4, 0, 2523 pll_vco_post_div_table, NULL); 2524 clk_register_clkdev(clk, "pll_u_out", NULL); 2525 clks[TEGRA210_CLK_PLL_U_OUT] = clk; 2526 2527 /* PLLU_OUT1 */ 2528 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out", 2529 clk_base + PLLU_OUTA, 0, 2530 TEGRA_DIVIDER_ROUND_UP, 2531 8, 8, 1, &pll_u_lock); 2532 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div", 2533 clk_base + PLLU_OUTA, 1, 0, 2534 CLK_SET_RATE_PARENT, 0, &pll_u_lock); 2535 clk_register_clkdev(clk, "pll_u_out1", NULL); 2536 clks[TEGRA210_CLK_PLL_U_OUT1] = clk; 2537 2538 /* PLLU_OUT2 */ 2539 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out", 2540 clk_base + PLLU_OUTA, 0, 2541 TEGRA_DIVIDER_ROUND_UP, 2542 24, 8, 1, &pll_u_lock); 2543 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div", 2544 clk_base + PLLU_OUTA, 17, 16, 2545 CLK_SET_RATE_PARENT, 0, &pll_u_lock); 2546 clk_register_clkdev(clk, "pll_u_out2", NULL); 2547 clks[TEGRA210_CLK_PLL_U_OUT2] = clk; 2548 2549 tegra210_utmi_param_configure(clk_base); 2550 2551 /* PLLU_480M */ 2552 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco", 2553 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 2554 22, 0, &pll_u_lock); 2555 clk_register_clkdev(clk, "pll_u_480M", NULL); 2556 clks[TEGRA210_CLK_PLL_U_480M] = clk; 2557 2558 /* PLLU_60M */ 2559 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2", 2560 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 2561 23, 0, NULL); 2562 clk_register_clkdev(clk, "pll_u_60M", NULL); 2563 clks[TEGRA210_CLK_PLL_U_60M] = clk; 2564 2565 /* PLLU_48M */ 2566 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1", 2567 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 2568 25, 0, NULL); 2569 clk_register_clkdev(clk, "pll_u_48M", NULL); 2570 clks[TEGRA210_CLK_PLL_U_48M] = clk; 2571 2572 /* PLLD */ 2573 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 2574 &pll_d_params, &pll_d_lock); 2575 clk_register_clkdev(clk, "pll_d", NULL); 2576 clks[TEGRA210_CLK_PLL_D] = clk; 2577 2578 /* PLLD_OUT0 */ 2579 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 2580 CLK_SET_RATE_PARENT, 1, 2); 2581 clk_register_clkdev(clk, "pll_d_out0", NULL); 2582 clks[TEGRA210_CLK_PLL_D_OUT0] = clk; 2583 2584 /* PLLRE */ 2585 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 2586 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); 2587 clk_register_clkdev(clk, "pll_re_vco", NULL); 2588 clks[TEGRA210_CLK_PLL_RE_VCO] = clk; 2589 2590 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 2591 clk_base + PLLRE_BASE, 16, 5, 0, 2592 pll_vco_post_div_table, &pll_re_lock); 2593 clk_register_clkdev(clk, "pll_re_out", NULL); 2594 clks[TEGRA210_CLK_PLL_RE_OUT] = clk; 2595 2596 /* PLLE */ 2597 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref", 2598 clk_base, 0, &pll_e_params, NULL); 2599 clk_register_clkdev(clk, "pll_e", NULL); 2600 clks[TEGRA210_CLK_PLL_E] = clk; 2601 2602 /* PLLC4 */ 2603 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, 2604 0, &pll_c4_vco_params, NULL, pll_ref_freq); 2605 clk_register_clkdev(clk, "pll_c4_vco", NULL); 2606 clks[TEGRA210_CLK_PLL_C4] = clk; 2607 2608 /* PLLC4_OUT0 */ 2609 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0, 2610 clk_base + PLLC4_BASE, 19, 4, 0, 2611 pll_vco_post_div_table, NULL); 2612 clk_register_clkdev(clk, "pll_c4_out0", NULL); 2613 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; 2614 2615 /* PLLC4_OUT1 */ 2616 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco", 2617 CLK_SET_RATE_PARENT, 1, 3); 2618 clk_register_clkdev(clk, "pll_c4_out1", NULL); 2619 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk; 2620 2621 /* PLLC4_OUT2 */ 2622 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco", 2623 CLK_SET_RATE_PARENT, 1, 5); 2624 clk_register_clkdev(clk, "pll_c4_out2", NULL); 2625 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk; 2626 2627 /* PLLC4_OUT3 */ 2628 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0", 2629 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 2630 8, 8, 1, NULL); 2631 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div", 2632 clk_base + PLLC4_OUT, 1, 0, 2633 CLK_SET_RATE_PARENT, 0, NULL); 2634 clk_register_clkdev(clk, "pll_c4_out3", NULL); 2635 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk; 2636 2637 /* PLLDP */ 2638 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, 2639 0, &pll_dp_params, NULL); 2640 clk_register_clkdev(clk, "pll_dp", NULL); 2641 clks[TEGRA210_CLK_PLL_DP] = clk; 2642 2643 /* PLLD2 */ 2644 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, 2645 0, &pll_d2_params, NULL); 2646 clk_register_clkdev(clk, "pll_d2", NULL); 2647 clks[TEGRA210_CLK_PLL_D2] = clk; 2648 2649 /* PLLD2_OUT0 */ 2650 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 2651 CLK_SET_RATE_PARENT, 1, 1); 2652 clk_register_clkdev(clk, "pll_d2_out0", NULL); 2653 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk; 2654 2655 /* PLLP_OUT2 */ 2656 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p", 2657 CLK_SET_RATE_PARENT, 1, 2); 2658 clk_register_clkdev(clk, "pll_p_out2", NULL); 2659 clks[TEGRA210_CLK_PLL_P_OUT2] = clk; 2660 2661 } 2662 2663 /* Tegra210 CPU clock and reset control functions */ 2664 static void tegra210_wait_cpu_in_reset(u32 cpu) 2665 { 2666 unsigned int reg; 2667 2668 do { 2669 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 2670 cpu_relax(); 2671 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 2672 } 2673 2674 static void tegra210_disable_cpu_clock(u32 cpu) 2675 { 2676 /* flow controller would take care in the power sequence. */ 2677 } 2678 2679 #ifdef CONFIG_PM_SLEEP 2680 static void tegra210_cpu_clock_suspend(void) 2681 { 2682 /* switch coresite to clk_m, save off original source */ 2683 tegra210_cpu_clk_sctx.clk_csite_src = 2684 readl(clk_base + CLK_SOURCE_CSITE); 2685 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 2686 } 2687 2688 static void tegra210_cpu_clock_resume(void) 2689 { 2690 writel(tegra210_cpu_clk_sctx.clk_csite_src, 2691 clk_base + CLK_SOURCE_CSITE); 2692 } 2693 #endif 2694 2695 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { 2696 .wait_for_reset = tegra210_wait_cpu_in_reset, 2697 .disable_clock = tegra210_disable_cpu_clock, 2698 #ifdef CONFIG_PM_SLEEP 2699 .suspend = tegra210_cpu_clock_suspend, 2700 .resume = tegra210_cpu_clock_resume, 2701 #endif 2702 }; 2703 2704 static const struct of_device_id pmc_match[] __initconst = { 2705 { .compatible = "nvidia,tegra210-pmc" }, 2706 { }, 2707 }; 2708 2709 static struct tegra_clk_init_table init_table[] __initdata = { 2710 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 }, 2711 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 }, 2712 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 }, 2713 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 }, 2714 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 }, 2715 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 }, 2716 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 }, 2717 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 }, 2718 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2719 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 2720 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 2721 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 2722 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 2723 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 2724 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 }, 2725 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 }, 2726 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1 }, 2727 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 }, 2728 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, 2729 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, 2730 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 }, 2731 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2732 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, 2733 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 }, 2734 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, 2735 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, 2736 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 }, 2737 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, 2738 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, 2739 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 }, 2740 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 }, 2741 { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2742 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2743 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2744 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 }, 2745 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 }, 2746 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 }, 2747 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 }, 2748 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 }, 2749 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 }, 2750 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 }, 2751 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 }, 2752 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 }, 2753 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2754 /* This MUST be the last entry. */ 2755 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, 2756 }; 2757 2758 /** 2759 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs 2760 * 2761 * Program an initial clock rate and enable or disable clocks needed 2762 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be 2763 * called by assigning a pointer to it to tegra_clk_apply_init_table - 2764 * this will be called as an arch_initcall. No return value. 2765 */ 2766 static void __init tegra210_clock_apply_init_table(void) 2767 { 2768 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX); 2769 } 2770 2771 /** 2772 * tegra210_clock_init - Tegra210-specific clock initialization 2773 * @np: struct device_node * of the DT node for the SoC CAR IP block 2774 * 2775 * Register most SoC clocks for the Tegra210 system-on-chip. Intended 2776 * to be called by the OF init code when a DT node with the 2777 * "nvidia,tegra210-car" string is encountered, and declared with 2778 * CLK_OF_DECLARE. No return value. 2779 */ 2780 static void __init tegra210_clock_init(struct device_node *np) 2781 { 2782 struct device_node *node; 2783 u32 value, clk_m_div; 2784 2785 clk_base = of_iomap(np, 0); 2786 if (!clk_base) { 2787 pr_err("ioremap tegra210 CAR failed\n"); 2788 return; 2789 } 2790 2791 node = of_find_matching_node(NULL, pmc_match); 2792 if (!node) { 2793 pr_err("Failed to find pmc node\n"); 2794 WARN_ON(1); 2795 return; 2796 } 2797 2798 pmc_base = of_iomap(node, 0); 2799 if (!pmc_base) { 2800 pr_err("Can't map pmc registers\n"); 2801 WARN_ON(1); 2802 return; 2803 } 2804 2805 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, 2806 TEGRA210_CAR_BANK_COUNT); 2807 if (!clks) 2808 return; 2809 2810 value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; 2811 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1; 2812 2813 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, 2814 ARRAY_SIZE(tegra210_input_freq), clk_m_div, 2815 &osc_freq, &pll_ref_freq) < 0) 2816 return; 2817 2818 tegra_fixed_clk_init(tegra210_clks); 2819 tegra210_pll_init(clk_base, pmc_base); 2820 tegra210_periph_clk_init(clk_base, pmc_base); 2821 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, 2822 tegra210_audio_plls, 2823 ARRAY_SIZE(tegra210_audio_plls)); 2824 tegra_pmc_clk_init(pmc_base, tegra210_clks); 2825 2826 /* For Tegra210, PLLD is the only source for DSIA & DSIB */ 2827 value = clk_readl(clk_base + PLLD_BASE); 2828 value &= ~BIT(25); 2829 clk_writel(value, clk_base + PLLD_BASE); 2830 2831 tegra_clk_apply_init_table = tegra210_clock_apply_init_table; 2832 2833 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, 2834 &pll_x_params); 2835 tegra_add_of_provider(np); 2836 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 2837 2838 tegra_cpu_car_ops = &tegra210_cpu_car_ops; 2839 } 2840 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); 2841