1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk-provider.h> 19 #include <linux/clkdev.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/clk/tegra.h> 23 #include <linux/delay.h> 24 #include <dt-bindings/clock/tegra20-car.h> 25 26 #include "clk.h" 27 #include "clk-id.h" 28 29 #define MISC_CLK_ENB 0x48 30 31 #define OSC_CTRL 0x50 32 #define OSC_CTRL_OSC_FREQ_MASK (3<<30) 33 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) 34 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) 35 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) 36 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) 37 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 38 39 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) 40 #define OSC_CTRL_PLL_REF_DIV_1 (0<<28) 41 #define OSC_CTRL_PLL_REF_DIV_2 (1<<28) 42 #define OSC_CTRL_PLL_REF_DIV_4 (2<<28) 43 44 #define OSC_FREQ_DET 0x58 45 #define OSC_FREQ_DET_TRIG (1<<31) 46 47 #define OSC_FREQ_DET_STATUS 0x5c 48 #define OSC_FREQ_DET_BUSY (1<<31) 49 #define OSC_FREQ_DET_CNT_MASK 0xFFFF 50 51 #define TEGRA20_CLK_PERIPH_BANKS 3 52 53 #define PLLS_BASE 0xf0 54 #define PLLS_MISC 0xf4 55 #define PLLC_BASE 0x80 56 #define PLLC_MISC 0x8c 57 #define PLLM_BASE 0x90 58 #define PLLM_MISC 0x9c 59 #define PLLP_BASE 0xa0 60 #define PLLP_MISC 0xac 61 #define PLLA_BASE 0xb0 62 #define PLLA_MISC 0xbc 63 #define PLLU_BASE 0xc0 64 #define PLLU_MISC 0xcc 65 #define PLLD_BASE 0xd0 66 #define PLLD_MISC 0xdc 67 #define PLLX_BASE 0xe0 68 #define PLLX_MISC 0xe4 69 #define PLLE_BASE 0xe8 70 #define PLLE_MISC 0xec 71 72 #define PLL_BASE_LOCK BIT(27) 73 #define PLLE_MISC_LOCK BIT(11) 74 75 #define PLL_MISC_LOCK_ENABLE 18 76 #define PLLDU_MISC_LOCK_ENABLE 22 77 #define PLLE_MISC_LOCK_ENABLE 9 78 79 #define PLLC_OUT 0x84 80 #define PLLM_OUT 0x94 81 #define PLLP_OUTA 0xa4 82 #define PLLP_OUTB 0xa8 83 #define PLLA_OUT 0xb4 84 85 #define CCLK_BURST_POLICY 0x20 86 #define SUPER_CCLK_DIVIDER 0x24 87 #define SCLK_BURST_POLICY 0x28 88 #define SUPER_SCLK_DIVIDER 0x2c 89 #define CLK_SYSTEM_RATE 0x30 90 91 #define CCLK_BURST_POLICY_SHIFT 28 92 #define CCLK_RUN_POLICY_SHIFT 4 93 #define CCLK_IDLE_POLICY_SHIFT 0 94 #define CCLK_IDLE_POLICY 1 95 #define CCLK_RUN_POLICY 2 96 #define CCLK_BURST_POLICY_PLLX 8 97 98 #define CLK_SOURCE_I2S1 0x100 99 #define CLK_SOURCE_I2S2 0x104 100 #define CLK_SOURCE_PWM 0x110 101 #define CLK_SOURCE_SPI 0x114 102 #define CLK_SOURCE_XIO 0x120 103 #define CLK_SOURCE_TWC 0x12c 104 #define CLK_SOURCE_IDE 0x144 105 #define CLK_SOURCE_HDMI 0x18c 106 #define CLK_SOURCE_DISP1 0x138 107 #define CLK_SOURCE_DISP2 0x13c 108 #define CLK_SOURCE_CSITE 0x1d4 109 #define CLK_SOURCE_I2C1 0x124 110 #define CLK_SOURCE_I2C2 0x198 111 #define CLK_SOURCE_I2C3 0x1b8 112 #define CLK_SOURCE_DVC 0x128 113 #define CLK_SOURCE_UARTA 0x178 114 #define CLK_SOURCE_UARTB 0x17c 115 #define CLK_SOURCE_UARTC 0x1a0 116 #define CLK_SOURCE_UARTD 0x1c0 117 #define CLK_SOURCE_UARTE 0x1c4 118 #define CLK_SOURCE_EMC 0x19c 119 120 #define AUDIO_SYNC_CLK 0x38 121 122 /* Tegra CPU clock and reset control regs */ 123 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 124 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 125 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 126 127 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 128 #define CPU_RESET(cpu) (0x1111ul << (cpu)) 129 130 #ifdef CONFIG_PM_SLEEP 131 static struct cpu_clk_suspend_context { 132 u32 pllx_misc; 133 u32 pllx_base; 134 135 u32 cpu_burst; 136 u32 clk_csite_src; 137 u32 cclk_divider; 138 } tegra20_cpu_clk_sctx; 139 #endif 140 141 static void __iomem *clk_base; 142 static void __iomem *pmc_base; 143 144 static DEFINE_SPINLOCK(emc_lock); 145 146 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 147 _clk_num, _gate_flags, _clk_id) \ 148 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 149 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 150 _clk_num, \ 151 _gate_flags, _clk_id) 152 153 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ 154 _clk_num, _gate_flags, _clk_id) \ 155 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 156 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 157 _clk_num, _gate_flags, \ 158 _clk_id) 159 160 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 161 _mux_shift, _mux_width, _clk_num, \ 162 _gate_flags, _clk_id) \ 163 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 164 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ 165 _clk_num, _gate_flags, \ 166 _clk_id) 167 168 static struct clk **clks; 169 170 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 171 { 12000000, 600000000, 600, 12, 1, 8 }, 172 { 13000000, 600000000, 600, 13, 1, 8 }, 173 { 19200000, 600000000, 500, 16, 1, 6 }, 174 { 26000000, 600000000, 600, 26, 1, 8 }, 175 { 0, 0, 0, 0, 0, 0 }, 176 }; 177 178 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 179 { 12000000, 666000000, 666, 12, 1, 8 }, 180 { 13000000, 666000000, 666, 13, 1, 8 }, 181 { 19200000, 666000000, 555, 16, 1, 8 }, 182 { 26000000, 666000000, 666, 26, 1, 8 }, 183 { 12000000, 600000000, 600, 12, 1, 8 }, 184 { 13000000, 600000000, 600, 13, 1, 8 }, 185 { 19200000, 600000000, 375, 12, 1, 6 }, 186 { 26000000, 600000000, 600, 26, 1, 8 }, 187 { 0, 0, 0, 0, 0, 0 }, 188 }; 189 190 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 191 { 12000000, 216000000, 432, 12, 2, 8 }, 192 { 13000000, 216000000, 432, 13, 2, 8 }, 193 { 19200000, 216000000, 90, 4, 2, 1 }, 194 { 26000000, 216000000, 432, 26, 2, 8 }, 195 { 12000000, 432000000, 432, 12, 1, 8 }, 196 { 13000000, 432000000, 432, 13, 1, 8 }, 197 { 19200000, 432000000, 90, 4, 1, 1 }, 198 { 26000000, 432000000, 432, 26, 1, 8 }, 199 { 0, 0, 0, 0, 0, 0 }, 200 }; 201 202 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 203 { 28800000, 56448000, 49, 25, 1, 1 }, 204 { 28800000, 73728000, 64, 25, 1, 1 }, 205 { 28800000, 24000000, 5, 6, 1, 1 }, 206 { 0, 0, 0, 0, 0, 0 }, 207 }; 208 209 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 210 { 12000000, 216000000, 216, 12, 1, 4 }, 211 { 13000000, 216000000, 216, 13, 1, 4 }, 212 { 19200000, 216000000, 135, 12, 1, 3 }, 213 { 26000000, 216000000, 216, 26, 1, 4 }, 214 { 12000000, 594000000, 594, 12, 1, 8 }, 215 { 13000000, 594000000, 594, 13, 1, 8 }, 216 { 19200000, 594000000, 495, 16, 1, 8 }, 217 { 26000000, 594000000, 594, 26, 1, 8 }, 218 { 12000000, 1000000000, 1000, 12, 1, 12 }, 219 { 13000000, 1000000000, 1000, 13, 1, 12 }, 220 { 19200000, 1000000000, 625, 12, 1, 8 }, 221 { 26000000, 1000000000, 1000, 26, 1, 12 }, 222 { 0, 0, 0, 0, 0, 0 }, 223 }; 224 225 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 226 { 12000000, 480000000, 960, 12, 1, 0 }, 227 { 13000000, 480000000, 960, 13, 1, 0 }, 228 { 19200000, 480000000, 200, 4, 1, 0 }, 229 { 26000000, 480000000, 960, 26, 1, 0 }, 230 { 0, 0, 0, 0, 0, 0 }, 231 }; 232 233 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 234 /* 1 GHz */ 235 { 12000000, 1000000000, 1000, 12, 1, 12 }, 236 { 13000000, 1000000000, 1000, 13, 1, 12 }, 237 { 19200000, 1000000000, 625, 12, 1, 8 }, 238 { 26000000, 1000000000, 1000, 26, 1, 12 }, 239 /* 912 MHz */ 240 { 12000000, 912000000, 912, 12, 1, 12 }, 241 { 13000000, 912000000, 912, 13, 1, 12 }, 242 { 19200000, 912000000, 760, 16, 1, 8 }, 243 { 26000000, 912000000, 912, 26, 1, 12 }, 244 /* 816 MHz */ 245 { 12000000, 816000000, 816, 12, 1, 12 }, 246 { 13000000, 816000000, 816, 13, 1, 12 }, 247 { 19200000, 816000000, 680, 16, 1, 8 }, 248 { 26000000, 816000000, 816, 26, 1, 12 }, 249 /* 760 MHz */ 250 { 12000000, 760000000, 760, 12, 1, 12 }, 251 { 13000000, 760000000, 760, 13, 1, 12 }, 252 { 19200000, 760000000, 950, 24, 1, 8 }, 253 { 26000000, 760000000, 760, 26, 1, 12 }, 254 /* 750 MHz */ 255 { 12000000, 750000000, 750, 12, 1, 12 }, 256 { 13000000, 750000000, 750, 13, 1, 12 }, 257 { 19200000, 750000000, 625, 16, 1, 8 }, 258 { 26000000, 750000000, 750, 26, 1, 12 }, 259 /* 608 MHz */ 260 { 12000000, 608000000, 608, 12, 1, 12 }, 261 { 13000000, 608000000, 608, 13, 1, 12 }, 262 { 19200000, 608000000, 380, 12, 1, 8 }, 263 { 26000000, 608000000, 608, 26, 1, 12 }, 264 /* 456 MHz */ 265 { 12000000, 456000000, 456, 12, 1, 12 }, 266 { 13000000, 456000000, 456, 13, 1, 12 }, 267 { 19200000, 456000000, 380, 16, 1, 8 }, 268 { 26000000, 456000000, 456, 26, 1, 12 }, 269 /* 312 MHz */ 270 { 12000000, 312000000, 312, 12, 1, 12 }, 271 { 13000000, 312000000, 312, 13, 1, 12 }, 272 { 19200000, 312000000, 260, 16, 1, 8 }, 273 { 26000000, 312000000, 312, 26, 1, 12 }, 274 { 0, 0, 0, 0, 0, 0 }, 275 }; 276 277 static const struct pdiv_map plle_p[] = { 278 { .pdiv = 1, .hw_val = 1 }, 279 { .pdiv = 0, .hw_val = 0 }, 280 }; 281 282 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 283 { 12000000, 100000000, 200, 24, 1, 0 }, 284 { 0, 0, 0, 0, 0, 0 }, 285 }; 286 287 /* PLL parameters */ 288 static struct tegra_clk_pll_params pll_c_params = { 289 .input_min = 2000000, 290 .input_max = 31000000, 291 .cf_min = 1000000, 292 .cf_max = 6000000, 293 .vco_min = 20000000, 294 .vco_max = 1400000000, 295 .base_reg = PLLC_BASE, 296 .misc_reg = PLLC_MISC, 297 .lock_mask = PLL_BASE_LOCK, 298 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 299 .lock_delay = 300, 300 .freq_table = pll_c_freq_table, 301 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 302 }; 303 304 static struct tegra_clk_pll_params pll_m_params = { 305 .input_min = 2000000, 306 .input_max = 31000000, 307 .cf_min = 1000000, 308 .cf_max = 6000000, 309 .vco_min = 20000000, 310 .vco_max = 1200000000, 311 .base_reg = PLLM_BASE, 312 .misc_reg = PLLM_MISC, 313 .lock_mask = PLL_BASE_LOCK, 314 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 315 .lock_delay = 300, 316 .freq_table = pll_m_freq_table, 317 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 318 }; 319 320 static struct tegra_clk_pll_params pll_p_params = { 321 .input_min = 2000000, 322 .input_max = 31000000, 323 .cf_min = 1000000, 324 .cf_max = 6000000, 325 .vco_min = 20000000, 326 .vco_max = 1400000000, 327 .base_reg = PLLP_BASE, 328 .misc_reg = PLLP_MISC, 329 .lock_mask = PLL_BASE_LOCK, 330 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 331 .lock_delay = 300, 332 .freq_table = pll_p_freq_table, 333 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 334 TEGRA_PLL_HAS_LOCK_ENABLE, 335 .fixed_rate = 216000000, 336 }; 337 338 static struct tegra_clk_pll_params pll_a_params = { 339 .input_min = 2000000, 340 .input_max = 31000000, 341 .cf_min = 1000000, 342 .cf_max = 6000000, 343 .vco_min = 20000000, 344 .vco_max = 1400000000, 345 .base_reg = PLLA_BASE, 346 .misc_reg = PLLA_MISC, 347 .lock_mask = PLL_BASE_LOCK, 348 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 349 .lock_delay = 300, 350 .freq_table = pll_a_freq_table, 351 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 352 }; 353 354 static struct tegra_clk_pll_params pll_d_params = { 355 .input_min = 2000000, 356 .input_max = 40000000, 357 .cf_min = 1000000, 358 .cf_max = 6000000, 359 .vco_min = 40000000, 360 .vco_max = 1000000000, 361 .base_reg = PLLD_BASE, 362 .misc_reg = PLLD_MISC, 363 .lock_mask = PLL_BASE_LOCK, 364 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 365 .lock_delay = 1000, 366 .freq_table = pll_d_freq_table, 367 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 368 }; 369 370 static const struct pdiv_map pllu_p[] = { 371 { .pdiv = 1, .hw_val = 1 }, 372 { .pdiv = 2, .hw_val = 0 }, 373 { .pdiv = 0, .hw_val = 0 }, 374 }; 375 376 static struct tegra_clk_pll_params pll_u_params = { 377 .input_min = 2000000, 378 .input_max = 40000000, 379 .cf_min = 1000000, 380 .cf_max = 6000000, 381 .vco_min = 48000000, 382 .vco_max = 960000000, 383 .base_reg = PLLU_BASE, 384 .misc_reg = PLLU_MISC, 385 .lock_mask = PLL_BASE_LOCK, 386 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 387 .lock_delay = 1000, 388 .pdiv_tohw = pllu_p, 389 .freq_table = pll_u_freq_table, 390 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 391 }; 392 393 static struct tegra_clk_pll_params pll_x_params = { 394 .input_min = 2000000, 395 .input_max = 31000000, 396 .cf_min = 1000000, 397 .cf_max = 6000000, 398 .vco_min = 20000000, 399 .vco_max = 1200000000, 400 .base_reg = PLLX_BASE, 401 .misc_reg = PLLX_MISC, 402 .lock_mask = PLL_BASE_LOCK, 403 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 404 .lock_delay = 300, 405 .freq_table = pll_x_freq_table, 406 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 407 }; 408 409 static struct tegra_clk_pll_params pll_e_params = { 410 .input_min = 12000000, 411 .input_max = 12000000, 412 .cf_min = 0, 413 .cf_max = 0, 414 .vco_min = 0, 415 .vco_max = 0, 416 .base_reg = PLLE_BASE, 417 .misc_reg = PLLE_MISC, 418 .lock_mask = PLLE_MISC_LOCK, 419 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 420 .lock_delay = 0, 421 .pdiv_tohw = plle_p, 422 .freq_table = pll_e_freq_table, 423 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | 424 TEGRA_PLL_HAS_LOCK_ENABLE, 425 .fixed_rate = 100000000, 426 }; 427 428 static struct tegra_devclk devclks[] __initdata = { 429 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C }, 430 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 }, 431 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P }, 432 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 }, 433 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 }, 434 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 }, 435 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 }, 436 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M }, 437 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 }, 438 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X }, 439 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U }, 440 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D }, 441 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 }, 442 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A }, 443 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 }, 444 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E }, 445 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK }, 446 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK }, 447 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK }, 448 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK }, 449 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE }, 450 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD }, 451 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO }, 452 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X }, 453 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 }, 454 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA }, 455 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC }, 456 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER }, 457 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC }, 458 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS }, 459 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP }, 460 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA }, 461 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV }, 462 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC }, 463 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD }, 464 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 }, 465 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 }, 466 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI }, 467 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI }, 468 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP }, 469 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX }, 470 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI }, 471 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 }, 472 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 }, 473 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K }, 474 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK }, 475 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M }, 476 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF }, 477 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 }, 478 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 }, 479 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT }, 480 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN }, 481 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 }, 482 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 }, 483 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 }, 484 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 }, 485 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI }, 486 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO }, 487 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC }, 488 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE }, 489 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH }, 490 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR }, 491 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE }, 492 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA }, 493 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR }, 494 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI }, 495 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE }, 496 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI }, 497 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP }, 498 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE }, 499 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X }, 500 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D }, 501 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D }, 502 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR }, 503 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 }, 504 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 }, 505 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 }, 506 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 }, 507 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE }, 508 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO }, 509 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC }, 510 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR }, 511 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI }, 512 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 }, 513 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 }, 514 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 }, 515 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC }, 516 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM }, 517 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA }, 518 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB }, 519 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC }, 520 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD }, 521 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE }, 522 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 }, 523 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 }, 524 }; 525 526 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { 527 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true }, 528 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true }, 529 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, 530 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, 531 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, 532 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true }, 533 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true }, 534 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true }, 535 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true }, 536 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true }, 537 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true }, 538 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true }, 539 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true }, 540 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true }, 541 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true }, 542 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true }, 543 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true }, 544 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true }, 545 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true }, 546 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true }, 547 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true }, 548 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true }, 549 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true }, 550 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true }, 551 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true }, 552 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true }, 553 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true }, 554 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true }, 555 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true }, 556 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true }, 557 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true }, 558 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true }, 559 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true }, 560 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true }, 561 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true }, 562 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true }, 563 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true }, 564 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true }, 565 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true }, 566 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true }, 567 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true }, 568 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true }, 569 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true }, 570 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true }, 571 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true }, 572 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true }, 573 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true }, 574 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true }, 575 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true }, 576 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true }, 577 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true }, 578 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, 579 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, 580 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, 581 [tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true }, 582 }; 583 584 static unsigned long tegra20_clk_measure_input_freq(void) 585 { 586 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 587 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 588 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 589 unsigned long input_freq; 590 591 switch (auto_clk_control) { 592 case OSC_CTRL_OSC_FREQ_12MHZ: 593 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 594 input_freq = 12000000; 595 break; 596 case OSC_CTRL_OSC_FREQ_13MHZ: 597 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 598 input_freq = 13000000; 599 break; 600 case OSC_CTRL_OSC_FREQ_19_2MHZ: 601 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 602 input_freq = 19200000; 603 break; 604 case OSC_CTRL_OSC_FREQ_26MHZ: 605 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 606 input_freq = 26000000; 607 break; 608 default: 609 pr_err("Unexpected clock autodetect value %d", 610 auto_clk_control); 611 BUG(); 612 return 0; 613 } 614 615 return input_freq; 616 } 617 618 static unsigned int tegra20_get_pll_ref_div(void) 619 { 620 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 621 OSC_CTRL_PLL_REF_DIV_MASK; 622 623 switch (pll_ref_div) { 624 case OSC_CTRL_PLL_REF_DIV_1: 625 return 1; 626 case OSC_CTRL_PLL_REF_DIV_2: 627 return 2; 628 case OSC_CTRL_PLL_REF_DIV_4: 629 return 4; 630 default: 631 pr_err("Invalid pll ref divider %d\n", pll_ref_div); 632 BUG(); 633 } 634 return 0; 635 } 636 637 static void tegra20_pll_init(void) 638 { 639 struct clk *clk; 640 641 /* PLLC */ 642 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 643 &pll_c_params, NULL); 644 clks[TEGRA20_CLK_PLL_C] = clk; 645 646 /* PLLC_OUT1 */ 647 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 648 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 649 8, 8, 1, NULL); 650 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 651 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 652 0, NULL); 653 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; 654 655 /* PLLM */ 656 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 657 CLK_SET_RATE_GATE, &pll_m_params, NULL); 658 clks[TEGRA20_CLK_PLL_M] = clk; 659 660 /* PLLM_OUT1 */ 661 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 662 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 663 8, 8, 1, NULL); 664 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 665 clk_base + PLLM_OUT, 1, 0, 666 CLK_SET_RATE_PARENT, 0, NULL); 667 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; 668 669 /* PLLX */ 670 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 671 &pll_x_params, NULL); 672 clks[TEGRA20_CLK_PLL_X] = clk; 673 674 /* PLLU */ 675 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 676 &pll_u_params, NULL); 677 clks[TEGRA20_CLK_PLL_U] = clk; 678 679 /* PLLD */ 680 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 681 &pll_d_params, NULL); 682 clks[TEGRA20_CLK_PLL_D] = clk; 683 684 /* PLLD_OUT0 */ 685 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 686 CLK_SET_RATE_PARENT, 1, 2); 687 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; 688 689 /* PLLA */ 690 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 691 &pll_a_params, NULL); 692 clks[TEGRA20_CLK_PLL_A] = clk; 693 694 /* PLLA_OUT0 */ 695 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 696 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 697 8, 8, 1, NULL); 698 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 699 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 700 CLK_SET_RATE_PARENT, 0, NULL); 701 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; 702 703 /* PLLE */ 704 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 705 0, &pll_e_params, NULL); 706 clks[TEGRA20_CLK_PLL_E] = clk; 707 } 708 709 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 710 "pll_p", "pll_p_out4", 711 "pll_p_out3", "clk_d", "pll_x" }; 712 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 713 "pll_p_out3", "pll_p_out2", "clk_d", 714 "clk_32k", "pll_m_out1" }; 715 716 static void tegra20_super_clk_init(void) 717 { 718 struct clk *clk; 719 720 /* CCLK */ 721 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 722 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 723 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 724 clks[TEGRA20_CLK_CCLK] = clk; 725 726 /* SCLK */ 727 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 728 ARRAY_SIZE(sclk_parents), 729 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 730 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 731 clks[TEGRA20_CLK_SCLK] = clk; 732 733 /* twd */ 734 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 735 clks[TEGRA20_CLK_TWD] = clk; 736 } 737 738 static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused", 739 "pll_a_out0", "unused", "unused", 740 "unused" }; 741 742 static void __init tegra20_audio_clk_init(void) 743 { 744 struct clk *clk; 745 746 /* audio */ 747 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 748 ARRAY_SIZE(audio_parents), 749 CLK_SET_RATE_NO_REPARENT, 750 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 751 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 752 clk_base + AUDIO_SYNC_CLK, 4, 753 CLK_GATE_SET_TO_DISABLE, NULL); 754 clks[TEGRA20_CLK_AUDIO] = clk; 755 756 /* audio_2x */ 757 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 758 CLK_SET_RATE_PARENT, 2, 1); 759 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 760 TEGRA_PERIPH_NO_RESET, clk_base, 761 CLK_SET_RATE_PARENT, 89, 762 periph_clk_enb_refcnt); 763 clks[TEGRA20_CLK_AUDIO_2X] = clk; 764 } 765 766 static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 767 "clk_m" }; 768 static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 769 "clk_m" }; 770 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m", 771 "clk_32k" }; 772 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 773 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 774 "clk_m" }; 775 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 776 777 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 778 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1), 779 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2), 780 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI), 781 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO), 782 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC), 783 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE), 784 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC), 785 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1), 786 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2), 787 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3), 788 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI), 789 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM), 790 }; 791 792 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 793 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA), 794 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB), 795 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC), 796 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD), 797 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE), 798 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1), 799 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), 800 }; 801 802 static void __init tegra20_periph_clk_init(void) 803 { 804 struct tegra_periph_init_data *data; 805 struct clk *clk; 806 unsigned int i; 807 808 /* ac97 */ 809 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 810 TEGRA_PERIPH_ON_APB, 811 clk_base, 0, 3, periph_clk_enb_refcnt); 812 clks[TEGRA20_CLK_AC97] = clk; 813 814 /* emc */ 815 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 816 ARRAY_SIZE(mux_pllmcp_clkm), 817 CLK_SET_RATE_NO_REPARENT, 818 clk_base + CLK_SOURCE_EMC, 819 30, 2, 0, &emc_lock); 820 821 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 822 &emc_lock); 823 clks[TEGRA20_CLK_MC] = clk; 824 825 /* dsi */ 826 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 827 48, periph_clk_enb_refcnt); 828 clk_register_clkdev(clk, NULL, "dsi"); 829 clks[TEGRA20_CLK_DSI] = clk; 830 831 /* pex */ 832 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 833 periph_clk_enb_refcnt); 834 clks[TEGRA20_CLK_PEX] = clk; 835 836 /* dev1 OSC divider */ 837 clk_register_divider(NULL, "dev1_osc_div", "clk_m", 838 0, clk_base + MISC_CLK_ENB, 22, 2, 839 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 840 NULL); 841 842 /* dev2 OSC divider */ 843 clk_register_divider(NULL, "dev2_osc_div", "clk_m", 844 0, clk_base + MISC_CLK_ENB, 20, 2, 845 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 846 NULL); 847 848 /* cdev1 */ 849 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, 850 clk_base, 0, 94, periph_clk_enb_refcnt); 851 clks[TEGRA20_CLK_CDEV1] = clk; 852 853 /* cdev2 */ 854 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, 855 clk_base, 0, 93, periph_clk_enb_refcnt); 856 clks[TEGRA20_CLK_CDEV2] = clk; 857 858 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 859 data = &tegra_periph_clk_list[i]; 860 clk = tegra_clk_register_periph_data(clk_base, data); 861 clks[data->clk_id] = clk; 862 } 863 864 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 865 data = &tegra_periph_nodiv_clk_list[i]; 866 clk = tegra_clk_register_periph_nodiv(data->name, 867 data->p.parent_names, 868 data->num_parents, &data->periph, 869 clk_base, data->offset); 870 clks[data->clk_id] = clk; 871 } 872 873 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); 874 } 875 876 static void __init tegra20_osc_clk_init(void) 877 { 878 struct clk *clk; 879 unsigned long input_freq; 880 unsigned int pll_ref_div; 881 882 input_freq = tegra20_clk_measure_input_freq(); 883 884 /* clk_m */ 885 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED, 886 input_freq); 887 clks[TEGRA20_CLK_CLK_M] = clk; 888 889 /* pll_ref */ 890 pll_ref_div = tegra20_get_pll_ref_div(); 891 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 892 CLK_SET_RATE_PARENT, 1, pll_ref_div); 893 clks[TEGRA20_CLK_PLL_REF] = clk; 894 } 895 896 /* Tegra20 CPU clock and reset control functions */ 897 static void tegra20_wait_cpu_in_reset(u32 cpu) 898 { 899 unsigned int reg; 900 901 do { 902 reg = readl(clk_base + 903 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 904 cpu_relax(); 905 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 906 907 return; 908 } 909 910 static void tegra20_put_cpu_in_reset(u32 cpu) 911 { 912 writel(CPU_RESET(cpu), 913 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 914 dmb(); 915 } 916 917 static void tegra20_cpu_out_of_reset(u32 cpu) 918 { 919 writel(CPU_RESET(cpu), 920 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 921 wmb(); 922 } 923 924 static void tegra20_enable_cpu_clock(u32 cpu) 925 { 926 unsigned int reg; 927 928 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 929 writel(reg & ~CPU_CLOCK(cpu), 930 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 931 barrier(); 932 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 933 } 934 935 static void tegra20_disable_cpu_clock(u32 cpu) 936 { 937 unsigned int reg; 938 939 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 940 writel(reg | CPU_CLOCK(cpu), 941 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 942 } 943 944 #ifdef CONFIG_PM_SLEEP 945 static bool tegra20_cpu_rail_off_ready(void) 946 { 947 unsigned int cpu_rst_status; 948 949 cpu_rst_status = readl(clk_base + 950 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 951 952 return !!(cpu_rst_status & 0x2); 953 } 954 955 static void tegra20_cpu_clock_suspend(void) 956 { 957 /* switch coresite to clk_m, save off original source */ 958 tegra20_cpu_clk_sctx.clk_csite_src = 959 readl(clk_base + CLK_SOURCE_CSITE); 960 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 961 962 tegra20_cpu_clk_sctx.cpu_burst = 963 readl(clk_base + CCLK_BURST_POLICY); 964 tegra20_cpu_clk_sctx.pllx_base = 965 readl(clk_base + PLLX_BASE); 966 tegra20_cpu_clk_sctx.pllx_misc = 967 readl(clk_base + PLLX_MISC); 968 tegra20_cpu_clk_sctx.cclk_divider = 969 readl(clk_base + SUPER_CCLK_DIVIDER); 970 } 971 972 static void tegra20_cpu_clock_resume(void) 973 { 974 unsigned int reg, policy; 975 976 /* Is CPU complex already running on PLLX? */ 977 reg = readl(clk_base + CCLK_BURST_POLICY); 978 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 979 980 if (policy == CCLK_IDLE_POLICY) 981 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 982 else if (policy == CCLK_RUN_POLICY) 983 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 984 else 985 BUG(); 986 987 if (reg != CCLK_BURST_POLICY_PLLX) { 988 /* restore PLLX settings if CPU is on different PLL */ 989 writel(tegra20_cpu_clk_sctx.pllx_misc, 990 clk_base + PLLX_MISC); 991 writel(tegra20_cpu_clk_sctx.pllx_base, 992 clk_base + PLLX_BASE); 993 994 /* wait for PLL stabilization if PLLX was enabled */ 995 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 996 udelay(300); 997 } 998 999 /* 1000 * Restore original burst policy setting for calls resulting from CPU 1001 * LP2 in idle or system suspend. 1002 */ 1003 writel(tegra20_cpu_clk_sctx.cclk_divider, 1004 clk_base + SUPER_CCLK_DIVIDER); 1005 writel(tegra20_cpu_clk_sctx.cpu_burst, 1006 clk_base + CCLK_BURST_POLICY); 1007 1008 writel(tegra20_cpu_clk_sctx.clk_csite_src, 1009 clk_base + CLK_SOURCE_CSITE); 1010 } 1011 #endif 1012 1013 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1014 .wait_for_reset = tegra20_wait_cpu_in_reset, 1015 .put_in_reset = tegra20_put_cpu_in_reset, 1016 .out_of_reset = tegra20_cpu_out_of_reset, 1017 .enable_clock = tegra20_enable_cpu_clock, 1018 .disable_clock = tegra20_disable_cpu_clock, 1019 #ifdef CONFIG_PM_SLEEP 1020 .rail_off_ready = tegra20_cpu_rail_off_ready, 1021 .suspend = tegra20_cpu_clock_suspend, 1022 .resume = tegra20_cpu_clock_resume, 1023 #endif 1024 }; 1025 1026 static struct tegra_clk_init_table init_table[] __initdata = { 1027 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 }, 1028 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 }, 1029 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 }, 1030 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, 1031 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, 1032 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, 1033 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, 1034 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, 1035 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, 1036 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, 1037 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1038 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1039 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 }, 1040 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 }, 1041 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 }, 1042 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 }, 1043 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 }, 1044 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 }, 1045 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 }, 1046 { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1047 { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 }, 1048 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1049 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1050 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1051 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1052 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1053 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, 1054 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1055 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1056 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1057 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1058 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, 1059 { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 }, 1060 { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 }, 1061 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1062 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1063 { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, 1064 /* must be the last entry */ 1065 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, 1066 }; 1067 1068 static void __init tegra20_clock_apply_init_table(void) 1069 { 1070 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); 1071 } 1072 1073 /* 1074 * Some clocks may be used by different drivers depending on the board 1075 * configuration. List those here to register them twice in the clock lookup 1076 * table under two names. 1077 */ 1078 static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1079 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL), 1080 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL), 1081 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL), 1082 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"), 1083 /* must be the last entry */ 1084 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), 1085 }; 1086 1087 static const struct of_device_id pmc_match[] __initconst = { 1088 { .compatible = "nvidia,tegra20-pmc" }, 1089 { }, 1090 }; 1091 1092 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, 1093 void *data) 1094 { 1095 struct clk_hw *parent_hw; 1096 struct clk_hw *hw; 1097 struct clk *clk; 1098 1099 clk = of_clk_src_onecell_get(clkspec, data); 1100 if (IS_ERR(clk)) 1101 return clk; 1102 1103 /* 1104 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent 1105 * clock is created by the pinctrl driver. It is possible for clk user 1106 * to request these clocks before pinctrl driver got probed and hence 1107 * user will get an orphaned clock. That might be undesirable because 1108 * user may expect parent clock to be enabled by the child. 1109 */ 1110 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || 1111 clkspec->args[0] == TEGRA20_CLK_CDEV2) { 1112 hw = __clk_get_hw(clk); 1113 1114 parent_hw = clk_hw_get_parent(hw); 1115 if (!parent_hw) 1116 return ERR_PTR(-EPROBE_DEFER); 1117 } 1118 1119 return clk; 1120 } 1121 1122 static void __init tegra20_clock_init(struct device_node *np) 1123 { 1124 struct device_node *node; 1125 1126 clk_base = of_iomap(np, 0); 1127 if (!clk_base) { 1128 pr_err("Can't map CAR registers\n"); 1129 BUG(); 1130 } 1131 1132 node = of_find_matching_node(NULL, pmc_match); 1133 if (!node) { 1134 pr_err("Failed to find pmc node\n"); 1135 BUG(); 1136 } 1137 1138 pmc_base = of_iomap(node, 0); 1139 if (!pmc_base) { 1140 pr_err("Can't map pmc registers\n"); 1141 BUG(); 1142 } 1143 1144 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, 1145 TEGRA20_CLK_PERIPH_BANKS); 1146 if (!clks) 1147 return; 1148 1149 tegra20_osc_clk_init(); 1150 tegra_fixed_clk_init(tegra20_clks); 1151 tegra20_pll_init(); 1152 tegra20_super_clk_init(); 1153 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); 1154 tegra20_periph_clk_init(); 1155 tegra20_audio_clk_init(); 1156 tegra_pmc_clk_init(pmc_base, tegra20_clks); 1157 1158 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); 1159 1160 tegra_add_of_provider(np, tegra20_clk_src_onecell_get); 1161 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1162 1163 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1164 1165 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1166 } 1167 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init); 1168