1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/clk/tegra.h> 12 #include <linux/delay.h> 13 #include <dt-bindings/clock/tegra20-car.h> 14 15 #include "clk.h" 16 #include "clk-id.h" 17 18 #define MISC_CLK_ENB 0x48 19 20 #define OSC_CTRL 0x50 21 #define OSC_CTRL_OSC_FREQ_MASK (3<<30) 22 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) 23 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) 24 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) 25 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) 26 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 27 28 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) 29 #define OSC_CTRL_PLL_REF_DIV_1 (0<<28) 30 #define OSC_CTRL_PLL_REF_DIV_2 (1<<28) 31 #define OSC_CTRL_PLL_REF_DIV_4 (2<<28) 32 33 #define OSC_FREQ_DET 0x58 34 #define OSC_FREQ_DET_TRIG (1<<31) 35 36 #define OSC_FREQ_DET_STATUS 0x5c 37 #define OSC_FREQ_DET_BUSY (1<<31) 38 #define OSC_FREQ_DET_CNT_MASK 0xFFFF 39 40 #define TEGRA20_CLK_PERIPH_BANKS 3 41 42 #define PLLS_BASE 0xf0 43 #define PLLS_MISC 0xf4 44 #define PLLC_BASE 0x80 45 #define PLLC_MISC 0x8c 46 #define PLLM_BASE 0x90 47 #define PLLM_MISC 0x9c 48 #define PLLP_BASE 0xa0 49 #define PLLP_MISC 0xac 50 #define PLLA_BASE 0xb0 51 #define PLLA_MISC 0xbc 52 #define PLLU_BASE 0xc0 53 #define PLLU_MISC 0xcc 54 #define PLLD_BASE 0xd0 55 #define PLLD_MISC 0xdc 56 #define PLLX_BASE 0xe0 57 #define PLLX_MISC 0xe4 58 #define PLLE_BASE 0xe8 59 #define PLLE_MISC 0xec 60 61 #define PLL_BASE_LOCK BIT(27) 62 #define PLLE_MISC_LOCK BIT(11) 63 64 #define PLL_MISC_LOCK_ENABLE 18 65 #define PLLDU_MISC_LOCK_ENABLE 22 66 #define PLLE_MISC_LOCK_ENABLE 9 67 68 #define PLLC_OUT 0x84 69 #define PLLM_OUT 0x94 70 #define PLLP_OUTA 0xa4 71 #define PLLP_OUTB 0xa8 72 #define PLLA_OUT 0xb4 73 74 #define CCLK_BURST_POLICY 0x20 75 #define SUPER_CCLK_DIVIDER 0x24 76 #define SCLK_BURST_POLICY 0x28 77 #define SUPER_SCLK_DIVIDER 0x2c 78 #define CLK_SYSTEM_RATE 0x30 79 80 #define CCLK_BURST_POLICY_SHIFT 28 81 #define CCLK_RUN_POLICY_SHIFT 4 82 #define CCLK_IDLE_POLICY_SHIFT 0 83 #define CCLK_IDLE_POLICY 1 84 #define CCLK_RUN_POLICY 2 85 #define CCLK_BURST_POLICY_PLLX 8 86 87 #define CLK_SOURCE_I2S1 0x100 88 #define CLK_SOURCE_I2S2 0x104 89 #define CLK_SOURCE_PWM 0x110 90 #define CLK_SOURCE_SPI 0x114 91 #define CLK_SOURCE_XIO 0x120 92 #define CLK_SOURCE_TWC 0x12c 93 #define CLK_SOURCE_IDE 0x144 94 #define CLK_SOURCE_HDMI 0x18c 95 #define CLK_SOURCE_DISP1 0x138 96 #define CLK_SOURCE_DISP2 0x13c 97 #define CLK_SOURCE_CSITE 0x1d4 98 #define CLK_SOURCE_I2C1 0x124 99 #define CLK_SOURCE_I2C2 0x198 100 #define CLK_SOURCE_I2C3 0x1b8 101 #define CLK_SOURCE_DVC 0x128 102 #define CLK_SOURCE_UARTA 0x178 103 #define CLK_SOURCE_UARTB 0x17c 104 #define CLK_SOURCE_UARTC 0x1a0 105 #define CLK_SOURCE_UARTD 0x1c0 106 #define CLK_SOURCE_UARTE 0x1c4 107 #define CLK_SOURCE_EMC 0x19c 108 109 #define AUDIO_SYNC_CLK 0x38 110 111 /* Tegra CPU clock and reset control regs */ 112 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 113 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 114 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 115 116 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 117 #define CPU_RESET(cpu) (0x1111ul << (cpu)) 118 119 #ifdef CONFIG_PM_SLEEP 120 static struct cpu_clk_suspend_context { 121 u32 pllx_misc; 122 u32 pllx_base; 123 124 u32 cpu_burst; 125 u32 clk_csite_src; 126 u32 cclk_divider; 127 } tegra20_cpu_clk_sctx; 128 #endif 129 130 static void __iomem *clk_base; 131 static void __iomem *pmc_base; 132 133 static DEFINE_SPINLOCK(emc_lock); 134 135 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 136 _clk_num, _gate_flags, _clk_id) \ 137 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 138 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 139 _clk_num, \ 140 _gate_flags, _clk_id) 141 142 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ 143 _clk_num, _gate_flags, _clk_id) \ 144 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 145 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 146 _clk_num, _gate_flags, \ 147 _clk_id) 148 149 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 150 _mux_shift, _mux_width, _clk_num, \ 151 _gate_flags, _clk_id) \ 152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 153 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ 154 _clk_num, _gate_flags, \ 155 _clk_id) 156 157 static struct clk **clks; 158 159 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 160 { 12000000, 600000000, 600, 12, 1, 8 }, 161 { 13000000, 600000000, 600, 13, 1, 8 }, 162 { 19200000, 600000000, 500, 16, 1, 6 }, 163 { 26000000, 600000000, 600, 26, 1, 8 }, 164 { 0, 0, 0, 0, 0, 0 }, 165 }; 166 167 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 168 { 12000000, 666000000, 666, 12, 1, 8 }, 169 { 13000000, 666000000, 666, 13, 1, 8 }, 170 { 19200000, 666000000, 555, 16, 1, 8 }, 171 { 26000000, 666000000, 666, 26, 1, 8 }, 172 { 12000000, 600000000, 600, 12, 1, 8 }, 173 { 13000000, 600000000, 600, 13, 1, 8 }, 174 { 19200000, 600000000, 375, 12, 1, 6 }, 175 { 26000000, 600000000, 600, 26, 1, 8 }, 176 { 0, 0, 0, 0, 0, 0 }, 177 }; 178 179 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 180 { 12000000, 216000000, 432, 12, 2, 8 }, 181 { 13000000, 216000000, 432, 13, 2, 8 }, 182 { 19200000, 216000000, 90, 4, 2, 1 }, 183 { 26000000, 216000000, 432, 26, 2, 8 }, 184 { 12000000, 432000000, 432, 12, 1, 8 }, 185 { 13000000, 432000000, 432, 13, 1, 8 }, 186 { 19200000, 432000000, 90, 4, 1, 1 }, 187 { 26000000, 432000000, 432, 26, 1, 8 }, 188 { 0, 0, 0, 0, 0, 0 }, 189 }; 190 191 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 192 { 28800000, 56448000, 49, 25, 1, 1 }, 193 { 28800000, 73728000, 64, 25, 1, 1 }, 194 { 28800000, 24000000, 5, 6, 1, 1 }, 195 { 0, 0, 0, 0, 0, 0 }, 196 }; 197 198 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 199 { 12000000, 216000000, 216, 12, 1, 4 }, 200 { 13000000, 216000000, 216, 13, 1, 4 }, 201 { 19200000, 216000000, 135, 12, 1, 3 }, 202 { 26000000, 216000000, 216, 26, 1, 4 }, 203 { 12000000, 594000000, 594, 12, 1, 8 }, 204 { 13000000, 594000000, 594, 13, 1, 8 }, 205 { 19200000, 594000000, 495, 16, 1, 8 }, 206 { 26000000, 594000000, 594, 26, 1, 8 }, 207 { 12000000, 1000000000, 1000, 12, 1, 12 }, 208 { 13000000, 1000000000, 1000, 13, 1, 12 }, 209 { 19200000, 1000000000, 625, 12, 1, 8 }, 210 { 26000000, 1000000000, 1000, 26, 1, 12 }, 211 { 0, 0, 0, 0, 0, 0 }, 212 }; 213 214 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 215 { 12000000, 480000000, 960, 12, 1, 0 }, 216 { 13000000, 480000000, 960, 13, 1, 0 }, 217 { 19200000, 480000000, 200, 4, 1, 0 }, 218 { 26000000, 480000000, 960, 26, 1, 0 }, 219 { 0, 0, 0, 0, 0, 0 }, 220 }; 221 222 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 223 /* 1 GHz */ 224 { 12000000, 1000000000, 1000, 12, 1, 12 }, 225 { 13000000, 1000000000, 1000, 13, 1, 12 }, 226 { 19200000, 1000000000, 625, 12, 1, 8 }, 227 { 26000000, 1000000000, 1000, 26, 1, 12 }, 228 /* 912 MHz */ 229 { 12000000, 912000000, 912, 12, 1, 12 }, 230 { 13000000, 912000000, 912, 13, 1, 12 }, 231 { 19200000, 912000000, 760, 16, 1, 8 }, 232 { 26000000, 912000000, 912, 26, 1, 12 }, 233 /* 816 MHz */ 234 { 12000000, 816000000, 816, 12, 1, 12 }, 235 { 13000000, 816000000, 816, 13, 1, 12 }, 236 { 19200000, 816000000, 680, 16, 1, 8 }, 237 { 26000000, 816000000, 816, 26, 1, 12 }, 238 /* 760 MHz */ 239 { 12000000, 760000000, 760, 12, 1, 12 }, 240 { 13000000, 760000000, 760, 13, 1, 12 }, 241 { 19200000, 760000000, 950, 24, 1, 8 }, 242 { 26000000, 760000000, 760, 26, 1, 12 }, 243 /* 750 MHz */ 244 { 12000000, 750000000, 750, 12, 1, 12 }, 245 { 13000000, 750000000, 750, 13, 1, 12 }, 246 { 19200000, 750000000, 625, 16, 1, 8 }, 247 { 26000000, 750000000, 750, 26, 1, 12 }, 248 /* 608 MHz */ 249 { 12000000, 608000000, 608, 12, 1, 12 }, 250 { 13000000, 608000000, 608, 13, 1, 12 }, 251 { 19200000, 608000000, 380, 12, 1, 8 }, 252 { 26000000, 608000000, 608, 26, 1, 12 }, 253 /* 456 MHz */ 254 { 12000000, 456000000, 456, 12, 1, 12 }, 255 { 13000000, 456000000, 456, 13, 1, 12 }, 256 { 19200000, 456000000, 380, 16, 1, 8 }, 257 { 26000000, 456000000, 456, 26, 1, 12 }, 258 /* 312 MHz */ 259 { 12000000, 312000000, 312, 12, 1, 12 }, 260 { 13000000, 312000000, 312, 13, 1, 12 }, 261 { 19200000, 312000000, 260, 16, 1, 8 }, 262 { 26000000, 312000000, 312, 26, 1, 12 }, 263 { 0, 0, 0, 0, 0, 0 }, 264 }; 265 266 static const struct pdiv_map plle_p[] = { 267 { .pdiv = 1, .hw_val = 1 }, 268 { .pdiv = 0, .hw_val = 0 }, 269 }; 270 271 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 272 { 12000000, 100000000, 200, 24, 1, 0 }, 273 { 0, 0, 0, 0, 0, 0 }, 274 }; 275 276 /* PLL parameters */ 277 static struct tegra_clk_pll_params pll_c_params = { 278 .input_min = 2000000, 279 .input_max = 31000000, 280 .cf_min = 1000000, 281 .cf_max = 6000000, 282 .vco_min = 20000000, 283 .vco_max = 1400000000, 284 .base_reg = PLLC_BASE, 285 .misc_reg = PLLC_MISC, 286 .lock_mask = PLL_BASE_LOCK, 287 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 288 .lock_delay = 300, 289 .freq_table = pll_c_freq_table, 290 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 291 }; 292 293 static struct tegra_clk_pll_params pll_m_params = { 294 .input_min = 2000000, 295 .input_max = 31000000, 296 .cf_min = 1000000, 297 .cf_max = 6000000, 298 .vco_min = 20000000, 299 .vco_max = 1200000000, 300 .base_reg = PLLM_BASE, 301 .misc_reg = PLLM_MISC, 302 .lock_mask = PLL_BASE_LOCK, 303 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 304 .lock_delay = 300, 305 .freq_table = pll_m_freq_table, 306 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 307 }; 308 309 static struct tegra_clk_pll_params pll_p_params = { 310 .input_min = 2000000, 311 .input_max = 31000000, 312 .cf_min = 1000000, 313 .cf_max = 6000000, 314 .vco_min = 20000000, 315 .vco_max = 1400000000, 316 .base_reg = PLLP_BASE, 317 .misc_reg = PLLP_MISC, 318 .lock_mask = PLL_BASE_LOCK, 319 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 320 .lock_delay = 300, 321 .freq_table = pll_p_freq_table, 322 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 323 TEGRA_PLL_HAS_LOCK_ENABLE, 324 .fixed_rate = 216000000, 325 }; 326 327 static struct tegra_clk_pll_params pll_a_params = { 328 .input_min = 2000000, 329 .input_max = 31000000, 330 .cf_min = 1000000, 331 .cf_max = 6000000, 332 .vco_min = 20000000, 333 .vco_max = 1400000000, 334 .base_reg = PLLA_BASE, 335 .misc_reg = PLLA_MISC, 336 .lock_mask = PLL_BASE_LOCK, 337 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 338 .lock_delay = 300, 339 .freq_table = pll_a_freq_table, 340 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 341 }; 342 343 static struct tegra_clk_pll_params pll_d_params = { 344 .input_min = 2000000, 345 .input_max = 40000000, 346 .cf_min = 1000000, 347 .cf_max = 6000000, 348 .vco_min = 40000000, 349 .vco_max = 1000000000, 350 .base_reg = PLLD_BASE, 351 .misc_reg = PLLD_MISC, 352 .lock_mask = PLL_BASE_LOCK, 353 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 354 .lock_delay = 1000, 355 .freq_table = pll_d_freq_table, 356 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 357 }; 358 359 static const struct pdiv_map pllu_p[] = { 360 { .pdiv = 1, .hw_val = 1 }, 361 { .pdiv = 2, .hw_val = 0 }, 362 { .pdiv = 0, .hw_val = 0 }, 363 }; 364 365 static struct tegra_clk_pll_params pll_u_params = { 366 .input_min = 2000000, 367 .input_max = 40000000, 368 .cf_min = 1000000, 369 .cf_max = 6000000, 370 .vco_min = 48000000, 371 .vco_max = 960000000, 372 .base_reg = PLLU_BASE, 373 .misc_reg = PLLU_MISC, 374 .lock_mask = PLL_BASE_LOCK, 375 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 376 .lock_delay = 1000, 377 .pdiv_tohw = pllu_p, 378 .freq_table = pll_u_freq_table, 379 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 380 }; 381 382 static struct tegra_clk_pll_params pll_x_params = { 383 .input_min = 2000000, 384 .input_max = 31000000, 385 .cf_min = 1000000, 386 .cf_max = 6000000, 387 .vco_min = 20000000, 388 .vco_max = 1200000000, 389 .base_reg = PLLX_BASE, 390 .misc_reg = PLLX_MISC, 391 .lock_mask = PLL_BASE_LOCK, 392 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 393 .lock_delay = 300, 394 .freq_table = pll_x_freq_table, 395 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 396 }; 397 398 static struct tegra_clk_pll_params pll_e_params = { 399 .input_min = 12000000, 400 .input_max = 12000000, 401 .cf_min = 0, 402 .cf_max = 0, 403 .vco_min = 0, 404 .vco_max = 0, 405 .base_reg = PLLE_BASE, 406 .misc_reg = PLLE_MISC, 407 .lock_mask = PLLE_MISC_LOCK, 408 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 409 .lock_delay = 0, 410 .pdiv_tohw = plle_p, 411 .freq_table = pll_e_freq_table, 412 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | 413 TEGRA_PLL_HAS_LOCK_ENABLE, 414 .fixed_rate = 100000000, 415 }; 416 417 static struct tegra_devclk devclks[] __initdata = { 418 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C }, 419 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 }, 420 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P }, 421 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 }, 422 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 }, 423 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 }, 424 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 }, 425 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M }, 426 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 }, 427 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X }, 428 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U }, 429 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D }, 430 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 }, 431 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A }, 432 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 }, 433 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E }, 434 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK }, 435 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK }, 436 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK }, 437 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK }, 438 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE }, 439 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD }, 440 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO }, 441 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X }, 442 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 }, 443 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA }, 444 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC }, 445 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER }, 446 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC }, 447 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS }, 448 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP }, 449 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA }, 450 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV }, 451 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC }, 452 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD }, 453 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 }, 454 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 }, 455 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI }, 456 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI }, 457 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP }, 458 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX }, 459 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI }, 460 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 }, 461 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 }, 462 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K }, 463 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK }, 464 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M }, 465 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF }, 466 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 }, 467 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 }, 468 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT }, 469 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN }, 470 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 }, 471 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 }, 472 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 }, 473 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 }, 474 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI }, 475 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO }, 476 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC }, 477 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE }, 478 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH }, 479 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR }, 480 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE }, 481 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA }, 482 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR }, 483 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI }, 484 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE }, 485 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI }, 486 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP }, 487 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE }, 488 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X }, 489 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D }, 490 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D }, 491 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR }, 492 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 }, 493 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 }, 494 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 }, 495 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 }, 496 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE }, 497 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO }, 498 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC }, 499 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR }, 500 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI }, 501 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 }, 502 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 }, 503 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 }, 504 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC }, 505 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM }, 506 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA }, 507 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB }, 508 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC }, 509 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD }, 510 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE }, 511 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 }, 512 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 }, 513 }; 514 515 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { 516 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true }, 517 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true }, 518 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, 519 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, 520 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, 521 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true }, 522 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true }, 523 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true }, 524 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true }, 525 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true }, 526 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true }, 527 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true }, 528 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true }, 529 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true }, 530 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true }, 531 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true }, 532 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true }, 533 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true }, 534 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true }, 535 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true }, 536 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true }, 537 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true }, 538 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true }, 539 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true }, 540 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true }, 541 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true }, 542 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true }, 543 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true }, 544 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true }, 545 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true }, 546 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true }, 547 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true }, 548 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true }, 549 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true }, 550 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true }, 551 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true }, 552 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true }, 553 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true }, 554 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true }, 555 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true }, 556 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true }, 557 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true }, 558 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true }, 559 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true }, 560 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true }, 561 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true }, 562 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true }, 563 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true }, 564 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true }, 565 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true }, 566 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true }, 567 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, 568 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, 569 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, 570 }; 571 572 static unsigned long tegra20_clk_measure_input_freq(void) 573 { 574 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 575 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 576 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 577 unsigned long input_freq; 578 579 switch (auto_clk_control) { 580 case OSC_CTRL_OSC_FREQ_12MHZ: 581 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 582 input_freq = 12000000; 583 break; 584 case OSC_CTRL_OSC_FREQ_13MHZ: 585 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 586 input_freq = 13000000; 587 break; 588 case OSC_CTRL_OSC_FREQ_19_2MHZ: 589 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 590 input_freq = 19200000; 591 break; 592 case OSC_CTRL_OSC_FREQ_26MHZ: 593 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 594 input_freq = 26000000; 595 break; 596 default: 597 pr_err("Unexpected clock autodetect value %d", 598 auto_clk_control); 599 BUG(); 600 return 0; 601 } 602 603 return input_freq; 604 } 605 606 static unsigned int tegra20_get_pll_ref_div(void) 607 { 608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 609 OSC_CTRL_PLL_REF_DIV_MASK; 610 611 switch (pll_ref_div) { 612 case OSC_CTRL_PLL_REF_DIV_1: 613 return 1; 614 case OSC_CTRL_PLL_REF_DIV_2: 615 return 2; 616 case OSC_CTRL_PLL_REF_DIV_4: 617 return 4; 618 default: 619 pr_err("Invalid pll ref divider %d\n", pll_ref_div); 620 BUG(); 621 } 622 return 0; 623 } 624 625 static void tegra20_pll_init(void) 626 { 627 struct clk *clk; 628 629 /* PLLC */ 630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 631 &pll_c_params, NULL); 632 clks[TEGRA20_CLK_PLL_C] = clk; 633 634 /* PLLC_OUT1 */ 635 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 636 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 637 8, 8, 1, NULL); 638 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 639 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 640 0, NULL); 641 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; 642 643 /* PLLM */ 644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 645 CLK_SET_RATE_GATE, &pll_m_params, NULL); 646 clks[TEGRA20_CLK_PLL_M] = clk; 647 648 /* PLLM_OUT1 */ 649 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 650 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 651 8, 8, 1, NULL); 652 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 653 clk_base + PLLM_OUT, 1, 0, 654 CLK_SET_RATE_PARENT, 0, NULL); 655 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; 656 657 /* PLLX */ 658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 659 &pll_x_params, NULL); 660 clks[TEGRA20_CLK_PLL_X] = clk; 661 662 /* PLLU */ 663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 664 &pll_u_params, NULL); 665 clks[TEGRA20_CLK_PLL_U] = clk; 666 667 /* PLLD */ 668 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 669 &pll_d_params, NULL); 670 clks[TEGRA20_CLK_PLL_D] = clk; 671 672 /* PLLD_OUT0 */ 673 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 674 CLK_SET_RATE_PARENT, 1, 2); 675 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; 676 677 /* PLLA */ 678 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 679 &pll_a_params, NULL); 680 clks[TEGRA20_CLK_PLL_A] = clk; 681 682 /* PLLA_OUT0 */ 683 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 684 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 685 8, 8, 1, NULL); 686 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 687 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 688 CLK_SET_RATE_PARENT, 0, NULL); 689 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; 690 691 /* PLLE */ 692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 693 0, &pll_e_params, NULL); 694 clks[TEGRA20_CLK_PLL_E] = clk; 695 } 696 697 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 698 "pll_p", "pll_p_out4", 699 "pll_p_out3", "clk_d", "pll_x" }; 700 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 701 "pll_p_out3", "pll_p_out2", "clk_d", 702 "clk_32k", "pll_m_out1" }; 703 704 static void tegra20_super_clk_init(void) 705 { 706 struct clk *clk; 707 708 /* CCLK */ 709 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 710 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 711 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 712 clks[TEGRA20_CLK_CCLK] = clk; 713 714 /* SCLK */ 715 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 716 ARRAY_SIZE(sclk_parents), 717 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 718 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 719 clks[TEGRA20_CLK_SCLK] = clk; 720 721 /* twd */ 722 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 723 clks[TEGRA20_CLK_TWD] = clk; 724 } 725 726 static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused", 727 "pll_a_out0", "unused", "unused", 728 "unused" }; 729 730 static void __init tegra20_audio_clk_init(void) 731 { 732 struct clk *clk; 733 734 /* audio */ 735 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 736 ARRAY_SIZE(audio_parents), 737 CLK_SET_RATE_NO_REPARENT, 738 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 739 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 740 clk_base + AUDIO_SYNC_CLK, 4, 741 CLK_GATE_SET_TO_DISABLE, NULL); 742 clks[TEGRA20_CLK_AUDIO] = clk; 743 744 /* audio_2x */ 745 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 746 CLK_SET_RATE_PARENT, 2, 1); 747 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 748 TEGRA_PERIPH_NO_RESET, clk_base, 749 CLK_SET_RATE_PARENT, 89, 750 periph_clk_enb_refcnt); 751 clks[TEGRA20_CLK_AUDIO_2X] = clk; 752 } 753 754 static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 755 "clk_m" }; 756 static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 757 "clk_m" }; 758 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m", 759 "clk_32k" }; 760 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 761 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 762 "clk_m" }; 763 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 764 765 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 766 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1), 767 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2), 768 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI), 769 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO), 770 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC), 771 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE), 772 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC), 773 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1), 774 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2), 775 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3), 776 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI), 777 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM), 778 }; 779 780 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 781 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA), 782 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB), 783 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC), 784 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD), 785 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE), 786 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1), 787 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), 788 }; 789 790 static void __init tegra20_emc_clk_init(void) 791 { 792 const u32 use_pllm_ud = BIT(29); 793 struct clk *clk; 794 u32 emc_reg; 795 796 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 797 ARRAY_SIZE(mux_pllmcp_clkm), 798 CLK_SET_RATE_NO_REPARENT, 799 clk_base + CLK_SOURCE_EMC, 800 30, 2, 0, &emc_lock); 801 802 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 803 &emc_lock); 804 clks[TEGRA20_CLK_MC] = clk; 805 806 /* un-divided pll_m_out0 is currently unsupported */ 807 emc_reg = readl_relaxed(clk_base + CLK_SOURCE_EMC); 808 if (emc_reg & use_pllm_ud) { 809 pr_err("%s: un-divided PllM_out0 used as clock source\n", 810 __func__); 811 return; 812 } 813 814 /* 815 * Note that 'emc_mux' source and 'emc' rate shouldn't be changed at 816 * the same time due to a HW bug, this won't happen because we're 817 * defining 'emc_mux' and 'emc' as distinct clocks. 818 */ 819 clk = tegra_clk_register_divider("emc", "emc_mux", 820 clk_base + CLK_SOURCE_EMC, CLK_IS_CRITICAL, 821 TEGRA_DIVIDER_INT, 0, 8, 1, &emc_lock); 822 clks[TEGRA20_CLK_EMC] = clk; 823 } 824 825 static void __init tegra20_periph_clk_init(void) 826 { 827 struct tegra_periph_init_data *data; 828 struct clk *clk; 829 unsigned int i; 830 831 /* ac97 */ 832 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 833 TEGRA_PERIPH_ON_APB, 834 clk_base, 0, 3, periph_clk_enb_refcnt); 835 clks[TEGRA20_CLK_AC97] = clk; 836 837 /* emc */ 838 tegra20_emc_clk_init(); 839 840 /* dsi */ 841 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 842 48, periph_clk_enb_refcnt); 843 clk_register_clkdev(clk, NULL, "dsi"); 844 clks[TEGRA20_CLK_DSI] = clk; 845 846 /* pex */ 847 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 848 periph_clk_enb_refcnt); 849 clks[TEGRA20_CLK_PEX] = clk; 850 851 /* dev1 OSC divider */ 852 clk_register_divider(NULL, "dev1_osc_div", "clk_m", 853 0, clk_base + MISC_CLK_ENB, 22, 2, 854 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 855 NULL); 856 857 /* dev2 OSC divider */ 858 clk_register_divider(NULL, "dev2_osc_div", "clk_m", 859 0, clk_base + MISC_CLK_ENB, 20, 2, 860 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 861 NULL); 862 863 /* cdev1 */ 864 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, 865 clk_base, 0, 94, periph_clk_enb_refcnt); 866 clks[TEGRA20_CLK_CDEV1] = clk; 867 868 /* cdev2 */ 869 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, 870 clk_base, 0, 93, periph_clk_enb_refcnt); 871 clks[TEGRA20_CLK_CDEV2] = clk; 872 873 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 874 data = &tegra_periph_clk_list[i]; 875 clk = tegra_clk_register_periph_data(clk_base, data); 876 clks[data->clk_id] = clk; 877 } 878 879 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 880 data = &tegra_periph_nodiv_clk_list[i]; 881 clk = tegra_clk_register_periph_nodiv(data->name, 882 data->p.parent_names, 883 data->num_parents, &data->periph, 884 clk_base, data->offset); 885 clks[data->clk_id] = clk; 886 } 887 888 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); 889 } 890 891 static void __init tegra20_osc_clk_init(void) 892 { 893 struct clk *clk; 894 unsigned long input_freq; 895 unsigned int pll_ref_div; 896 897 input_freq = tegra20_clk_measure_input_freq(); 898 899 /* clk_m */ 900 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED, 901 input_freq); 902 clks[TEGRA20_CLK_CLK_M] = clk; 903 904 /* pll_ref */ 905 pll_ref_div = tegra20_get_pll_ref_div(); 906 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 907 CLK_SET_RATE_PARENT, 1, pll_ref_div); 908 clks[TEGRA20_CLK_PLL_REF] = clk; 909 } 910 911 /* Tegra20 CPU clock and reset control functions */ 912 static void tegra20_wait_cpu_in_reset(u32 cpu) 913 { 914 unsigned int reg; 915 916 do { 917 reg = readl(clk_base + 918 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 919 cpu_relax(); 920 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 921 922 return; 923 } 924 925 static void tegra20_put_cpu_in_reset(u32 cpu) 926 { 927 writel(CPU_RESET(cpu), 928 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 929 dmb(); 930 } 931 932 static void tegra20_cpu_out_of_reset(u32 cpu) 933 { 934 writel(CPU_RESET(cpu), 935 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 936 wmb(); 937 } 938 939 static void tegra20_enable_cpu_clock(u32 cpu) 940 { 941 unsigned int reg; 942 943 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 944 writel(reg & ~CPU_CLOCK(cpu), 945 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 946 barrier(); 947 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 948 } 949 950 static void tegra20_disable_cpu_clock(u32 cpu) 951 { 952 unsigned int reg; 953 954 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 955 writel(reg | CPU_CLOCK(cpu), 956 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 957 } 958 959 #ifdef CONFIG_PM_SLEEP 960 static bool tegra20_cpu_rail_off_ready(void) 961 { 962 unsigned int cpu_rst_status; 963 964 cpu_rst_status = readl(clk_base + 965 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 966 967 return !!(cpu_rst_status & 0x2); 968 } 969 970 static void tegra20_cpu_clock_suspend(void) 971 { 972 /* switch coresite to clk_m, save off original source */ 973 tegra20_cpu_clk_sctx.clk_csite_src = 974 readl(clk_base + CLK_SOURCE_CSITE); 975 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 976 977 tegra20_cpu_clk_sctx.cpu_burst = 978 readl(clk_base + CCLK_BURST_POLICY); 979 tegra20_cpu_clk_sctx.pllx_base = 980 readl(clk_base + PLLX_BASE); 981 tegra20_cpu_clk_sctx.pllx_misc = 982 readl(clk_base + PLLX_MISC); 983 tegra20_cpu_clk_sctx.cclk_divider = 984 readl(clk_base + SUPER_CCLK_DIVIDER); 985 } 986 987 static void tegra20_cpu_clock_resume(void) 988 { 989 unsigned int reg, policy; 990 991 /* Is CPU complex already running on PLLX? */ 992 reg = readl(clk_base + CCLK_BURST_POLICY); 993 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 994 995 if (policy == CCLK_IDLE_POLICY) 996 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 997 else if (policy == CCLK_RUN_POLICY) 998 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 999 else 1000 BUG(); 1001 1002 if (reg != CCLK_BURST_POLICY_PLLX) { 1003 /* restore PLLX settings if CPU is on different PLL */ 1004 writel(tegra20_cpu_clk_sctx.pllx_misc, 1005 clk_base + PLLX_MISC); 1006 writel(tegra20_cpu_clk_sctx.pllx_base, 1007 clk_base + PLLX_BASE); 1008 1009 /* wait for PLL stabilization if PLLX was enabled */ 1010 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 1011 udelay(300); 1012 } 1013 1014 /* 1015 * Restore original burst policy setting for calls resulting from CPU 1016 * LP2 in idle or system suspend. 1017 */ 1018 writel(tegra20_cpu_clk_sctx.cclk_divider, 1019 clk_base + SUPER_CCLK_DIVIDER); 1020 writel(tegra20_cpu_clk_sctx.cpu_burst, 1021 clk_base + CCLK_BURST_POLICY); 1022 1023 writel(tegra20_cpu_clk_sctx.clk_csite_src, 1024 clk_base + CLK_SOURCE_CSITE); 1025 } 1026 #endif 1027 1028 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1029 .wait_for_reset = tegra20_wait_cpu_in_reset, 1030 .put_in_reset = tegra20_put_cpu_in_reset, 1031 .out_of_reset = tegra20_cpu_out_of_reset, 1032 .enable_clock = tegra20_enable_cpu_clock, 1033 .disable_clock = tegra20_disable_cpu_clock, 1034 #ifdef CONFIG_PM_SLEEP 1035 .rail_off_ready = tegra20_cpu_rail_off_ready, 1036 .suspend = tegra20_cpu_clock_suspend, 1037 .resume = tegra20_cpu_clock_resume, 1038 #endif 1039 }; 1040 1041 static struct tegra_clk_init_table init_table[] __initdata = { 1042 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 }, 1043 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 }, 1044 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 }, 1045 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, 1046 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, 1047 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, 1048 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, 1049 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, 1050 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, 1051 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, 1052 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1053 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1054 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 }, 1055 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 }, 1056 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 }, 1057 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 }, 1058 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 }, 1059 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 }, 1060 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 }, 1061 { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1062 { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 }, 1063 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1064 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1065 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1066 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1067 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1068 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, 1069 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1070 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1071 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1072 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1073 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, 1074 { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 }, 1075 { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 }, 1076 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1077 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1078 { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, 1079 /* must be the last entry */ 1080 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, 1081 }; 1082 1083 static void __init tegra20_clock_apply_init_table(void) 1084 { 1085 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); 1086 } 1087 1088 /* 1089 * Some clocks may be used by different drivers depending on the board 1090 * configuration. List those here to register them twice in the clock lookup 1091 * table under two names. 1092 */ 1093 static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1094 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL), 1095 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL), 1096 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL), 1097 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"), 1098 /* must be the last entry */ 1099 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), 1100 }; 1101 1102 static const struct of_device_id pmc_match[] __initconst = { 1103 { .compatible = "nvidia,tegra20-pmc" }, 1104 { }, 1105 }; 1106 1107 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, 1108 void *data) 1109 { 1110 struct clk_hw *parent_hw; 1111 struct clk_hw *hw; 1112 struct clk *clk; 1113 1114 clk = of_clk_src_onecell_get(clkspec, data); 1115 if (IS_ERR(clk)) 1116 return clk; 1117 1118 /* 1119 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent 1120 * clock is created by the pinctrl driver. It is possible for clk user 1121 * to request these clocks before pinctrl driver got probed and hence 1122 * user will get an orphaned clock. That might be undesirable because 1123 * user may expect parent clock to be enabled by the child. 1124 */ 1125 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || 1126 clkspec->args[0] == TEGRA20_CLK_CDEV2) { 1127 hw = __clk_get_hw(clk); 1128 1129 parent_hw = clk_hw_get_parent(hw); 1130 if (!parent_hw) 1131 return ERR_PTR(-EPROBE_DEFER); 1132 } 1133 1134 return clk; 1135 } 1136 1137 static void __init tegra20_clock_init(struct device_node *np) 1138 { 1139 struct device_node *node; 1140 1141 clk_base = of_iomap(np, 0); 1142 if (!clk_base) { 1143 pr_err("Can't map CAR registers\n"); 1144 BUG(); 1145 } 1146 1147 node = of_find_matching_node(NULL, pmc_match); 1148 if (!node) { 1149 pr_err("Failed to find pmc node\n"); 1150 BUG(); 1151 } 1152 1153 pmc_base = of_iomap(node, 0); 1154 if (!pmc_base) { 1155 pr_err("Can't map pmc registers\n"); 1156 BUG(); 1157 } 1158 1159 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, 1160 TEGRA20_CLK_PERIPH_BANKS); 1161 if (!clks) 1162 return; 1163 1164 tegra20_osc_clk_init(); 1165 tegra_fixed_clk_init(tegra20_clks); 1166 tegra20_pll_init(); 1167 tegra20_super_clk_init(); 1168 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); 1169 tegra20_periph_clk_init(); 1170 tegra20_audio_clk_init(); 1171 tegra_pmc_clk_init(pmc_base, tegra20_clks); 1172 1173 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); 1174 1175 tegra_add_of_provider(np, tegra20_clk_src_onecell_get); 1176 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1177 1178 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1179 1180 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1181 } 1182 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init); 1183