1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/clkdev.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/clk/tegra.h> 24 #include <linux/delay.h> 25 #include <dt-bindings/clock/tegra20-car.h> 26 27 #include "clk.h" 28 #include "clk-id.h" 29 30 #define OSC_CTRL 0x50 31 #define OSC_CTRL_OSC_FREQ_MASK (3<<30) 32 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) 33 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) 34 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) 35 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) 36 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 37 38 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) 39 #define OSC_CTRL_PLL_REF_DIV_1 (0<<28) 40 #define OSC_CTRL_PLL_REF_DIV_2 (1<<28) 41 #define OSC_CTRL_PLL_REF_DIV_4 (2<<28) 42 43 #define OSC_FREQ_DET 0x58 44 #define OSC_FREQ_DET_TRIG (1<<31) 45 46 #define OSC_FREQ_DET_STATUS 0x5c 47 #define OSC_FREQ_DET_BUSY (1<<31) 48 #define OSC_FREQ_DET_CNT_MASK 0xFFFF 49 50 #define TEGRA20_CLK_PERIPH_BANKS 3 51 52 #define PLLS_BASE 0xf0 53 #define PLLS_MISC 0xf4 54 #define PLLC_BASE 0x80 55 #define PLLC_MISC 0x8c 56 #define PLLM_BASE 0x90 57 #define PLLM_MISC 0x9c 58 #define PLLP_BASE 0xa0 59 #define PLLP_MISC 0xac 60 #define PLLA_BASE 0xb0 61 #define PLLA_MISC 0xbc 62 #define PLLU_BASE 0xc0 63 #define PLLU_MISC 0xcc 64 #define PLLD_BASE 0xd0 65 #define PLLD_MISC 0xdc 66 #define PLLX_BASE 0xe0 67 #define PLLX_MISC 0xe4 68 #define PLLE_BASE 0xe8 69 #define PLLE_MISC 0xec 70 71 #define PLL_BASE_LOCK BIT(27) 72 #define PLLE_MISC_LOCK BIT(11) 73 74 #define PLL_MISC_LOCK_ENABLE 18 75 #define PLLDU_MISC_LOCK_ENABLE 22 76 #define PLLE_MISC_LOCK_ENABLE 9 77 78 #define PLLC_OUT 0x84 79 #define PLLM_OUT 0x94 80 #define PLLP_OUTA 0xa4 81 #define PLLP_OUTB 0xa8 82 #define PLLA_OUT 0xb4 83 84 #define CCLK_BURST_POLICY 0x20 85 #define SUPER_CCLK_DIVIDER 0x24 86 #define SCLK_BURST_POLICY 0x28 87 #define SUPER_SCLK_DIVIDER 0x2c 88 #define CLK_SYSTEM_RATE 0x30 89 90 #define CCLK_BURST_POLICY_SHIFT 28 91 #define CCLK_RUN_POLICY_SHIFT 4 92 #define CCLK_IDLE_POLICY_SHIFT 0 93 #define CCLK_IDLE_POLICY 1 94 #define CCLK_RUN_POLICY 2 95 #define CCLK_BURST_POLICY_PLLX 8 96 97 #define CLK_SOURCE_I2S1 0x100 98 #define CLK_SOURCE_I2S2 0x104 99 #define CLK_SOURCE_PWM 0x110 100 #define CLK_SOURCE_SPI 0x114 101 #define CLK_SOURCE_XIO 0x120 102 #define CLK_SOURCE_TWC 0x12c 103 #define CLK_SOURCE_IDE 0x144 104 #define CLK_SOURCE_HDMI 0x18c 105 #define CLK_SOURCE_DISP1 0x138 106 #define CLK_SOURCE_DISP2 0x13c 107 #define CLK_SOURCE_CSITE 0x1d4 108 #define CLK_SOURCE_I2C1 0x124 109 #define CLK_SOURCE_I2C2 0x198 110 #define CLK_SOURCE_I2C3 0x1b8 111 #define CLK_SOURCE_DVC 0x128 112 #define CLK_SOURCE_UARTA 0x178 113 #define CLK_SOURCE_UARTB 0x17c 114 #define CLK_SOURCE_UARTC 0x1a0 115 #define CLK_SOURCE_UARTD 0x1c0 116 #define CLK_SOURCE_UARTE 0x1c4 117 #define CLK_SOURCE_EMC 0x19c 118 119 #define AUDIO_SYNC_CLK 0x38 120 121 /* Tegra CPU clock and reset control regs */ 122 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 123 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 124 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 125 126 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 127 #define CPU_RESET(cpu) (0x1111ul << (cpu)) 128 129 #ifdef CONFIG_PM_SLEEP 130 static struct cpu_clk_suspend_context { 131 u32 pllx_misc; 132 u32 pllx_base; 133 134 u32 cpu_burst; 135 u32 clk_csite_src; 136 u32 cclk_divider; 137 } tegra20_cpu_clk_sctx; 138 #endif 139 140 static void __iomem *clk_base; 141 static void __iomem *pmc_base; 142 143 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 144 _clk_num, _gate_flags, _clk_id) \ 145 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 146 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 147 _clk_num, \ 148 _gate_flags, _clk_id) 149 150 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ 151 _clk_num, _gate_flags, _clk_id) \ 152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 153 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 154 _clk_num, _gate_flags, \ 155 _clk_id) 156 157 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 158 _mux_shift, _mux_width, _clk_num, \ 159 _gate_flags, _clk_id) \ 160 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 161 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ 162 _clk_num, _gate_flags, \ 163 _clk_id) 164 165 static struct clk **clks; 166 167 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 168 { 12000000, 600000000, 600, 12, 0, 8 }, 169 { 13000000, 600000000, 600, 13, 0, 8 }, 170 { 19200000, 600000000, 500, 16, 0, 6 }, 171 { 26000000, 600000000, 600, 26, 0, 8 }, 172 { 0, 0, 0, 0, 0, 0 }, 173 }; 174 175 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 176 { 12000000, 666000000, 666, 12, 0, 8}, 177 { 13000000, 666000000, 666, 13, 0, 8}, 178 { 19200000, 666000000, 555, 16, 0, 8}, 179 { 26000000, 666000000, 666, 26, 0, 8}, 180 { 12000000, 600000000, 600, 12, 0, 8}, 181 { 13000000, 600000000, 600, 13, 0, 8}, 182 { 19200000, 600000000, 375, 12, 0, 6}, 183 { 26000000, 600000000, 600, 26, 0, 8}, 184 { 0, 0, 0, 0, 0, 0 }, 185 }; 186 187 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 188 { 12000000, 216000000, 432, 12, 1, 8}, 189 { 13000000, 216000000, 432, 13, 1, 8}, 190 { 19200000, 216000000, 90, 4, 1, 1}, 191 { 26000000, 216000000, 432, 26, 1, 8}, 192 { 12000000, 432000000, 432, 12, 0, 8}, 193 { 13000000, 432000000, 432, 13, 0, 8}, 194 { 19200000, 432000000, 90, 4, 0, 1}, 195 { 26000000, 432000000, 432, 26, 0, 8}, 196 { 0, 0, 0, 0, 0, 0 }, 197 }; 198 199 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 200 { 28800000, 56448000, 49, 25, 0, 1}, 201 { 28800000, 73728000, 64, 25, 0, 1}, 202 { 28800000, 24000000, 5, 6, 0, 1}, 203 { 0, 0, 0, 0, 0, 0 }, 204 }; 205 206 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 207 { 12000000, 216000000, 216, 12, 0, 4}, 208 { 13000000, 216000000, 216, 13, 0, 4}, 209 { 19200000, 216000000, 135, 12, 0, 3}, 210 { 26000000, 216000000, 216, 26, 0, 4}, 211 212 { 12000000, 594000000, 594, 12, 0, 8}, 213 { 13000000, 594000000, 594, 13, 0, 8}, 214 { 19200000, 594000000, 495, 16, 0, 8}, 215 { 26000000, 594000000, 594, 26, 0, 8}, 216 217 { 12000000, 1000000000, 1000, 12, 0, 12}, 218 { 13000000, 1000000000, 1000, 13, 0, 12}, 219 { 19200000, 1000000000, 625, 12, 0, 8}, 220 { 26000000, 1000000000, 1000, 26, 0, 12}, 221 222 { 0, 0, 0, 0, 0, 0 }, 223 }; 224 225 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 226 { 12000000, 480000000, 960, 12, 0, 0}, 227 { 13000000, 480000000, 960, 13, 0, 0}, 228 { 19200000, 480000000, 200, 4, 0, 0}, 229 { 26000000, 480000000, 960, 26, 0, 0}, 230 { 0, 0, 0, 0, 0, 0 }, 231 }; 232 233 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 234 /* 1 GHz */ 235 { 12000000, 1000000000, 1000, 12, 0, 12}, 236 { 13000000, 1000000000, 1000, 13, 0, 12}, 237 { 19200000, 1000000000, 625, 12, 0, 8}, 238 { 26000000, 1000000000, 1000, 26, 0, 12}, 239 240 /* 912 MHz */ 241 { 12000000, 912000000, 912, 12, 0, 12}, 242 { 13000000, 912000000, 912, 13, 0, 12}, 243 { 19200000, 912000000, 760, 16, 0, 8}, 244 { 26000000, 912000000, 912, 26, 0, 12}, 245 246 /* 816 MHz */ 247 { 12000000, 816000000, 816, 12, 0, 12}, 248 { 13000000, 816000000, 816, 13, 0, 12}, 249 { 19200000, 816000000, 680, 16, 0, 8}, 250 { 26000000, 816000000, 816, 26, 0, 12}, 251 252 /* 760 MHz */ 253 { 12000000, 760000000, 760, 12, 0, 12}, 254 { 13000000, 760000000, 760, 13, 0, 12}, 255 { 19200000, 760000000, 950, 24, 0, 8}, 256 { 26000000, 760000000, 760, 26, 0, 12}, 257 258 /* 750 MHz */ 259 { 12000000, 750000000, 750, 12, 0, 12}, 260 { 13000000, 750000000, 750, 13, 0, 12}, 261 { 19200000, 750000000, 625, 16, 0, 8}, 262 { 26000000, 750000000, 750, 26, 0, 12}, 263 264 /* 608 MHz */ 265 { 12000000, 608000000, 608, 12, 0, 12}, 266 { 13000000, 608000000, 608, 13, 0, 12}, 267 { 19200000, 608000000, 380, 12, 0, 8}, 268 { 26000000, 608000000, 608, 26, 0, 12}, 269 270 /* 456 MHz */ 271 { 12000000, 456000000, 456, 12, 0, 12}, 272 { 13000000, 456000000, 456, 13, 0, 12}, 273 { 19200000, 456000000, 380, 16, 0, 8}, 274 { 26000000, 456000000, 456, 26, 0, 12}, 275 276 /* 312 MHz */ 277 { 12000000, 312000000, 312, 12, 0, 12}, 278 { 13000000, 312000000, 312, 13, 0, 12}, 279 { 19200000, 312000000, 260, 16, 0, 8}, 280 { 26000000, 312000000, 312, 26, 0, 12}, 281 282 { 0, 0, 0, 0, 0, 0 }, 283 }; 284 285 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 286 { 12000000, 100000000, 200, 24, 0, 0 }, 287 { 0, 0, 0, 0, 0, 0 }, 288 }; 289 290 /* PLL parameters */ 291 static struct tegra_clk_pll_params pll_c_params = { 292 .input_min = 2000000, 293 .input_max = 31000000, 294 .cf_min = 1000000, 295 .cf_max = 6000000, 296 .vco_min = 20000000, 297 .vco_max = 1400000000, 298 .base_reg = PLLC_BASE, 299 .misc_reg = PLLC_MISC, 300 .lock_mask = PLL_BASE_LOCK, 301 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 302 .lock_delay = 300, 303 .freq_table = pll_c_freq_table, 304 .flags = TEGRA_PLL_HAS_CPCON, 305 }; 306 307 static struct tegra_clk_pll_params pll_m_params = { 308 .input_min = 2000000, 309 .input_max = 31000000, 310 .cf_min = 1000000, 311 .cf_max = 6000000, 312 .vco_min = 20000000, 313 .vco_max = 1200000000, 314 .base_reg = PLLM_BASE, 315 .misc_reg = PLLM_MISC, 316 .lock_mask = PLL_BASE_LOCK, 317 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 318 .lock_delay = 300, 319 .freq_table = pll_m_freq_table, 320 .flags = TEGRA_PLL_HAS_CPCON, 321 }; 322 323 static struct tegra_clk_pll_params pll_p_params = { 324 .input_min = 2000000, 325 .input_max = 31000000, 326 .cf_min = 1000000, 327 .cf_max = 6000000, 328 .vco_min = 20000000, 329 .vco_max = 1400000000, 330 .base_reg = PLLP_BASE, 331 .misc_reg = PLLP_MISC, 332 .lock_mask = PLL_BASE_LOCK, 333 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 334 .lock_delay = 300, 335 .freq_table = pll_p_freq_table, 336 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON, 337 .fixed_rate = 216000000, 338 }; 339 340 static struct tegra_clk_pll_params pll_a_params = { 341 .input_min = 2000000, 342 .input_max = 31000000, 343 .cf_min = 1000000, 344 .cf_max = 6000000, 345 .vco_min = 20000000, 346 .vco_max = 1400000000, 347 .base_reg = PLLA_BASE, 348 .misc_reg = PLLA_MISC, 349 .lock_mask = PLL_BASE_LOCK, 350 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 351 .lock_delay = 300, 352 .freq_table = pll_a_freq_table, 353 .flags = TEGRA_PLL_HAS_CPCON, 354 }; 355 356 static struct tegra_clk_pll_params pll_d_params = { 357 .input_min = 2000000, 358 .input_max = 40000000, 359 .cf_min = 1000000, 360 .cf_max = 6000000, 361 .vco_min = 40000000, 362 .vco_max = 1000000000, 363 .base_reg = PLLD_BASE, 364 .misc_reg = PLLD_MISC, 365 .lock_mask = PLL_BASE_LOCK, 366 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 367 .lock_delay = 1000, 368 .freq_table = pll_d_freq_table, 369 .flags = TEGRA_PLL_HAS_CPCON, 370 }; 371 372 static struct pdiv_map pllu_p[] = { 373 { .pdiv = 1, .hw_val = 1 }, 374 { .pdiv = 2, .hw_val = 0 }, 375 { .pdiv = 0, .hw_val = 0 }, 376 }; 377 378 static struct tegra_clk_pll_params pll_u_params = { 379 .input_min = 2000000, 380 .input_max = 40000000, 381 .cf_min = 1000000, 382 .cf_max = 6000000, 383 .vco_min = 48000000, 384 .vco_max = 960000000, 385 .base_reg = PLLU_BASE, 386 .misc_reg = PLLU_MISC, 387 .lock_mask = PLL_BASE_LOCK, 388 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 389 .lock_delay = 1000, 390 .pdiv_tohw = pllu_p, 391 .freq_table = pll_u_freq_table, 392 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, 393 }; 394 395 static struct tegra_clk_pll_params pll_x_params = { 396 .input_min = 2000000, 397 .input_max = 31000000, 398 .cf_min = 1000000, 399 .cf_max = 6000000, 400 .vco_min = 20000000, 401 .vco_max = 1200000000, 402 .base_reg = PLLX_BASE, 403 .misc_reg = PLLX_MISC, 404 .lock_mask = PLL_BASE_LOCK, 405 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 406 .lock_delay = 300, 407 .freq_table = pll_x_freq_table, 408 .flags = TEGRA_PLL_HAS_CPCON, 409 }; 410 411 static struct tegra_clk_pll_params pll_e_params = { 412 .input_min = 12000000, 413 .input_max = 12000000, 414 .cf_min = 0, 415 .cf_max = 0, 416 .vco_min = 0, 417 .vco_max = 0, 418 .base_reg = PLLE_BASE, 419 .misc_reg = PLLE_MISC, 420 .lock_mask = PLLE_MISC_LOCK, 421 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 422 .lock_delay = 0, 423 .freq_table = pll_e_freq_table, 424 .flags = TEGRA_PLL_FIXED, 425 .fixed_rate = 100000000, 426 }; 427 428 static struct tegra_devclk devclks[] __initdata = { 429 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C }, 430 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 }, 431 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P }, 432 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 }, 433 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 }, 434 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 }, 435 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 }, 436 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M }, 437 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 }, 438 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X }, 439 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U }, 440 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D }, 441 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 }, 442 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A }, 443 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 }, 444 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E }, 445 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK }, 446 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK }, 447 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK }, 448 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK }, 449 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE }, 450 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD }, 451 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO }, 452 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X }, 453 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 }, 454 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA }, 455 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC }, 456 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER }, 457 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC }, 458 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS }, 459 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP }, 460 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA }, 461 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV }, 462 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC }, 463 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD }, 464 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 }, 465 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 }, 466 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI }, 467 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI }, 468 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP }, 469 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX }, 470 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI }, 471 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 }, 472 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 }, 473 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K }, 474 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK }, 475 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M }, 476 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF }, 477 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 }, 478 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 }, 479 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT }, 480 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN }, 481 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 }, 482 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 }, 483 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 }, 484 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 }, 485 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI }, 486 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO }, 487 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC }, 488 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE }, 489 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH }, 490 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR }, 491 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE }, 492 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA }, 493 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR }, 494 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI }, 495 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE }, 496 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI }, 497 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP }, 498 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE }, 499 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X }, 500 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D }, 501 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D }, 502 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR }, 503 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 }, 504 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 }, 505 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 }, 506 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 }, 507 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE }, 508 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO }, 509 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC }, 510 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR }, 511 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI }, 512 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 }, 513 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 }, 514 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 }, 515 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC }, 516 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM }, 517 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA }, 518 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB }, 519 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC }, 520 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD }, 521 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE }, 522 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 }, 523 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 }, 524 }; 525 526 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { 527 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, 528 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, 529 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, 530 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true }, 531 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true }, 532 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true }, 533 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true }, 534 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true }, 535 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true }, 536 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true }, 537 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true }, 538 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true }, 539 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true }, 540 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true }, 541 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true }, 542 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true }, 543 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true }, 544 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true }, 545 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true }, 546 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true }, 547 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true }, 548 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true }, 549 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true }, 550 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true }, 551 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true }, 552 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true }, 553 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true }, 554 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true }, 555 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true }, 556 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true }, 557 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true }, 558 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true }, 559 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true }, 560 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true }, 561 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true }, 562 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true }, 563 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true }, 564 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true }, 565 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true }, 566 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true }, 567 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true }, 568 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true }, 569 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true }, 570 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true }, 571 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true }, 572 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true }, 573 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true }, 574 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true }, 575 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true }, 576 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, 577 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, 578 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, 579 }; 580 581 static unsigned long tegra20_clk_measure_input_freq(void) 582 { 583 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 584 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 585 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 586 unsigned long input_freq; 587 588 switch (auto_clk_control) { 589 case OSC_CTRL_OSC_FREQ_12MHZ: 590 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 591 input_freq = 12000000; 592 break; 593 case OSC_CTRL_OSC_FREQ_13MHZ: 594 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 595 input_freq = 13000000; 596 break; 597 case OSC_CTRL_OSC_FREQ_19_2MHZ: 598 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 599 input_freq = 19200000; 600 break; 601 case OSC_CTRL_OSC_FREQ_26MHZ: 602 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 603 input_freq = 26000000; 604 break; 605 default: 606 pr_err("Unexpected clock autodetect value %d", 607 auto_clk_control); 608 BUG(); 609 return 0; 610 } 611 612 return input_freq; 613 } 614 615 static unsigned int tegra20_get_pll_ref_div(void) 616 { 617 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 618 OSC_CTRL_PLL_REF_DIV_MASK; 619 620 switch (pll_ref_div) { 621 case OSC_CTRL_PLL_REF_DIV_1: 622 return 1; 623 case OSC_CTRL_PLL_REF_DIV_2: 624 return 2; 625 case OSC_CTRL_PLL_REF_DIV_4: 626 return 4; 627 default: 628 pr_err("Invalied pll ref divider %d\n", pll_ref_div); 629 BUG(); 630 } 631 return 0; 632 } 633 634 static void tegra20_pll_init(void) 635 { 636 struct clk *clk; 637 638 /* PLLC */ 639 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 640 &pll_c_params, NULL); 641 clks[TEGRA20_CLK_PLL_C] = clk; 642 643 /* PLLC_OUT1 */ 644 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 645 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 646 8, 8, 1, NULL); 647 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 648 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 649 0, NULL); 650 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; 651 652 /* PLLM */ 653 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 654 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 655 &pll_m_params, NULL); 656 clks[TEGRA20_CLK_PLL_M] = clk; 657 658 /* PLLM_OUT1 */ 659 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 660 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 661 8, 8, 1, NULL); 662 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 663 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 664 CLK_SET_RATE_PARENT, 0, NULL); 665 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; 666 667 /* PLLX */ 668 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 669 &pll_x_params, NULL); 670 clks[TEGRA20_CLK_PLL_X] = clk; 671 672 /* PLLU */ 673 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 674 &pll_u_params, NULL); 675 clks[TEGRA20_CLK_PLL_U] = clk; 676 677 /* PLLD */ 678 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 679 &pll_d_params, NULL); 680 clks[TEGRA20_CLK_PLL_D] = clk; 681 682 /* PLLD_OUT0 */ 683 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 684 CLK_SET_RATE_PARENT, 1, 2); 685 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; 686 687 /* PLLA */ 688 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 689 &pll_a_params, NULL); 690 clks[TEGRA20_CLK_PLL_A] = clk; 691 692 /* PLLA_OUT0 */ 693 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 694 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 695 8, 8, 1, NULL); 696 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 697 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 698 CLK_SET_RATE_PARENT, 0, NULL); 699 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; 700 701 /* PLLE */ 702 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 703 0, &pll_e_params, NULL); 704 clks[TEGRA20_CLK_PLL_E] = clk; 705 } 706 707 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 708 "pll_p", "pll_p_out4", 709 "pll_p_out3", "clk_d", "pll_x" }; 710 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 711 "pll_p_out3", "pll_p_out2", "clk_d", 712 "clk_32k", "pll_m_out1" }; 713 714 static void tegra20_super_clk_init(void) 715 { 716 struct clk *clk; 717 718 /* CCLK */ 719 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 720 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 721 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 722 clks[TEGRA20_CLK_CCLK] = clk; 723 724 /* SCLK */ 725 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 726 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, 727 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 728 clks[TEGRA20_CLK_SCLK] = clk; 729 730 /* twd */ 731 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 732 clks[TEGRA20_CLK_TWD] = clk; 733 } 734 735 static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 736 "pll_a_out0", "unused", "unused", 737 "unused"}; 738 739 static void __init tegra20_audio_clk_init(void) 740 { 741 struct clk *clk; 742 743 /* audio */ 744 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 745 ARRAY_SIZE(audio_parents), 746 CLK_SET_RATE_NO_REPARENT, 747 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 748 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 749 clk_base + AUDIO_SYNC_CLK, 4, 750 CLK_GATE_SET_TO_DISABLE, NULL); 751 clks[TEGRA20_CLK_AUDIO] = clk; 752 753 /* audio_2x */ 754 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 755 CLK_SET_RATE_PARENT, 2, 1); 756 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 757 TEGRA_PERIPH_NO_RESET, clk_base, 758 CLK_SET_RATE_PARENT, 89, 759 periph_clk_enb_refcnt); 760 clks[TEGRA20_CLK_AUDIO_2X] = clk; 761 762 } 763 764 static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 765 "clk_m"}; 766 static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 767 "clk_m"}; 768 static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 769 "clk_32k"}; 770 static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 771 static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 772 "clk_m"}; 773 static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 774 775 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 776 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1), 777 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2), 778 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI), 779 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO), 780 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC), 781 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE), 782 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC), 783 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1), 784 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2), 785 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3), 786 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI), 787 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM), 788 }; 789 790 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 791 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA), 792 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB), 793 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC), 794 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD), 795 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE), 796 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1), 797 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), 798 }; 799 800 static void __init tegra20_periph_clk_init(void) 801 { 802 struct tegra_periph_init_data *data; 803 struct clk *clk; 804 int i; 805 806 /* ac97 */ 807 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 808 TEGRA_PERIPH_ON_APB, 809 clk_base, 0, 3, periph_clk_enb_refcnt); 810 clks[TEGRA20_CLK_AC97] = clk; 811 812 /* apbdma */ 813 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 814 0, 34, periph_clk_enb_refcnt); 815 clks[TEGRA20_CLK_APBDMA] = clk; 816 817 /* emc */ 818 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 819 ARRAY_SIZE(mux_pllmcp_clkm), 820 CLK_SET_RATE_NO_REPARENT, 821 clk_base + CLK_SOURCE_EMC, 822 30, 2, 0, NULL); 823 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 824 57, periph_clk_enb_refcnt); 825 clks[TEGRA20_CLK_EMC] = clk; 826 827 /* dsi */ 828 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 829 48, periph_clk_enb_refcnt); 830 clk_register_clkdev(clk, NULL, "dsi"); 831 clks[TEGRA20_CLK_DSI] = clk; 832 833 /* pex */ 834 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 835 periph_clk_enb_refcnt); 836 clks[TEGRA20_CLK_PEX] = clk; 837 838 /* cdev1 */ 839 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 840 26000000); 841 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 842 clk_base, 0, 94, periph_clk_enb_refcnt); 843 clks[TEGRA20_CLK_CDEV1] = clk; 844 845 /* cdev2 */ 846 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 847 26000000); 848 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 849 clk_base, 0, 93, periph_clk_enb_refcnt); 850 clks[TEGRA20_CLK_CDEV2] = clk; 851 852 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 853 data = &tegra_periph_clk_list[i]; 854 clk = tegra_clk_register_periph(data->name, data->p.parent_names, 855 data->num_parents, &data->periph, 856 clk_base, data->offset, data->flags); 857 clks[data->clk_id] = clk; 858 } 859 860 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 861 data = &tegra_periph_nodiv_clk_list[i]; 862 clk = tegra_clk_register_periph_nodiv(data->name, 863 data->p.parent_names, 864 data->num_parents, &data->periph, 865 clk_base, data->offset); 866 clks[data->clk_id] = clk; 867 } 868 869 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); 870 } 871 872 static void __init tegra20_osc_clk_init(void) 873 { 874 struct clk *clk; 875 unsigned long input_freq; 876 unsigned int pll_ref_div; 877 878 input_freq = tegra20_clk_measure_input_freq(); 879 880 /* clk_m */ 881 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | 882 CLK_IGNORE_UNUSED, input_freq); 883 clks[TEGRA20_CLK_CLK_M] = clk; 884 885 /* pll_ref */ 886 pll_ref_div = tegra20_get_pll_ref_div(); 887 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 888 CLK_SET_RATE_PARENT, 1, pll_ref_div); 889 clks[TEGRA20_CLK_PLL_REF] = clk; 890 } 891 892 /* Tegra20 CPU clock and reset control functions */ 893 static void tegra20_wait_cpu_in_reset(u32 cpu) 894 { 895 unsigned int reg; 896 897 do { 898 reg = readl(clk_base + 899 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 900 cpu_relax(); 901 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 902 903 return; 904 } 905 906 static void tegra20_put_cpu_in_reset(u32 cpu) 907 { 908 writel(CPU_RESET(cpu), 909 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 910 dmb(); 911 } 912 913 static void tegra20_cpu_out_of_reset(u32 cpu) 914 { 915 writel(CPU_RESET(cpu), 916 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 917 wmb(); 918 } 919 920 static void tegra20_enable_cpu_clock(u32 cpu) 921 { 922 unsigned int reg; 923 924 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 925 writel(reg & ~CPU_CLOCK(cpu), 926 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 927 barrier(); 928 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 929 } 930 931 static void tegra20_disable_cpu_clock(u32 cpu) 932 { 933 unsigned int reg; 934 935 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 936 writel(reg | CPU_CLOCK(cpu), 937 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 938 } 939 940 #ifdef CONFIG_PM_SLEEP 941 static bool tegra20_cpu_rail_off_ready(void) 942 { 943 unsigned int cpu_rst_status; 944 945 cpu_rst_status = readl(clk_base + 946 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 947 948 return !!(cpu_rst_status & 0x2); 949 } 950 951 static void tegra20_cpu_clock_suspend(void) 952 { 953 /* switch coresite to clk_m, save off original source */ 954 tegra20_cpu_clk_sctx.clk_csite_src = 955 readl(clk_base + CLK_SOURCE_CSITE); 956 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 957 958 tegra20_cpu_clk_sctx.cpu_burst = 959 readl(clk_base + CCLK_BURST_POLICY); 960 tegra20_cpu_clk_sctx.pllx_base = 961 readl(clk_base + PLLX_BASE); 962 tegra20_cpu_clk_sctx.pllx_misc = 963 readl(clk_base + PLLX_MISC); 964 tegra20_cpu_clk_sctx.cclk_divider = 965 readl(clk_base + SUPER_CCLK_DIVIDER); 966 } 967 968 static void tegra20_cpu_clock_resume(void) 969 { 970 unsigned int reg, policy; 971 972 /* Is CPU complex already running on PLLX? */ 973 reg = readl(clk_base + CCLK_BURST_POLICY); 974 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 975 976 if (policy == CCLK_IDLE_POLICY) 977 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 978 else if (policy == CCLK_RUN_POLICY) 979 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 980 else 981 BUG(); 982 983 if (reg != CCLK_BURST_POLICY_PLLX) { 984 /* restore PLLX settings if CPU is on different PLL */ 985 writel(tegra20_cpu_clk_sctx.pllx_misc, 986 clk_base + PLLX_MISC); 987 writel(tegra20_cpu_clk_sctx.pllx_base, 988 clk_base + PLLX_BASE); 989 990 /* wait for PLL stabilization if PLLX was enabled */ 991 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 992 udelay(300); 993 } 994 995 /* 996 * Restore original burst policy setting for calls resulting from CPU 997 * LP2 in idle or system suspend. 998 */ 999 writel(tegra20_cpu_clk_sctx.cclk_divider, 1000 clk_base + SUPER_CCLK_DIVIDER); 1001 writel(tegra20_cpu_clk_sctx.cpu_burst, 1002 clk_base + CCLK_BURST_POLICY); 1003 1004 writel(tegra20_cpu_clk_sctx.clk_csite_src, 1005 clk_base + CLK_SOURCE_CSITE); 1006 } 1007 #endif 1008 1009 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1010 .wait_for_reset = tegra20_wait_cpu_in_reset, 1011 .put_in_reset = tegra20_put_cpu_in_reset, 1012 .out_of_reset = tegra20_cpu_out_of_reset, 1013 .enable_clock = tegra20_enable_cpu_clock, 1014 .disable_clock = tegra20_disable_cpu_clock, 1015 #ifdef CONFIG_PM_SLEEP 1016 .rail_off_ready = tegra20_cpu_rail_off_ready, 1017 .suspend = tegra20_cpu_clock_suspend, 1018 .resume = tegra20_cpu_clock_resume, 1019 #endif 1020 }; 1021 1022 static struct tegra_clk_init_table init_table[] __initdata = { 1023 {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1}, 1024 {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1}, 1025 {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1}, 1026 {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1}, 1027 {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1}, 1028 {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1}, 1029 {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1}, 1030 {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1}, 1031 {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, 1032 {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1}, 1033 {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1}, 1034 {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1}, 1035 {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, 1036 {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0}, 1037 {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0}, 1038 {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0}, 1039 {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0}, 1040 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0}, 1041 {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1}, 1042 {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1}, 1043 {TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1}, 1044 {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1}, 1045 {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, 1046 {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, 1047 {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0}, 1048 {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0}, 1049 {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0}, 1050 {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0}, 1051 {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0}, 1052 {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0}, 1053 {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0}, 1054 {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0}, 1055 {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0}, 1056 {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0}, 1057 {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0}, 1058 {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0}, 1059 {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0}, 1060 {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ 1061 }; 1062 1063 static void __init tegra20_clock_apply_init_table(void) 1064 { 1065 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); 1066 } 1067 1068 /* 1069 * Some clocks may be used by different drivers depending on the board 1070 * configuration. List those here to register them twice in the clock lookup 1071 * table under two names. 1072 */ 1073 static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1074 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL), 1075 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL), 1076 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL), 1077 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"), 1078 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */ 1079 }; 1080 1081 static const struct of_device_id pmc_match[] __initconst = { 1082 { .compatible = "nvidia,tegra20-pmc" }, 1083 {}, 1084 }; 1085 1086 static void __init tegra20_clock_init(struct device_node *np) 1087 { 1088 struct device_node *node; 1089 1090 clk_base = of_iomap(np, 0); 1091 if (!clk_base) { 1092 pr_err("Can't map CAR registers\n"); 1093 BUG(); 1094 } 1095 1096 node = of_find_matching_node(NULL, pmc_match); 1097 if (!node) { 1098 pr_err("Failed to find pmc node\n"); 1099 BUG(); 1100 } 1101 1102 pmc_base = of_iomap(node, 0); 1103 if (!pmc_base) { 1104 pr_err("Can't map pmc registers\n"); 1105 BUG(); 1106 } 1107 1108 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, 1109 TEGRA20_CLK_PERIPH_BANKS); 1110 if (!clks) 1111 return; 1112 1113 tegra20_osc_clk_init(); 1114 tegra_fixed_clk_init(tegra20_clks); 1115 tegra20_pll_init(); 1116 tegra20_super_clk_init(); 1117 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); 1118 tegra20_periph_clk_init(); 1119 tegra20_audio_clk_init(); 1120 tegra_pmc_clk_init(pmc_base, tegra20_clks); 1121 1122 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); 1123 1124 tegra_add_of_provider(np); 1125 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1126 1127 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1128 1129 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1130 } 1131 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init); 1132