1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/init.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/clk/tegra.h> 15 #include <linux/delay.h> 16 #include <dt-bindings/clock/tegra20-car.h> 17 18 #include "clk.h" 19 #include "clk-id.h" 20 21 #define MISC_CLK_ENB 0x48 22 23 #define OSC_CTRL 0x50 24 #define OSC_CTRL_OSC_FREQ_MASK (3u<<30) 25 #define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30) 26 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30) 27 #define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30) 28 #define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30) 29 #define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK) 30 31 #define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28) 32 #define OSC_CTRL_PLL_REF_DIV_1 (0u<<28) 33 #define OSC_CTRL_PLL_REF_DIV_2 (1u<<28) 34 #define OSC_CTRL_PLL_REF_DIV_4 (2u<<28) 35 36 #define OSC_FREQ_DET 0x58 37 #define OSC_FREQ_DET_TRIG (1u<<31) 38 39 #define OSC_FREQ_DET_STATUS 0x5c 40 #define OSC_FREQ_DET_BUSYu (1<<31) 41 #define OSC_FREQ_DET_CNT_MASK 0xFFFFu 42 43 #define TEGRA20_CLK_PERIPH_BANKS 3 44 45 #define PLLS_BASE 0xf0 46 #define PLLS_MISC 0xf4 47 #define PLLC_BASE 0x80 48 #define PLLC_MISC 0x8c 49 #define PLLM_BASE 0x90 50 #define PLLM_MISC 0x9c 51 #define PLLP_BASE 0xa0 52 #define PLLP_MISC 0xac 53 #define PLLA_BASE 0xb0 54 #define PLLA_MISC 0xbc 55 #define PLLU_BASE 0xc0 56 #define PLLU_MISC 0xcc 57 #define PLLD_BASE 0xd0 58 #define PLLD_MISC 0xdc 59 #define PLLX_BASE 0xe0 60 #define PLLX_MISC 0xe4 61 #define PLLE_BASE 0xe8 62 #define PLLE_MISC 0xec 63 64 #define PLL_BASE_LOCK BIT(27) 65 #define PLLE_MISC_LOCK BIT(11) 66 67 #define PLL_MISC_LOCK_ENABLE 18 68 #define PLLDU_MISC_LOCK_ENABLE 22 69 #define PLLE_MISC_LOCK_ENABLE 9 70 71 #define PLLC_OUT 0x84 72 #define PLLM_OUT 0x94 73 #define PLLP_OUTA 0xa4 74 #define PLLP_OUTB 0xa8 75 #define PLLA_OUT 0xb4 76 77 #define CCLK_BURST_POLICY 0x20 78 #define SUPER_CCLK_DIVIDER 0x24 79 #define SCLK_BURST_POLICY 0x28 80 #define SUPER_SCLK_DIVIDER 0x2c 81 #define CLK_SYSTEM_RATE 0x30 82 83 #define CCLK_BURST_POLICY_SHIFT 28 84 #define CCLK_RUN_POLICY_SHIFT 4 85 #define CCLK_IDLE_POLICY_SHIFT 0 86 #define CCLK_IDLE_POLICY 1 87 #define CCLK_RUN_POLICY 2 88 #define CCLK_BURST_POLICY_PLLX 8 89 90 #define CLK_SOURCE_I2S1 0x100 91 #define CLK_SOURCE_I2S2 0x104 92 #define CLK_SOURCE_PWM 0x110 93 #define CLK_SOURCE_SPI 0x114 94 #define CLK_SOURCE_XIO 0x120 95 #define CLK_SOURCE_TWC 0x12c 96 #define CLK_SOURCE_IDE 0x144 97 #define CLK_SOURCE_HDMI 0x18c 98 #define CLK_SOURCE_DISP1 0x138 99 #define CLK_SOURCE_DISP2 0x13c 100 #define CLK_SOURCE_CSITE 0x1d4 101 #define CLK_SOURCE_I2C1 0x124 102 #define CLK_SOURCE_I2C2 0x198 103 #define CLK_SOURCE_I2C3 0x1b8 104 #define CLK_SOURCE_DVC 0x128 105 #define CLK_SOURCE_UARTA 0x178 106 #define CLK_SOURCE_UARTB 0x17c 107 #define CLK_SOURCE_UARTC 0x1a0 108 #define CLK_SOURCE_UARTD 0x1c0 109 #define CLK_SOURCE_UARTE 0x1c4 110 #define CLK_SOURCE_EMC 0x19c 111 112 #define AUDIO_SYNC_CLK 0x38 113 114 /* Tegra CPU clock and reset control regs */ 115 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 116 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 117 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 118 119 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 120 #define CPU_RESET(cpu) (0x1111ul << (cpu)) 121 122 #ifdef CONFIG_PM_SLEEP 123 static struct cpu_clk_suspend_context { 124 u32 pllx_misc; 125 u32 pllx_base; 126 127 u32 cpu_burst; 128 u32 clk_csite_src; 129 u32 cclk_divider; 130 } tegra20_cpu_clk_sctx; 131 #endif 132 133 static void __iomem *clk_base; 134 static void __iomem *pmc_base; 135 136 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 137 _clk_num, _gate_flags, _clk_id) \ 138 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 139 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 140 _clk_num, \ 141 _gate_flags, _clk_id) 142 143 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ 144 _clk_num, _gate_flags, _clk_id) \ 145 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 146 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 147 _clk_num, _gate_flags, \ 148 _clk_id) 149 150 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 151 _mux_shift, _mux_width, _clk_num, \ 152 _gate_flags, _clk_id) \ 153 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 154 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ 155 _clk_num, _gate_flags, \ 156 _clk_id) 157 158 static struct clk **clks; 159 160 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 161 { 12000000, 600000000, 600, 12, 1, 8 }, 162 { 13000000, 600000000, 600, 13, 1, 8 }, 163 { 19200000, 600000000, 500, 16, 1, 6 }, 164 { 26000000, 600000000, 600, 26, 1, 8 }, 165 { 0, 0, 0, 0, 0, 0 }, 166 }; 167 168 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 169 { 12000000, 666000000, 666, 12, 1, 8 }, 170 { 13000000, 666000000, 666, 13, 1, 8 }, 171 { 19200000, 666000000, 555, 16, 1, 8 }, 172 { 26000000, 666000000, 666, 26, 1, 8 }, 173 { 12000000, 600000000, 600, 12, 1, 8 }, 174 { 13000000, 600000000, 600, 13, 1, 8 }, 175 { 19200000, 600000000, 375, 12, 1, 6 }, 176 { 26000000, 600000000, 600, 26, 1, 8 }, 177 { 0, 0, 0, 0, 0, 0 }, 178 }; 179 180 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 181 { 12000000, 216000000, 432, 12, 2, 8 }, 182 { 13000000, 216000000, 432, 13, 2, 8 }, 183 { 19200000, 216000000, 90, 4, 2, 1 }, 184 { 26000000, 216000000, 432, 26, 2, 8 }, 185 { 12000000, 432000000, 432, 12, 1, 8 }, 186 { 13000000, 432000000, 432, 13, 1, 8 }, 187 { 19200000, 432000000, 90, 4, 1, 1 }, 188 { 26000000, 432000000, 432, 26, 1, 8 }, 189 { 0, 0, 0, 0, 0, 0 }, 190 }; 191 192 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 193 { 28800000, 56448000, 49, 25, 1, 1 }, 194 { 28800000, 73728000, 64, 25, 1, 1 }, 195 { 28800000, 24000000, 5, 6, 1, 1 }, 196 { 0, 0, 0, 0, 0, 0 }, 197 }; 198 199 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 200 { 12000000, 216000000, 216, 12, 1, 4 }, 201 { 13000000, 216000000, 216, 13, 1, 4 }, 202 { 19200000, 216000000, 135, 12, 1, 3 }, 203 { 26000000, 216000000, 216, 26, 1, 4 }, 204 { 12000000, 594000000, 594, 12, 1, 8 }, 205 { 13000000, 594000000, 594, 13, 1, 8 }, 206 { 19200000, 594000000, 495, 16, 1, 8 }, 207 { 26000000, 594000000, 594, 26, 1, 8 }, 208 { 12000000, 1000000000, 1000, 12, 1, 12 }, 209 { 13000000, 1000000000, 1000, 13, 1, 12 }, 210 { 19200000, 1000000000, 625, 12, 1, 8 }, 211 { 26000000, 1000000000, 1000, 26, 1, 12 }, 212 { 0, 0, 0, 0, 0, 0 }, 213 }; 214 215 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 216 { 12000000, 480000000, 960, 12, 1, 0 }, 217 { 13000000, 480000000, 960, 13, 1, 0 }, 218 { 19200000, 480000000, 200, 4, 1, 0 }, 219 { 26000000, 480000000, 960, 26, 1, 0 }, 220 { 0, 0, 0, 0, 0, 0 }, 221 }; 222 223 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 224 /* 1 GHz */ 225 { 12000000, 1000000000, 1000, 12, 1, 12 }, 226 { 13000000, 1000000000, 1000, 13, 1, 12 }, 227 { 19200000, 1000000000, 625, 12, 1, 8 }, 228 { 26000000, 1000000000, 1000, 26, 1, 12 }, 229 /* 912 MHz */ 230 { 12000000, 912000000, 912, 12, 1, 12 }, 231 { 13000000, 912000000, 912, 13, 1, 12 }, 232 { 19200000, 912000000, 760, 16, 1, 8 }, 233 { 26000000, 912000000, 912, 26, 1, 12 }, 234 /* 816 MHz */ 235 { 12000000, 816000000, 816, 12, 1, 12 }, 236 { 13000000, 816000000, 816, 13, 1, 12 }, 237 { 19200000, 816000000, 680, 16, 1, 8 }, 238 { 26000000, 816000000, 816, 26, 1, 12 }, 239 /* 760 MHz */ 240 { 12000000, 760000000, 760, 12, 1, 12 }, 241 { 13000000, 760000000, 760, 13, 1, 12 }, 242 { 19200000, 760000000, 950, 24, 1, 8 }, 243 { 26000000, 760000000, 760, 26, 1, 12 }, 244 /* 750 MHz */ 245 { 12000000, 750000000, 750, 12, 1, 12 }, 246 { 13000000, 750000000, 750, 13, 1, 12 }, 247 { 19200000, 750000000, 625, 16, 1, 8 }, 248 { 26000000, 750000000, 750, 26, 1, 12 }, 249 /* 608 MHz */ 250 { 12000000, 608000000, 608, 12, 1, 12 }, 251 { 13000000, 608000000, 608, 13, 1, 12 }, 252 { 19200000, 608000000, 380, 12, 1, 8 }, 253 { 26000000, 608000000, 608, 26, 1, 12 }, 254 /* 456 MHz */ 255 { 12000000, 456000000, 456, 12, 1, 12 }, 256 { 13000000, 456000000, 456, 13, 1, 12 }, 257 { 19200000, 456000000, 380, 16, 1, 8 }, 258 { 26000000, 456000000, 456, 26, 1, 12 }, 259 /* 312 MHz */ 260 { 12000000, 312000000, 312, 12, 1, 12 }, 261 { 13000000, 312000000, 312, 13, 1, 12 }, 262 { 19200000, 312000000, 260, 16, 1, 8 }, 263 { 26000000, 312000000, 312, 26, 1, 12 }, 264 { 0, 0, 0, 0, 0, 0 }, 265 }; 266 267 static const struct pdiv_map plle_p[] = { 268 { .pdiv = 1, .hw_val = 1 }, 269 { .pdiv = 0, .hw_val = 0 }, 270 }; 271 272 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 273 { 12000000, 100000000, 200, 24, 1, 0 }, 274 { 0, 0, 0, 0, 0, 0 }, 275 }; 276 277 /* PLL parameters */ 278 static struct tegra_clk_pll_params pll_c_params = { 279 .input_min = 2000000, 280 .input_max = 31000000, 281 .cf_min = 1000000, 282 .cf_max = 6000000, 283 .vco_min = 20000000, 284 .vco_max = 1400000000, 285 .base_reg = PLLC_BASE, 286 .misc_reg = PLLC_MISC, 287 .lock_mask = PLL_BASE_LOCK, 288 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 289 .lock_delay = 300, 290 .freq_table = pll_c_freq_table, 291 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 292 }; 293 294 static struct tegra_clk_pll_params pll_m_params = { 295 .input_min = 2000000, 296 .input_max = 31000000, 297 .cf_min = 1000000, 298 .cf_max = 6000000, 299 .vco_min = 20000000, 300 .vco_max = 1200000000, 301 .base_reg = PLLM_BASE, 302 .misc_reg = PLLM_MISC, 303 .lock_mask = PLL_BASE_LOCK, 304 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 305 .lock_delay = 300, 306 .freq_table = pll_m_freq_table, 307 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 308 }; 309 310 static struct tegra_clk_pll_params pll_p_params = { 311 .input_min = 2000000, 312 .input_max = 31000000, 313 .cf_min = 1000000, 314 .cf_max = 6000000, 315 .vco_min = 20000000, 316 .vco_max = 1400000000, 317 .base_reg = PLLP_BASE, 318 .misc_reg = PLLP_MISC, 319 .lock_mask = PLL_BASE_LOCK, 320 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 321 .lock_delay = 300, 322 .freq_table = pll_p_freq_table, 323 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 324 TEGRA_PLL_HAS_LOCK_ENABLE, 325 .fixed_rate = 216000000, 326 }; 327 328 static struct tegra_clk_pll_params pll_a_params = { 329 .input_min = 2000000, 330 .input_max = 31000000, 331 .cf_min = 1000000, 332 .cf_max = 6000000, 333 .vco_min = 20000000, 334 .vco_max = 1400000000, 335 .base_reg = PLLA_BASE, 336 .misc_reg = PLLA_MISC, 337 .lock_mask = PLL_BASE_LOCK, 338 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 339 .lock_delay = 300, 340 .freq_table = pll_a_freq_table, 341 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 342 }; 343 344 static struct tegra_clk_pll_params pll_d_params = { 345 .input_min = 2000000, 346 .input_max = 40000000, 347 .cf_min = 1000000, 348 .cf_max = 6000000, 349 .vco_min = 40000000, 350 .vco_max = 1000000000, 351 .base_reg = PLLD_BASE, 352 .misc_reg = PLLD_MISC, 353 .lock_mask = PLL_BASE_LOCK, 354 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 355 .lock_delay = 1000, 356 .freq_table = pll_d_freq_table, 357 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 358 }; 359 360 static const struct pdiv_map pllu_p[] = { 361 { .pdiv = 1, .hw_val = 1 }, 362 { .pdiv = 2, .hw_val = 0 }, 363 { .pdiv = 0, .hw_val = 0 }, 364 }; 365 366 static struct tegra_clk_pll_params pll_u_params = { 367 .input_min = 2000000, 368 .input_max = 40000000, 369 .cf_min = 1000000, 370 .cf_max = 6000000, 371 .vco_min = 48000000, 372 .vco_max = 960000000, 373 .base_reg = PLLU_BASE, 374 .misc_reg = PLLU_MISC, 375 .lock_mask = PLL_BASE_LOCK, 376 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 377 .lock_delay = 1000, 378 .pdiv_tohw = pllu_p, 379 .freq_table = pll_u_freq_table, 380 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 381 }; 382 383 static struct tegra_clk_pll_params pll_x_params = { 384 .input_min = 2000000, 385 .input_max = 31000000, 386 .cf_min = 1000000, 387 .cf_max = 6000000, 388 .vco_min = 20000000, 389 .vco_max = 1200000000, 390 .base_reg = PLLX_BASE, 391 .misc_reg = PLLX_MISC, 392 .lock_mask = PLL_BASE_LOCK, 393 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 394 .lock_delay = 300, 395 .freq_table = pll_x_freq_table, 396 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 397 .pre_rate_change = tegra_cclk_pre_pllx_rate_change, 398 .post_rate_change = tegra_cclk_post_pllx_rate_change, 399 }; 400 401 static struct tegra_clk_pll_params pll_e_params = { 402 .input_min = 12000000, 403 .input_max = 12000000, 404 .cf_min = 0, 405 .cf_max = 0, 406 .vco_min = 0, 407 .vco_max = 0, 408 .base_reg = PLLE_BASE, 409 .misc_reg = PLLE_MISC, 410 .lock_mask = PLLE_MISC_LOCK, 411 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 412 .lock_delay = 0, 413 .pdiv_tohw = plle_p, 414 .freq_table = pll_e_freq_table, 415 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | 416 TEGRA_PLL_HAS_LOCK_ENABLE, 417 .fixed_rate = 100000000, 418 }; 419 420 static struct tegra_devclk devclks[] = { 421 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C }, 422 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 }, 423 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P }, 424 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 }, 425 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 }, 426 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 }, 427 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 }, 428 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M }, 429 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 }, 430 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X }, 431 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U }, 432 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D }, 433 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 }, 434 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A }, 435 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 }, 436 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E }, 437 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK }, 438 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK }, 439 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK }, 440 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK }, 441 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE }, 442 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD }, 443 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO }, 444 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X }, 445 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 }, 446 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA }, 447 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC }, 448 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER }, 449 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC }, 450 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS }, 451 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP }, 452 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA }, 453 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV }, 454 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC }, 455 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD }, 456 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 }, 457 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 }, 458 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI }, 459 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI }, 460 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP }, 461 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX }, 462 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI }, 463 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 }, 464 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 }, 465 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K }, 466 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M }, 467 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF }, 468 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 }, 469 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 }, 470 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT }, 471 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN }, 472 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 }, 473 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 }, 474 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 }, 475 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 }, 476 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI }, 477 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO }, 478 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC }, 479 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE }, 480 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH }, 481 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR }, 482 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE }, 483 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA }, 484 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR }, 485 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI }, 486 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE }, 487 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI }, 488 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP }, 489 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE }, 490 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X }, 491 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D }, 492 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D }, 493 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR }, 494 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 }, 495 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 }, 496 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 }, 497 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 }, 498 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE }, 499 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO }, 500 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC }, 501 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR }, 502 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI }, 503 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 }, 504 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 }, 505 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 }, 506 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC }, 507 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM }, 508 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA }, 509 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB }, 510 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC }, 511 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD }, 512 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE }, 513 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 }, 514 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 }, 515 }; 516 517 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { 518 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true }, 519 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true }, 520 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, 521 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, 522 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, 523 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true }, 524 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true }, 525 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true }, 526 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true }, 527 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true }, 528 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true }, 529 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true }, 530 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true }, 531 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true }, 532 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true }, 533 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true }, 534 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true }, 535 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true }, 536 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true }, 537 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true }, 538 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true }, 539 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true }, 540 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true }, 541 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true }, 542 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true }, 543 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true }, 544 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true }, 545 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true }, 546 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true }, 547 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true }, 548 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true }, 549 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true }, 550 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true }, 551 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true }, 552 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true }, 553 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true }, 554 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true }, 555 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true }, 556 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true }, 557 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true }, 558 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true }, 559 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true }, 560 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true }, 561 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true }, 562 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true }, 563 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true }, 564 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true }, 565 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true }, 566 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true }, 567 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true }, 568 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, 569 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, 570 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, 571 }; 572 573 static unsigned long tegra20_clk_measure_input_freq(void) 574 { 575 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 576 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 577 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 578 unsigned long input_freq; 579 580 switch (auto_clk_control) { 581 case OSC_CTRL_OSC_FREQ_12MHZ: 582 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 583 input_freq = 12000000; 584 break; 585 case OSC_CTRL_OSC_FREQ_13MHZ: 586 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 587 input_freq = 13000000; 588 break; 589 case OSC_CTRL_OSC_FREQ_19_2MHZ: 590 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 591 input_freq = 19200000; 592 break; 593 case OSC_CTRL_OSC_FREQ_26MHZ: 594 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 595 input_freq = 26000000; 596 break; 597 default: 598 pr_err("Unexpected clock autodetect value %d", 599 auto_clk_control); 600 BUG(); 601 return 0; 602 } 603 604 return input_freq; 605 } 606 607 static unsigned int tegra20_get_pll_ref_div(void) 608 { 609 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 610 OSC_CTRL_PLL_REF_DIV_MASK; 611 612 switch (pll_ref_div) { 613 case OSC_CTRL_PLL_REF_DIV_1: 614 return 1; 615 case OSC_CTRL_PLL_REF_DIV_2: 616 return 2; 617 case OSC_CTRL_PLL_REF_DIV_4: 618 return 4; 619 default: 620 pr_err("Invalid pll ref divider %d\n", pll_ref_div); 621 BUG(); 622 } 623 return 0; 624 } 625 626 static void tegra20_pll_init(void) 627 { 628 struct clk *clk; 629 630 /* PLLC */ 631 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 632 &pll_c_params, NULL); 633 clks[TEGRA20_CLK_PLL_C] = clk; 634 635 /* PLLC_OUT1 */ 636 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 637 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 638 8, 8, 1, NULL); 639 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 640 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 641 0, NULL); 642 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; 643 644 /* PLLM */ 645 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 646 CLK_SET_RATE_GATE, &pll_m_params, NULL); 647 clks[TEGRA20_CLK_PLL_M] = clk; 648 649 /* PLLM_OUT1 */ 650 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 651 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 652 8, 8, 1, NULL); 653 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 654 clk_base + PLLM_OUT, 1, 0, 655 CLK_SET_RATE_PARENT, 0, NULL); 656 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; 657 658 /* PLLX */ 659 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 660 &pll_x_params, NULL); 661 clks[TEGRA20_CLK_PLL_X] = clk; 662 663 /* PLLU */ 664 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 665 &pll_u_params, NULL); 666 clks[TEGRA20_CLK_PLL_U] = clk; 667 668 /* PLLD */ 669 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 670 &pll_d_params, NULL); 671 clks[TEGRA20_CLK_PLL_D] = clk; 672 673 /* PLLD_OUT0 */ 674 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 675 CLK_SET_RATE_PARENT, 1, 2); 676 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; 677 678 /* PLLA */ 679 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 680 &pll_a_params, NULL); 681 clks[TEGRA20_CLK_PLL_A] = clk; 682 683 /* PLLA_OUT0 */ 684 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 685 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 686 8, 8, 1, NULL); 687 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 688 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 689 CLK_SET_RATE_PARENT, 0, NULL); 690 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; 691 692 /* PLLE */ 693 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 694 0, &pll_e_params, NULL); 695 clks[TEGRA20_CLK_PLL_E] = clk; 696 } 697 698 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 699 "pll_p", "pll_p_out4", 700 "pll_p_out3", "clk_d", "pll_x" }; 701 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 702 "pll_p_out3", "pll_p_out2", "clk_d", 703 "clk_32k", "pll_m_out1" }; 704 705 static void tegra20_super_clk_init(void) 706 { 707 struct clk *clk; 708 709 /* CCLK */ 710 clk = tegra_clk_register_super_cclk("cclk", cclk_parents, 711 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 712 clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, 713 NULL); 714 clks[TEGRA20_CLK_CCLK] = clk; 715 716 /* twd */ 717 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 718 clks[TEGRA20_CLK_TWD] = clk; 719 } 720 721 static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused", 722 "pll_a_out0", "unused", "unused", 723 "unused" }; 724 725 static void __init tegra20_audio_clk_init(void) 726 { 727 struct clk *clk; 728 729 /* audio */ 730 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 731 ARRAY_SIZE(audio_parents), 732 CLK_SET_RATE_NO_REPARENT, 733 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 734 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 735 clk_base + AUDIO_SYNC_CLK, 4, 736 CLK_GATE_SET_TO_DISABLE, NULL); 737 clks[TEGRA20_CLK_AUDIO] = clk; 738 739 /* audio_2x */ 740 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 741 CLK_SET_RATE_PARENT, 2, 1); 742 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 743 TEGRA_PERIPH_NO_RESET, clk_base, 744 CLK_SET_RATE_PARENT, 89, 745 periph_clk_enb_refcnt); 746 clks[TEGRA20_CLK_AUDIO_2X] = clk; 747 } 748 749 static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 750 "clk_m" }; 751 static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 752 "clk_m" }; 753 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m", 754 "clk_32k" }; 755 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 756 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 757 "clk_m" }; 758 759 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 760 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1), 761 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2), 762 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI), 763 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO), 764 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC), 765 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE), 766 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC), 767 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1), 768 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2), 769 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3), 770 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI), 771 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM), 772 }; 773 774 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 775 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA), 776 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB), 777 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC), 778 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD), 779 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE), 780 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1), 781 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), 782 }; 783 784 static void __init tegra20_periph_clk_init(void) 785 { 786 struct tegra_periph_init_data *data; 787 struct clk *clk; 788 unsigned int i; 789 790 /* ac97 */ 791 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 792 TEGRA_PERIPH_ON_APB, 793 clk_base, 0, 3, periph_clk_enb_refcnt); 794 clks[TEGRA20_CLK_AC97] = clk; 795 796 /* emc */ 797 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false); 798 799 clks[TEGRA20_CLK_EMC] = clk; 800 801 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, 802 NULL); 803 clks[TEGRA20_CLK_MC] = clk; 804 805 /* dsi */ 806 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 807 48, periph_clk_enb_refcnt); 808 clk_register_clkdev(clk, NULL, "dsi"); 809 clks[TEGRA20_CLK_DSI] = clk; 810 811 /* pex */ 812 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 813 periph_clk_enb_refcnt); 814 clks[TEGRA20_CLK_PEX] = clk; 815 816 /* dev1 OSC divider */ 817 clk_register_divider(NULL, "dev1_osc_div", "clk_m", 818 0, clk_base + MISC_CLK_ENB, 22, 2, 819 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 820 NULL); 821 822 /* dev2 OSC divider */ 823 clk_register_divider(NULL, "dev2_osc_div", "clk_m", 824 0, clk_base + MISC_CLK_ENB, 20, 2, 825 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 826 NULL); 827 828 /* cdev1 */ 829 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, 830 clk_base, 0, 94, periph_clk_enb_refcnt); 831 clks[TEGRA20_CLK_CDEV1] = clk; 832 833 /* cdev2 */ 834 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, 835 clk_base, 0, 93, periph_clk_enb_refcnt); 836 clks[TEGRA20_CLK_CDEV2] = clk; 837 838 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 839 data = &tegra_periph_clk_list[i]; 840 clk = tegra_clk_register_periph_data(clk_base, data); 841 clks[data->clk_id] = clk; 842 } 843 844 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 845 data = &tegra_periph_nodiv_clk_list[i]; 846 clk = tegra_clk_register_periph_nodiv(data->name, 847 data->p.parent_names, 848 data->num_parents, &data->periph, 849 clk_base, data->offset); 850 clks[data->clk_id] = clk; 851 } 852 853 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); 854 } 855 856 static void __init tegra20_osc_clk_init(void) 857 { 858 struct clk *clk; 859 unsigned long input_freq; 860 unsigned int pll_ref_div; 861 862 input_freq = tegra20_clk_measure_input_freq(); 863 864 /* clk_m */ 865 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED, 866 input_freq); 867 clks[TEGRA20_CLK_CLK_M] = clk; 868 869 /* pll_ref */ 870 pll_ref_div = tegra20_get_pll_ref_div(); 871 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 872 CLK_SET_RATE_PARENT, 1, pll_ref_div); 873 clks[TEGRA20_CLK_PLL_REF] = clk; 874 } 875 876 /* Tegra20 CPU clock and reset control functions */ 877 static void tegra20_wait_cpu_in_reset(u32 cpu) 878 { 879 unsigned int reg; 880 881 do { 882 reg = readl(clk_base + 883 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 884 cpu_relax(); 885 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 886 887 return; 888 } 889 890 static void tegra20_put_cpu_in_reset(u32 cpu) 891 { 892 writel(CPU_RESET(cpu), 893 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 894 dmb(); 895 } 896 897 static void tegra20_cpu_out_of_reset(u32 cpu) 898 { 899 writel(CPU_RESET(cpu), 900 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 901 wmb(); 902 } 903 904 static void tegra20_enable_cpu_clock(u32 cpu) 905 { 906 unsigned int reg; 907 908 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 909 writel(reg & ~CPU_CLOCK(cpu), 910 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 911 barrier(); 912 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 913 } 914 915 static void tegra20_disable_cpu_clock(u32 cpu) 916 { 917 unsigned int reg; 918 919 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 920 writel(reg | CPU_CLOCK(cpu), 921 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 922 } 923 924 #ifdef CONFIG_PM_SLEEP 925 static bool tegra20_cpu_rail_off_ready(void) 926 { 927 unsigned int cpu_rst_status; 928 929 cpu_rst_status = readl(clk_base + 930 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 931 932 return !!(cpu_rst_status & 0x2); 933 } 934 935 static void tegra20_cpu_clock_suspend(void) 936 { 937 /* switch coresite to clk_m, save off original source */ 938 tegra20_cpu_clk_sctx.clk_csite_src = 939 readl(clk_base + CLK_SOURCE_CSITE); 940 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 941 942 tegra20_cpu_clk_sctx.cpu_burst = 943 readl(clk_base + CCLK_BURST_POLICY); 944 tegra20_cpu_clk_sctx.pllx_base = 945 readl(clk_base + PLLX_BASE); 946 tegra20_cpu_clk_sctx.pllx_misc = 947 readl(clk_base + PLLX_MISC); 948 tegra20_cpu_clk_sctx.cclk_divider = 949 readl(clk_base + SUPER_CCLK_DIVIDER); 950 } 951 952 static void tegra20_cpu_clock_resume(void) 953 { 954 unsigned int reg, policy; 955 u32 misc, base; 956 957 /* Is CPU complex already running on PLLX? */ 958 reg = readl(clk_base + CCLK_BURST_POLICY); 959 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 960 961 if (policy == CCLK_IDLE_POLICY) 962 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 963 else if (policy == CCLK_RUN_POLICY) 964 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 965 else 966 BUG(); 967 968 if (reg != CCLK_BURST_POLICY_PLLX) { 969 misc = readl_relaxed(clk_base + PLLX_MISC); 970 base = readl_relaxed(clk_base + PLLX_BASE); 971 972 if (misc != tegra20_cpu_clk_sctx.pllx_misc || 973 base != tegra20_cpu_clk_sctx.pllx_base) { 974 /* restore PLLX settings if CPU is on different PLL */ 975 writel(tegra20_cpu_clk_sctx.pllx_misc, 976 clk_base + PLLX_MISC); 977 writel(tegra20_cpu_clk_sctx.pllx_base, 978 clk_base + PLLX_BASE); 979 980 /* wait for PLL stabilization if PLLX was enabled */ 981 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 982 udelay(300); 983 } 984 } 985 986 /* 987 * Restore original burst policy setting for calls resulting from CPU 988 * LP2 in idle or system suspend. 989 */ 990 writel(tegra20_cpu_clk_sctx.cclk_divider, 991 clk_base + SUPER_CCLK_DIVIDER); 992 writel(tegra20_cpu_clk_sctx.cpu_burst, 993 clk_base + CCLK_BURST_POLICY); 994 995 writel(tegra20_cpu_clk_sctx.clk_csite_src, 996 clk_base + CLK_SOURCE_CSITE); 997 } 998 #endif 999 1000 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1001 .wait_for_reset = tegra20_wait_cpu_in_reset, 1002 .put_in_reset = tegra20_put_cpu_in_reset, 1003 .out_of_reset = tegra20_cpu_out_of_reset, 1004 .enable_clock = tegra20_enable_cpu_clock, 1005 .disable_clock = tegra20_disable_cpu_clock, 1006 #ifdef CONFIG_PM_SLEEP 1007 .rail_off_ready = tegra20_cpu_rail_off_ready, 1008 .suspend = tegra20_cpu_clock_suspend, 1009 .resume = tegra20_cpu_clock_resume, 1010 #endif 1011 }; 1012 1013 static struct tegra_clk_init_table init_table[] = { 1014 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 }, 1015 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 }, 1016 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 }, 1017 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, 1018 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, 1019 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, 1020 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, 1021 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 }, 1022 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, 1023 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, 1024 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1025 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1026 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 }, 1027 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 }, 1028 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 }, 1029 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 }, 1030 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 }, 1031 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 }, 1032 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 }, 1033 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1034 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1035 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1036 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1037 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1038 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, 1039 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1040 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1041 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1042 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1043 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, 1044 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1045 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1046 { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1047 { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1048 /* must be the last entry */ 1049 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, 1050 }; 1051 1052 /* 1053 * Some clocks may be used by different drivers depending on the board 1054 * configuration. List those here to register them twice in the clock lookup 1055 * table under two names. 1056 */ 1057 static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1058 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL), 1059 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL), 1060 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL), 1061 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"), 1062 /* must be the last entry */ 1063 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), 1064 }; 1065 1066 static const struct of_device_id pmc_match[] __initconst = { 1067 { .compatible = "nvidia,tegra20-pmc" }, 1068 { }, 1069 }; 1070 1071 static bool tegra20_car_initialized; 1072 1073 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, 1074 void *data) 1075 { 1076 struct clk_hw *parent_hw; 1077 struct clk_hw *hw; 1078 struct clk *clk; 1079 1080 /* 1081 * Timer clocks are needed early, the rest of the clocks shouldn't be 1082 * available to device drivers until clock tree is fully initialized. 1083 */ 1084 if (clkspec->args[0] != TEGRA20_CLK_RTC && 1085 clkspec->args[0] != TEGRA20_CLK_TWD && 1086 clkspec->args[0] != TEGRA20_CLK_TIMER && 1087 !tegra20_car_initialized) 1088 return ERR_PTR(-EPROBE_DEFER); 1089 1090 clk = of_clk_src_onecell_get(clkspec, data); 1091 if (IS_ERR(clk)) 1092 return clk; 1093 1094 hw = __clk_get_hw(clk); 1095 1096 /* 1097 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent 1098 * clock is created by the pinctrl driver. It is possible for clk user 1099 * to request these clocks before pinctrl driver got probed and hence 1100 * user will get an orphaned clock. That might be undesirable because 1101 * user may expect parent clock to be enabled by the child. 1102 */ 1103 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || 1104 clkspec->args[0] == TEGRA20_CLK_CDEV2) { 1105 parent_hw = clk_hw_get_parent(hw); 1106 if (!parent_hw) 1107 return ERR_PTR(-EPROBE_DEFER); 1108 } 1109 1110 if (clkspec->args[0] == TEGRA20_CLK_EMC) { 1111 if (!tegra20_clk_emc_driver_available(hw)) 1112 return ERR_PTR(-EPROBE_DEFER); 1113 } 1114 1115 return clk; 1116 } 1117 1118 static void __init tegra20_clock_init(struct device_node *np) 1119 { 1120 struct device_node *node; 1121 1122 clk_base = of_iomap(np, 0); 1123 if (!clk_base) { 1124 pr_err("Can't map CAR registers\n"); 1125 BUG(); 1126 } 1127 1128 node = of_find_matching_node(NULL, pmc_match); 1129 if (!node) { 1130 pr_err("Failed to find pmc node\n"); 1131 BUG(); 1132 } 1133 1134 pmc_base = of_iomap(node, 0); 1135 of_node_put(node); 1136 if (!pmc_base) { 1137 pr_err("Can't map pmc registers\n"); 1138 BUG(); 1139 } 1140 1141 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, 1142 TEGRA20_CLK_PERIPH_BANKS); 1143 if (!clks) 1144 return; 1145 1146 tegra20_osc_clk_init(); 1147 tegra_fixed_clk_init(tegra20_clks); 1148 tegra20_pll_init(); 1149 tegra20_super_clk_init(); 1150 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); 1151 tegra20_periph_clk_init(); 1152 tegra20_audio_clk_init(); 1153 1154 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); 1155 1156 tegra_add_of_provider(np, tegra20_clk_src_onecell_get); 1157 1158 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1159 } 1160 CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init); 1161 1162 /* 1163 * Clocks that use runtime PM can't be created at the tegra20_clock_init 1164 * time because drivers' base isn't initialized yet, and thus platform 1165 * devices can't be created for the clocks. Hence we need to split the 1166 * registration of the clocks into two phases. The first phase registers 1167 * essential clocks which don't require RPM and are actually used during 1168 * early boot. The second phase registers clocks which use RPM and this 1169 * is done when device drivers' core API is ready. 1170 */ 1171 static int tegra20_car_probe(struct platform_device *pdev) 1172 { 1173 struct clk *clk; 1174 1175 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1176 ARRAY_SIZE(sclk_parents), 1177 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1178 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 1179 clks[TEGRA20_CLK_SCLK] = clk; 1180 1181 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1182 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); 1183 tegra20_car_initialized = true; 1184 1185 return 0; 1186 } 1187 1188 static const struct of_device_id tegra20_car_match[] = { 1189 { .compatible = "nvidia,tegra20-car" }, 1190 { } 1191 }; 1192 1193 static struct platform_driver tegra20_car_driver = { 1194 .driver = { 1195 .name = "tegra20-car", 1196 .of_match_table = tegra20_car_match, 1197 .suppress_bind_attrs = true, 1198 }, 1199 .probe = tegra20_car_probe, 1200 }; 1201 builtin_platform_driver(tegra20_car_driver); 1202