1 /* 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk-provider.h> 19 #include <linux/clkdev.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/clk/tegra.h> 25 #include <dt-bindings/clock/tegra124-car.h> 26 #include <dt-bindings/reset/tegra124-car.h> 27 28 #include "clk.h" 29 #include "clk-id.h" 30 31 /* 32 * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register 33 * banks present in the Tegra124/132 CAR IP block. The banks are 34 * identified by single letters, e.g.: L, H, U, V, W, X. See 35 * periph_regs[] in drivers/clk/tegra/clk.c 36 */ 37 #define TEGRA124_CAR_BANK_COUNT 6 38 39 #define CLK_SOURCE_CSITE 0x1d4 40 #define CLK_SOURCE_EMC 0x19c 41 42 #define RST_DFLL_DVCO 0x2f4 43 #define DVFS_DFLL_RESET_SHIFT 0 44 45 #define PLLC_BASE 0x80 46 #define PLLC_OUT 0x84 47 #define PLLC_MISC2 0x88 48 #define PLLC_MISC 0x8c 49 #define PLLC2_BASE 0x4e8 50 #define PLLC2_MISC 0x4ec 51 #define PLLC3_BASE 0x4fc 52 #define PLLC3_MISC 0x500 53 #define PLLM_BASE 0x90 54 #define PLLM_OUT 0x94 55 #define PLLM_MISC 0x9c 56 #define PLLP_BASE 0xa0 57 #define PLLP_MISC 0xac 58 #define PLLA_BASE 0xb0 59 #define PLLA_MISC 0xbc 60 #define PLLD_BASE 0xd0 61 #define PLLD_MISC 0xdc 62 #define PLLU_BASE 0xc0 63 #define PLLU_MISC 0xcc 64 #define PLLX_BASE 0xe0 65 #define PLLX_MISC 0xe4 66 #define PLLX_MISC2 0x514 67 #define PLLX_MISC3 0x518 68 #define PLLE_BASE 0xe8 69 #define PLLE_MISC 0xec 70 #define PLLD2_BASE 0x4b8 71 #define PLLD2_MISC 0x4bc 72 #define PLLE_AUX 0x48c 73 #define PLLRE_BASE 0x4c4 74 #define PLLRE_MISC 0x4c8 75 #define PLLDP_BASE 0x590 76 #define PLLDP_MISC 0x594 77 #define PLLC4_BASE 0x5a4 78 #define PLLC4_MISC 0x5a8 79 80 #define PLLC_IDDQ_BIT 26 81 #define PLLRE_IDDQ_BIT 16 82 #define PLLSS_IDDQ_BIT 19 83 84 #define PLL_BASE_LOCK BIT(27) 85 #define PLLE_MISC_LOCK BIT(11) 86 #define PLLRE_MISC_LOCK BIT(24) 87 88 #define PLL_MISC_LOCK_ENABLE 18 89 #define PLLC_MISC_LOCK_ENABLE 24 90 #define PLLDU_MISC_LOCK_ENABLE 22 91 #define PLLE_MISC_LOCK_ENABLE 9 92 #define PLLRE_MISC_LOCK_ENABLE 30 93 #define PLLSS_MISC_LOCK_ENABLE 30 94 95 #define PLLXC_SW_MAX_P 6 96 97 #define PMC_PLLM_WB0_OVERRIDE 0x1dc 98 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 99 100 #define CCLKG_BURST_POLICY 0x368 101 102 /* Tegra CPU clock and reset control regs */ 103 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 104 105 #ifdef CONFIG_PM_SLEEP 106 static struct cpu_clk_suspend_context { 107 u32 clk_csite_src; 108 u32 cclkg_burst; 109 u32 cclkg_divider; 110 } tegra124_cpu_clk_sctx; 111 #endif 112 113 static void __iomem *clk_base; 114 static void __iomem *pmc_base; 115 116 static unsigned long osc_freq; 117 static unsigned long pll_ref_freq; 118 119 static DEFINE_SPINLOCK(pll_d_lock); 120 static DEFINE_SPINLOCK(pll_e_lock); 121 static DEFINE_SPINLOCK(pll_re_lock); 122 static DEFINE_SPINLOCK(pll_u_lock); 123 static DEFINE_SPINLOCK(emc_lock); 124 125 /* possible OSC frequencies in Hz */ 126 static unsigned long tegra124_input_freq[] = { 127 [ 0] = 13000000, 128 [ 1] = 16800000, 129 [ 4] = 19200000, 130 [ 5] = 38400000, 131 [ 8] = 12000000, 132 [ 9] = 48000000, 133 [12] = 26000000, 134 }; 135 136 static struct div_nmp pllxc_nmp = { 137 .divm_shift = 0, 138 .divm_width = 8, 139 .divn_shift = 8, 140 .divn_width = 8, 141 .divp_shift = 20, 142 .divp_width = 4, 143 }; 144 145 static const struct pdiv_map pllxc_p[] = { 146 { .pdiv = 1, .hw_val = 0 }, 147 { .pdiv = 2, .hw_val = 1 }, 148 { .pdiv = 3, .hw_val = 2 }, 149 { .pdiv = 4, .hw_val = 3 }, 150 { .pdiv = 5, .hw_val = 4 }, 151 { .pdiv = 6, .hw_val = 5 }, 152 { .pdiv = 8, .hw_val = 6 }, 153 { .pdiv = 10, .hw_val = 7 }, 154 { .pdiv = 12, .hw_val = 8 }, 155 { .pdiv = 16, .hw_val = 9 }, 156 { .pdiv = 12, .hw_val = 10 }, 157 { .pdiv = 16, .hw_val = 11 }, 158 { .pdiv = 20, .hw_val = 12 }, 159 { .pdiv = 24, .hw_val = 13 }, 160 { .pdiv = 32, .hw_val = 14 }, 161 { .pdiv = 0, .hw_val = 0 }, 162 }; 163 164 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 165 /* 1 GHz */ 166 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */ 167 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */ 168 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */ 169 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */ 170 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */ 171 { 0, 0, 0, 0, 0, 0 }, 172 }; 173 174 static struct tegra_clk_pll_params pll_x_params = { 175 .input_min = 12000000, 176 .input_max = 800000000, 177 .cf_min = 12000000, 178 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 179 .vco_min = 700000000, 180 .vco_max = 3000000000UL, 181 .base_reg = PLLX_BASE, 182 .misc_reg = PLLX_MISC, 183 .lock_mask = PLL_BASE_LOCK, 184 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 185 .lock_delay = 300, 186 .iddq_reg = PLLX_MISC3, 187 .iddq_bit_idx = 3, 188 .max_p = 6, 189 .dyn_ramp_reg = PLLX_MISC2, 190 .stepa_shift = 16, 191 .stepb_shift = 24, 192 .pdiv_tohw = pllxc_p, 193 .div_nmp = &pllxc_nmp, 194 .freq_table = pll_x_freq_table, 195 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 196 }; 197 198 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 199 { 12000000, 624000000, 104, 1, 2, 0 }, 200 { 12000000, 600000000, 100, 1, 2, 0 }, 201 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 202 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 203 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 204 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 205 { 0, 0, 0, 0, 0, 0 }, 206 }; 207 208 static struct tegra_clk_pll_params pll_c_params = { 209 .input_min = 12000000, 210 .input_max = 800000000, 211 .cf_min = 12000000, 212 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 213 .vco_min = 600000000, 214 .vco_max = 1400000000, 215 .base_reg = PLLC_BASE, 216 .misc_reg = PLLC_MISC, 217 .lock_mask = PLL_BASE_LOCK, 218 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 219 .lock_delay = 300, 220 .iddq_reg = PLLC_MISC, 221 .iddq_bit_idx = PLLC_IDDQ_BIT, 222 .max_p = PLLXC_SW_MAX_P, 223 .dyn_ramp_reg = PLLC_MISC2, 224 .stepa_shift = 17, 225 .stepb_shift = 9, 226 .pdiv_tohw = pllxc_p, 227 .div_nmp = &pllxc_nmp, 228 .freq_table = pll_c_freq_table, 229 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 230 }; 231 232 static struct div_nmp pllcx_nmp = { 233 .divm_shift = 0, 234 .divm_width = 2, 235 .divn_shift = 8, 236 .divn_width = 8, 237 .divp_shift = 20, 238 .divp_width = 3, 239 }; 240 241 static const struct pdiv_map pllc_p[] = { 242 { .pdiv = 1, .hw_val = 0 }, 243 { .pdiv = 2, .hw_val = 1 }, 244 { .pdiv = 3, .hw_val = 2 }, 245 { .pdiv = 4, .hw_val = 3 }, 246 { .pdiv = 6, .hw_val = 4 }, 247 { .pdiv = 8, .hw_val = 5 }, 248 { .pdiv = 12, .hw_val = 6 }, 249 { .pdiv = 16, .hw_val = 7 }, 250 { .pdiv = 0, .hw_val = 0 }, 251 }; 252 253 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 254 { 12000000, 600000000, 100, 1, 2, 0 }, 255 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 256 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 257 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 258 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 259 { 0, 0, 0, 0, 0, 0 }, 260 }; 261 262 static struct tegra_clk_pll_params pll_c2_params = { 263 .input_min = 12000000, 264 .input_max = 48000000, 265 .cf_min = 12000000, 266 .cf_max = 19200000, 267 .vco_min = 600000000, 268 .vco_max = 1200000000, 269 .base_reg = PLLC2_BASE, 270 .misc_reg = PLLC2_MISC, 271 .lock_mask = PLL_BASE_LOCK, 272 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 273 .lock_delay = 300, 274 .pdiv_tohw = pllc_p, 275 .div_nmp = &pllcx_nmp, 276 .max_p = 7, 277 .ext_misc_reg[0] = 0x4f0, 278 .ext_misc_reg[1] = 0x4f4, 279 .ext_misc_reg[2] = 0x4f8, 280 .freq_table = pll_cx_freq_table, 281 .flags = TEGRA_PLL_USE_LOCK, 282 }; 283 284 static struct tegra_clk_pll_params pll_c3_params = { 285 .input_min = 12000000, 286 .input_max = 48000000, 287 .cf_min = 12000000, 288 .cf_max = 19200000, 289 .vco_min = 600000000, 290 .vco_max = 1200000000, 291 .base_reg = PLLC3_BASE, 292 .misc_reg = PLLC3_MISC, 293 .lock_mask = PLL_BASE_LOCK, 294 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 295 .lock_delay = 300, 296 .pdiv_tohw = pllc_p, 297 .div_nmp = &pllcx_nmp, 298 .max_p = 7, 299 .ext_misc_reg[0] = 0x504, 300 .ext_misc_reg[1] = 0x508, 301 .ext_misc_reg[2] = 0x50c, 302 .freq_table = pll_cx_freq_table, 303 .flags = TEGRA_PLL_USE_LOCK, 304 }; 305 306 static struct div_nmp pllss_nmp = { 307 .divm_shift = 0, 308 .divm_width = 8, 309 .divn_shift = 8, 310 .divn_width = 8, 311 .divp_shift = 20, 312 .divp_width = 4, 313 }; 314 315 static const struct pdiv_map pll12g_ssd_esd_p[] = { 316 { .pdiv = 1, .hw_val = 0 }, 317 { .pdiv = 2, .hw_val = 1 }, 318 { .pdiv = 3, .hw_val = 2 }, 319 { .pdiv = 4, .hw_val = 3 }, 320 { .pdiv = 5, .hw_val = 4 }, 321 { .pdiv = 6, .hw_val = 5 }, 322 { .pdiv = 8, .hw_val = 6 }, 323 { .pdiv = 10, .hw_val = 7 }, 324 { .pdiv = 12, .hw_val = 8 }, 325 { .pdiv = 16, .hw_val = 9 }, 326 { .pdiv = 12, .hw_val = 10 }, 327 { .pdiv = 16, .hw_val = 11 }, 328 { .pdiv = 20, .hw_val = 12 }, 329 { .pdiv = 24, .hw_val = 13 }, 330 { .pdiv = 32, .hw_val = 14 }, 331 { .pdiv = 0, .hw_val = 0 }, 332 }; 333 334 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = { 335 { 12000000, 600000000, 100, 1, 2, 0 }, 336 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 337 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 338 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 339 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 340 { 0, 0, 0, 0, 0, 0 }, 341 }; 342 343 static struct tegra_clk_pll_params pll_c4_params = { 344 .input_min = 12000000, 345 .input_max = 1000000000, 346 .cf_min = 12000000, 347 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 348 .vco_min = 600000000, 349 .vco_max = 1200000000, 350 .base_reg = PLLC4_BASE, 351 .misc_reg = PLLC4_MISC, 352 .lock_mask = PLL_BASE_LOCK, 353 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 354 .lock_delay = 300, 355 .iddq_reg = PLLC4_BASE, 356 .iddq_bit_idx = PLLSS_IDDQ_BIT, 357 .pdiv_tohw = pll12g_ssd_esd_p, 358 .div_nmp = &pllss_nmp, 359 .ext_misc_reg[0] = 0x5ac, 360 .ext_misc_reg[1] = 0x5b0, 361 .ext_misc_reg[2] = 0x5b4, 362 .freq_table = pll_c4_freq_table, 363 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 364 }; 365 366 static const struct pdiv_map pllm_p[] = { 367 { .pdiv = 1, .hw_val = 0 }, 368 { .pdiv = 2, .hw_val = 1 }, 369 { .pdiv = 3, .hw_val = 2 }, 370 { .pdiv = 4, .hw_val = 3 }, 371 { .pdiv = 5, .hw_val = 4 }, 372 { .pdiv = 6, .hw_val = 5 }, 373 { .pdiv = 8, .hw_val = 6 }, 374 { .pdiv = 10, .hw_val = 7 }, 375 { .pdiv = 12, .hw_val = 8 }, 376 { .pdiv = 16, .hw_val = 9 }, 377 { .pdiv = 12, .hw_val = 10 }, 378 { .pdiv = 16, .hw_val = 11 }, 379 { .pdiv = 20, .hw_val = 12 }, 380 { .pdiv = 24, .hw_val = 13 }, 381 { .pdiv = 32, .hw_val = 14 }, 382 { .pdiv = 0, .hw_val = 0 }, 383 }; 384 385 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 386 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ 387 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ 388 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */ 389 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */ 390 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */ 391 { 0, 0, 0, 0, 0, 0}, 392 }; 393 394 static struct div_nmp pllm_nmp = { 395 .divm_shift = 0, 396 .divm_width = 8, 397 .override_divm_shift = 0, 398 .divn_shift = 8, 399 .divn_width = 8, 400 .override_divn_shift = 8, 401 .divp_shift = 20, 402 .divp_width = 1, 403 .override_divp_shift = 27, 404 }; 405 406 static struct tegra_clk_pll_params pll_m_params = { 407 .input_min = 12000000, 408 .input_max = 500000000, 409 .cf_min = 12000000, 410 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 411 .vco_min = 400000000, 412 .vco_max = 1066000000, 413 .base_reg = PLLM_BASE, 414 .misc_reg = PLLM_MISC, 415 .lock_mask = PLL_BASE_LOCK, 416 .lock_delay = 300, 417 .max_p = 5, 418 .pdiv_tohw = pllm_p, 419 .div_nmp = &pllm_nmp, 420 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 421 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 422 .freq_table = pll_m_freq_table, 423 .flags = TEGRA_PLL_USE_LOCK, 424 }; 425 426 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 427 /* PLLE special case: use cpcon field to store cml divider value */ 428 { 336000000, 100000000, 100, 21, 16, 11 }, 429 { 312000000, 100000000, 200, 26, 24, 13 }, 430 { 13000000, 100000000, 200, 1, 26, 13 }, 431 { 12000000, 100000000, 200, 1, 24, 13 }, 432 { 0, 0, 0, 0, 0, 0 }, 433 }; 434 435 static const struct pdiv_map plle_p[] = { 436 { .pdiv = 1, .hw_val = 0 }, 437 { .pdiv = 2, .hw_val = 1 }, 438 { .pdiv = 3, .hw_val = 2 }, 439 { .pdiv = 4, .hw_val = 3 }, 440 { .pdiv = 5, .hw_val = 4 }, 441 { .pdiv = 6, .hw_val = 5 }, 442 { .pdiv = 8, .hw_val = 6 }, 443 { .pdiv = 10, .hw_val = 7 }, 444 { .pdiv = 12, .hw_val = 8 }, 445 { .pdiv = 16, .hw_val = 9 }, 446 { .pdiv = 12, .hw_val = 10 }, 447 { .pdiv = 16, .hw_val = 11 }, 448 { .pdiv = 20, .hw_val = 12 }, 449 { .pdiv = 24, .hw_val = 13 }, 450 { .pdiv = 32, .hw_val = 14 }, 451 { .pdiv = 1, .hw_val = 0 }, 452 }; 453 454 static struct div_nmp plle_nmp = { 455 .divm_shift = 0, 456 .divm_width = 8, 457 .divn_shift = 8, 458 .divn_width = 8, 459 .divp_shift = 24, 460 .divp_width = 4, 461 }; 462 463 static struct tegra_clk_pll_params pll_e_params = { 464 .input_min = 12000000, 465 .input_max = 1000000000, 466 .cf_min = 12000000, 467 .cf_max = 75000000, 468 .vco_min = 1600000000, 469 .vco_max = 2400000000U, 470 .base_reg = PLLE_BASE, 471 .misc_reg = PLLE_MISC, 472 .aux_reg = PLLE_AUX, 473 .lock_mask = PLLE_MISC_LOCK, 474 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 475 .lock_delay = 300, 476 .pdiv_tohw = plle_p, 477 .div_nmp = &plle_nmp, 478 .freq_table = pll_e_freq_table, 479 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE, 480 .fixed_rate = 100000000, 481 }; 482 483 static const struct clk_div_table pll_re_div_table[] = { 484 { .val = 0, .div = 1 }, 485 { .val = 1, .div = 2 }, 486 { .val = 2, .div = 3 }, 487 { .val = 3, .div = 4 }, 488 { .val = 4, .div = 5 }, 489 { .val = 5, .div = 6 }, 490 { .val = 0, .div = 0 }, 491 }; 492 493 static struct div_nmp pllre_nmp = { 494 .divm_shift = 0, 495 .divm_width = 8, 496 .divn_shift = 8, 497 .divn_width = 8, 498 .divp_shift = 16, 499 .divp_width = 4, 500 }; 501 502 static struct tegra_clk_pll_params pll_re_vco_params = { 503 .input_min = 12000000, 504 .input_max = 1000000000, 505 .cf_min = 12000000, 506 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 507 .vco_min = 300000000, 508 .vco_max = 600000000, 509 .base_reg = PLLRE_BASE, 510 .misc_reg = PLLRE_MISC, 511 .lock_mask = PLLRE_MISC_LOCK, 512 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 513 .lock_delay = 300, 514 .iddq_reg = PLLRE_MISC, 515 .iddq_bit_idx = PLLRE_IDDQ_BIT, 516 .div_nmp = &pllre_nmp, 517 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | 518 TEGRA_PLL_LOCK_MISC, 519 }; 520 521 static struct div_nmp pllp_nmp = { 522 .divm_shift = 0, 523 .divm_width = 5, 524 .divn_shift = 8, 525 .divn_width = 10, 526 .divp_shift = 20, 527 .divp_width = 3, 528 }; 529 530 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 531 { 12000000, 408000000, 408, 12, 1, 8 }, 532 { 13000000, 408000000, 408, 13, 1, 8 }, 533 { 16800000, 408000000, 340, 14, 1, 8 }, 534 { 19200000, 408000000, 340, 16, 1, 8 }, 535 { 26000000, 408000000, 408, 26, 1, 8 }, 536 { 0, 0, 0, 0, 0, 0 }, 537 }; 538 539 static struct tegra_clk_pll_params pll_p_params = { 540 .input_min = 2000000, 541 .input_max = 31000000, 542 .cf_min = 1000000, 543 .cf_max = 6000000, 544 .vco_min = 200000000, 545 .vco_max = 700000000, 546 .base_reg = PLLP_BASE, 547 .misc_reg = PLLP_MISC, 548 .lock_mask = PLL_BASE_LOCK, 549 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 550 .lock_delay = 300, 551 .div_nmp = &pllp_nmp, 552 .freq_table = pll_p_freq_table, 553 .fixed_rate = 408000000, 554 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | 555 TEGRA_PLL_HAS_LOCK_ENABLE, 556 }; 557 558 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 559 { 9600000, 282240000, 147, 5, 1, 4 }, 560 { 9600000, 368640000, 192, 5, 1, 4 }, 561 { 9600000, 240000000, 200, 8, 1, 8 }, 562 { 28800000, 282240000, 245, 25, 1, 8 }, 563 { 28800000, 368640000, 320, 25, 1, 8 }, 564 { 28800000, 240000000, 200, 24, 1, 8 }, 565 { 0, 0, 0, 0, 0, 0 }, 566 }; 567 568 static struct tegra_clk_pll_params pll_a_params = { 569 .input_min = 2000000, 570 .input_max = 31000000, 571 .cf_min = 1000000, 572 .cf_max = 6000000, 573 .vco_min = 200000000, 574 .vco_max = 700000000, 575 .base_reg = PLLA_BASE, 576 .misc_reg = PLLA_MISC, 577 .lock_mask = PLL_BASE_LOCK, 578 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 579 .lock_delay = 300, 580 .div_nmp = &pllp_nmp, 581 .freq_table = pll_a_freq_table, 582 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 583 TEGRA_PLL_HAS_LOCK_ENABLE, 584 }; 585 586 static struct div_nmp plld_nmp = { 587 .divm_shift = 0, 588 .divm_width = 5, 589 .divn_shift = 8, 590 .divn_width = 11, 591 .divp_shift = 20, 592 .divp_width = 3, 593 }; 594 595 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 596 { 12000000, 216000000, 864, 12, 4, 12 }, 597 { 13000000, 216000000, 864, 13, 4, 12 }, 598 { 16800000, 216000000, 720, 14, 4, 12 }, 599 { 19200000, 216000000, 720, 16, 4, 12 }, 600 { 26000000, 216000000, 864, 26, 4, 12 }, 601 { 12000000, 594000000, 594, 12, 1, 12 }, 602 { 13000000, 594000000, 594, 13, 1, 12 }, 603 { 16800000, 594000000, 495, 14, 1, 12 }, 604 { 19200000, 594000000, 495, 16, 1, 12 }, 605 { 26000000, 594000000, 594, 26, 1, 12 }, 606 { 12000000, 1000000000, 1000, 12, 1, 12 }, 607 { 13000000, 1000000000, 1000, 13, 1, 12 }, 608 { 19200000, 1000000000, 625, 12, 1, 12 }, 609 { 26000000, 1000000000, 1000, 26, 1, 12 }, 610 { 0, 0, 0, 0, 0, 0 }, 611 }; 612 613 static struct tegra_clk_pll_params pll_d_params = { 614 .input_min = 2000000, 615 .input_max = 40000000, 616 .cf_min = 1000000, 617 .cf_max = 6000000, 618 .vco_min = 500000000, 619 .vco_max = 1000000000, 620 .base_reg = PLLD_BASE, 621 .misc_reg = PLLD_MISC, 622 .lock_mask = PLL_BASE_LOCK, 623 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 624 .lock_delay = 1000, 625 .div_nmp = &plld_nmp, 626 .freq_table = pll_d_freq_table, 627 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 628 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 629 }; 630 631 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = { 632 { 12000000, 594000000, 99, 1, 2, 0 }, 633 { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */ 634 { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 635 { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 636 { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */ 637 { 0, 0, 0, 0, 0, 0 }, 638 }; 639 640 static struct tegra_clk_pll_params tegra124_pll_d2_params = { 641 .input_min = 12000000, 642 .input_max = 1000000000, 643 .cf_min = 12000000, 644 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 645 .vco_min = 600000000, 646 .vco_max = 1200000000, 647 .base_reg = PLLD2_BASE, 648 .misc_reg = PLLD2_MISC, 649 .lock_mask = PLL_BASE_LOCK, 650 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 651 .lock_delay = 300, 652 .iddq_reg = PLLD2_BASE, 653 .iddq_bit_idx = PLLSS_IDDQ_BIT, 654 .pdiv_tohw = pll12g_ssd_esd_p, 655 .div_nmp = &pllss_nmp, 656 .ext_misc_reg[0] = 0x570, 657 .ext_misc_reg[1] = 0x574, 658 .ext_misc_reg[2] = 0x578, 659 .max_p = 15, 660 .freq_table = tegra124_pll_d2_freq_table, 661 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 662 }; 663 664 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 665 { 12000000, 600000000, 100, 1, 2, 0 }, 666 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 667 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 668 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 669 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 670 { 0, 0, 0, 0, 0, 0 }, 671 }; 672 673 static struct tegra_clk_pll_params pll_dp_params = { 674 .input_min = 12000000, 675 .input_max = 1000000000, 676 .cf_min = 12000000, 677 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 678 .vco_min = 600000000, 679 .vco_max = 1200000000, 680 .base_reg = PLLDP_BASE, 681 .misc_reg = PLLDP_MISC, 682 .lock_mask = PLL_BASE_LOCK, 683 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 684 .lock_delay = 300, 685 .iddq_reg = PLLDP_BASE, 686 .iddq_bit_idx = PLLSS_IDDQ_BIT, 687 .pdiv_tohw = pll12g_ssd_esd_p, 688 .div_nmp = &pllss_nmp, 689 .ext_misc_reg[0] = 0x598, 690 .ext_misc_reg[1] = 0x59c, 691 .ext_misc_reg[2] = 0x5a0, 692 .max_p = 5, 693 .freq_table = pll_dp_freq_table, 694 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 695 }; 696 697 static const struct pdiv_map pllu_p[] = { 698 { .pdiv = 1, .hw_val = 1 }, 699 { .pdiv = 2, .hw_val = 0 }, 700 { .pdiv = 0, .hw_val = 0 }, 701 }; 702 703 static struct div_nmp pllu_nmp = { 704 .divm_shift = 0, 705 .divm_width = 5, 706 .divn_shift = 8, 707 .divn_width = 10, 708 .divp_shift = 20, 709 .divp_width = 1, 710 }; 711 712 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 713 { 12000000, 480000000, 960, 12, 2, 12 }, 714 { 13000000, 480000000, 960, 13, 2, 12 }, 715 { 16800000, 480000000, 400, 7, 2, 5 }, 716 { 19200000, 480000000, 200, 4, 2, 3 }, 717 { 26000000, 480000000, 960, 26, 2, 12 }, 718 { 0, 0, 0, 0, 0, 0 }, 719 }; 720 721 static struct tegra_clk_pll_params pll_u_params = { 722 .input_min = 2000000, 723 .input_max = 40000000, 724 .cf_min = 1000000, 725 .cf_max = 6000000, 726 .vco_min = 480000000, 727 .vco_max = 960000000, 728 .base_reg = PLLU_BASE, 729 .misc_reg = PLLU_MISC, 730 .lock_mask = PLL_BASE_LOCK, 731 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 732 .lock_delay = 1000, 733 .pdiv_tohw = pllu_p, 734 .div_nmp = &pllu_nmp, 735 .freq_table = pll_u_freq_table, 736 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 737 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 738 }; 739 740 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 741 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true }, 742 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true }, 743 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true }, 744 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true }, 745 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true }, 746 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true }, 747 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true }, 748 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true }, 749 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true }, 750 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true }, 751 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true }, 752 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true }, 753 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true }, 754 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, 755 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, 756 [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true }, 757 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true }, 758 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true }, 759 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true }, 760 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true }, 761 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true }, 762 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true }, 763 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true }, 764 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true }, 765 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true }, 766 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true }, 767 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true }, 768 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true }, 769 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true }, 770 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true }, 771 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true }, 772 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true }, 773 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true }, 774 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true }, 775 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true }, 776 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true }, 777 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true }, 778 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true }, 779 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true }, 780 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true }, 781 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true }, 782 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true }, 783 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true }, 784 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true }, 785 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true }, 786 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true }, 787 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true }, 788 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, 789 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, 790 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true }, 791 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true }, 792 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true }, 793 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true }, 794 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true }, 795 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true }, 796 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true }, 797 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true }, 798 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true }, 799 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true }, 800 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true }, 801 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true }, 802 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true }, 803 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true }, 804 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true }, 805 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true }, 806 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true }, 807 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true }, 808 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true }, 809 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true }, 810 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true }, 811 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true }, 812 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true }, 813 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true }, 814 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true }, 815 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true }, 816 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true }, 817 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true }, 818 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true }, 819 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true }, 820 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true }, 821 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true }, 822 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true }, 823 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true }, 824 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true }, 825 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true }, 826 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true }, 827 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true }, 828 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true }, 829 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true }, 830 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true }, 831 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true }, 832 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true }, 833 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true }, 834 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true }, 835 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true }, 836 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true }, 837 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true }, 838 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true }, 839 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true }, 840 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true }, 841 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true }, 842 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true }, 843 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true }, 844 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true }, 845 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true }, 846 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true }, 847 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true }, 848 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true }, 849 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true }, 850 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true }, 851 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true }, 852 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true }, 853 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true }, 854 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true }, 855 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, 856 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true }, 857 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true }, 858 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true }, 859 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true }, 860 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true }, 861 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true }, 862 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true }, 863 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true }, 864 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true }, 865 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true }, 866 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true }, 867 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true }, 868 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true }, 869 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true }, 870 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true }, 871 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true }, 872 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true }, 873 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true }, 874 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true }, 875 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true }, 876 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true }, 877 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true }, 878 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true }, 879 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true }, 880 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true }, 881 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true }, 882 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true }, 883 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true }, 884 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true }, 885 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true }, 886 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true }, 887 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true }, 888 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true }, 889 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true }, 890 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true }, 891 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true }, 892 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true }, 893 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true }, 894 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true }, 895 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true }, 896 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true }, 897 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true }, 898 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true }, 899 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true }, 900 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true }, 901 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true }, 902 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true }, 903 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true }, 904 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true }, 905 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true }, 906 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true }, 907 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true }, 908 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true }, 909 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true }, 910 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true }, 911 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true }, 912 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true }, 913 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true }, 914 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true }, 915 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true }, 916 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true }, 917 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true }, 918 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true }, 919 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true }, 920 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true }, 921 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true }, 922 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true }, 923 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true }, 924 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true }, 925 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, 926 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, 927 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, 928 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, 929 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, 930 [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true }, 931 }; 932 933 static struct tegra_devclk devclks[] __initdata = { 934 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M }, 935 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF }, 936 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, 937 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 }, 938 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 }, 939 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C }, 940 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 }, 941 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 }, 942 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 }, 943 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P }, 944 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 }, 945 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 }, 946 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 }, 947 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 }, 948 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M }, 949 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 }, 950 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X }, 951 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 }, 952 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U }, 953 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M }, 954 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M }, 955 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M }, 956 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M }, 957 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D }, 958 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 }, 959 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 }, 960 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 }, 961 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A }, 962 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 }, 963 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO }, 964 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT }, 965 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC }, 966 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC }, 967 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC }, 968 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC }, 969 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC }, 970 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC }, 971 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC }, 972 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 }, 973 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 }, 974 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 }, 975 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 }, 976 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 }, 977 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF }, 978 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X }, 979 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X }, 980 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X }, 981 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X }, 982 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X }, 983 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X }, 984 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 }, 985 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 }, 986 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 }, 987 { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK }, 988 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G }, 989 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP }, 990 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK }, 991 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK }, 992 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK }, 993 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE }, 994 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC }, 995 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, 996 { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA }, 997 { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X }, 998 { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI }, 999 }; 1000 1001 static struct clk **clks; 1002 1003 static __init void tegra124_periph_clk_init(void __iomem *clk_base, 1004 void __iomem *pmc_base) 1005 { 1006 struct clk *clk; 1007 1008 /* xusb_ss_div2 */ 1009 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 1010 1, 2); 1011 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; 1012 1013 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, 1014 1, 17, 181); 1015 clks[TEGRA124_CLK_DPAUX] = clk; 1016 1017 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, 1018 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); 1019 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk; 1020 1021 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, 1022 clk_base, 0, 48, 1023 periph_clk_enb_refcnt); 1024 clks[TEGRA124_CLK_DSIA] = clk; 1025 1026 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, 1027 clk_base, 0, 82, 1028 periph_clk_enb_refcnt); 1029 clks[TEGRA124_CLK_DSIB] = clk; 1030 1031 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, 1032 &emc_lock); 1033 clks[TEGRA124_CLK_MC] = clk; 1034 1035 /* cml0 */ 1036 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1037 0, 0, &pll_e_lock); 1038 clk_register_clkdev(clk, "cml0", NULL); 1039 clks[TEGRA124_CLK_CML0] = clk; 1040 1041 /* cml1 */ 1042 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1043 1, 0, &pll_e_lock); 1044 clk_register_clkdev(clk, "cml1", NULL); 1045 clks[TEGRA124_CLK_CML1] = clk; 1046 1047 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); 1048 } 1049 1050 static void __init tegra124_pll_init(void __iomem *clk_base, 1051 void __iomem *pmc) 1052 { 1053 struct clk *clk; 1054 1055 /* PLLC */ 1056 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1057 pmc, 0, &pll_c_params, NULL); 1058 clk_register_clkdev(clk, "pll_c", NULL); 1059 clks[TEGRA124_CLK_PLL_C] = clk; 1060 1061 /* PLLC_OUT1 */ 1062 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1063 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1064 8, 8, 1, NULL); 1065 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1066 clk_base + PLLC_OUT, 1, 0, 1067 CLK_SET_RATE_PARENT, 0, NULL); 1068 clk_register_clkdev(clk, "pll_c_out1", NULL); 1069 clks[TEGRA124_CLK_PLL_C_OUT1] = clk; 1070 1071 /* PLLC_UD */ 1072 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", 1073 CLK_SET_RATE_PARENT, 1, 1); 1074 clk_register_clkdev(clk, "pll_c_ud", NULL); 1075 clks[TEGRA124_CLK_PLL_C_UD] = clk; 1076 1077 /* PLLC2 */ 1078 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 1079 &pll_c2_params, NULL); 1080 clk_register_clkdev(clk, "pll_c2", NULL); 1081 clks[TEGRA124_CLK_PLL_C2] = clk; 1082 1083 /* PLLC3 */ 1084 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 1085 &pll_c3_params, NULL); 1086 clk_register_clkdev(clk, "pll_c3", NULL); 1087 clks[TEGRA124_CLK_PLL_C3] = clk; 1088 1089 /* PLLM */ 1090 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1091 CLK_SET_RATE_GATE, &pll_m_params, NULL); 1092 clk_register_clkdev(clk, "pll_m", NULL); 1093 clks[TEGRA124_CLK_PLL_M] = clk; 1094 1095 /* PLLM_OUT1 */ 1096 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1097 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1098 8, 8, 1, NULL); 1099 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1100 clk_base + PLLM_OUT, 1, 0, 1101 CLK_SET_RATE_PARENT, 0, NULL); 1102 clk_register_clkdev(clk, "pll_m_out1", NULL); 1103 clks[TEGRA124_CLK_PLL_M_OUT1] = clk; 1104 1105 /* PLLM_UD */ 1106 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1107 CLK_SET_RATE_PARENT, 1, 1); 1108 clk_register_clkdev(clk, "pll_m_ud", NULL); 1109 clks[TEGRA124_CLK_PLL_M_UD] = clk; 1110 1111 /* PLLU */ 1112 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, 1113 &pll_u_params, &pll_u_lock); 1114 clk_register_clkdev(clk, "pll_u", NULL); 1115 clks[TEGRA124_CLK_PLL_U] = clk; 1116 1117 /* PLLU_480M */ 1118 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1119 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1120 22, 0, &pll_u_lock); 1121 clk_register_clkdev(clk, "pll_u_480M", NULL); 1122 clks[TEGRA124_CLK_PLL_U_480M] = clk; 1123 1124 /* PLLU_60M */ 1125 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1126 CLK_SET_RATE_PARENT, 1, 8); 1127 clk_register_clkdev(clk, "pll_u_60M", NULL); 1128 clks[TEGRA124_CLK_PLL_U_60M] = clk; 1129 1130 /* PLLU_48M */ 1131 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1132 CLK_SET_RATE_PARENT, 1, 10); 1133 clk_register_clkdev(clk, "pll_u_48M", NULL); 1134 clks[TEGRA124_CLK_PLL_U_48M] = clk; 1135 1136 /* PLLU_12M */ 1137 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1138 CLK_SET_RATE_PARENT, 1, 40); 1139 clk_register_clkdev(clk, "pll_u_12M", NULL); 1140 clks[TEGRA124_CLK_PLL_U_12M] = clk; 1141 1142 /* PLLD */ 1143 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1144 &pll_d_params, &pll_d_lock); 1145 clk_register_clkdev(clk, "pll_d", NULL); 1146 clks[TEGRA124_CLK_PLL_D] = clk; 1147 1148 /* PLLD_OUT0 */ 1149 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1150 CLK_SET_RATE_PARENT, 1, 2); 1151 clk_register_clkdev(clk, "pll_d_out0", NULL); 1152 clks[TEGRA124_CLK_PLL_D_OUT0] = clk; 1153 1154 /* PLLRE */ 1155 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1156 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); 1157 clk_register_clkdev(clk, "pll_re_vco", NULL); 1158 clks[TEGRA124_CLK_PLL_RE_VCO] = clk; 1159 1160 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1161 clk_base + PLLRE_BASE, 16, 4, 0, 1162 pll_re_div_table, &pll_re_lock); 1163 clk_register_clkdev(clk, "pll_re_out", NULL); 1164 clks[TEGRA124_CLK_PLL_RE_OUT] = clk; 1165 1166 /* PLLE */ 1167 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref", 1168 clk_base, 0, &pll_e_params, NULL); 1169 clk_register_clkdev(clk, "pll_e", NULL); 1170 clks[TEGRA124_CLK_PLL_E] = clk; 1171 1172 /* PLLC4 */ 1173 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0, 1174 &pll_c4_params, NULL); 1175 clk_register_clkdev(clk, "pll_c4", NULL); 1176 clks[TEGRA124_CLK_PLL_C4] = clk; 1177 1178 /* PLLDP */ 1179 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0, 1180 &pll_dp_params, NULL); 1181 clk_register_clkdev(clk, "pll_dp", NULL); 1182 clks[TEGRA124_CLK_PLL_DP] = clk; 1183 1184 /* PLLD2 */ 1185 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0, 1186 &tegra124_pll_d2_params, NULL); 1187 clk_register_clkdev(clk, "pll_d2", NULL); 1188 clks[TEGRA124_CLK_PLL_D2] = clk; 1189 1190 /* PLLD2_OUT0 */ 1191 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1192 CLK_SET_RATE_PARENT, 1, 1); 1193 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1194 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk; 1195 1196 } 1197 1198 /* Tegra124 CPU clock and reset control functions */ 1199 static void tegra124_wait_cpu_in_reset(u32 cpu) 1200 { 1201 unsigned int reg; 1202 1203 do { 1204 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1205 cpu_relax(); 1206 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1207 } 1208 1209 static void tegra124_disable_cpu_clock(u32 cpu) 1210 { 1211 /* flow controller would take care in the power sequence. */ 1212 } 1213 1214 #ifdef CONFIG_PM_SLEEP 1215 static void tegra124_cpu_clock_suspend(void) 1216 { 1217 /* switch coresite to clk_m, save off original source */ 1218 tegra124_cpu_clk_sctx.clk_csite_src = 1219 readl(clk_base + CLK_SOURCE_CSITE); 1220 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 1221 1222 tegra124_cpu_clk_sctx.cclkg_burst = 1223 readl(clk_base + CCLKG_BURST_POLICY); 1224 tegra124_cpu_clk_sctx.cclkg_divider = 1225 readl(clk_base + CCLKG_BURST_POLICY + 4); 1226 } 1227 1228 static void tegra124_cpu_clock_resume(void) 1229 { 1230 writel(tegra124_cpu_clk_sctx.clk_csite_src, 1231 clk_base + CLK_SOURCE_CSITE); 1232 1233 writel(tegra124_cpu_clk_sctx.cclkg_burst, 1234 clk_base + CCLKG_BURST_POLICY); 1235 writel(tegra124_cpu_clk_sctx.cclkg_divider, 1236 clk_base + CCLKG_BURST_POLICY + 4); 1237 } 1238 #endif 1239 1240 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { 1241 .wait_for_reset = tegra124_wait_cpu_in_reset, 1242 .disable_clock = tegra124_disable_cpu_clock, 1243 #ifdef CONFIG_PM_SLEEP 1244 .suspend = tegra124_cpu_clock_suspend, 1245 .resume = tegra124_cpu_clock_resume, 1246 #endif 1247 }; 1248 1249 static const struct of_device_id pmc_match[] __initconst = { 1250 { .compatible = "nvidia,tegra124-pmc" }, 1251 { }, 1252 }; 1253 1254 static struct tegra_clk_init_table common_init_table[] __initdata = { 1255 { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1256 { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1257 { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1258 { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1259 { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 }, 1260 { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 }, 1261 { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 }, 1262 { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 }, 1263 { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1264 { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1265 { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1266 { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1267 { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1268 { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1269 { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_C3, 600000000, 0 }, 1270 { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 }, 1271 { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 }, 1272 { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 }, 1273 { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 }, 1274 { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 }, 1275 { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 }, 1276 { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 }, 1277 { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 }, 1278 { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 }, 1279 { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 }, 1280 { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 }, 1281 { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 }, 1282 { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 }, 1283 { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 }, 1284 { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 }, 1285 { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 }, 1286 { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 }, 1287 { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 }, 1288 { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 }, 1289 { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1290 { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1291 { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 }, 1292 { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 }, 1293 { TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1294 { TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1295 { TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1296 { TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1297 { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1298 { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1299 { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1300 /* must be the last entry */ 1301 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, 1302 }; 1303 1304 static struct tegra_clk_init_table tegra124_init_table[] __initdata = { 1305 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 }, 1306 { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1307 { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 }, 1308 { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 }, 1309 /* must be the last entry */ 1310 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, 1311 }; 1312 1313 /* Tegra132 requires the SOC_THERM clock to remain active */ 1314 static struct tegra_clk_init_table tegra132_init_table[] __initdata = { 1315 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 }, 1316 /* must be the last entry */ 1317 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, 1318 }; 1319 1320 static struct tegra_audio_clk_info tegra124_audio_plls[] = { 1321 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" }, 1322 }; 1323 1324 /** 1325 * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs 1326 * 1327 * Program an initial clock rate and enable or disable clocks needed 1328 * by the rest of the kernel, for Tegra124 SoCs. It is intended to be 1329 * called by assigning a pointer to it to tegra_clk_apply_init_table - 1330 * this will be called as an arch_initcall. No return value. 1331 */ 1332 static void __init tegra124_clock_apply_init_table(void) 1333 { 1334 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); 1335 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX); 1336 } 1337 1338 /** 1339 * tegra124_car_barrier - wait for pending writes to the CAR to complete 1340 * 1341 * Wait for any outstanding writes to the CAR MMIO space from this CPU 1342 * to complete before continuing execution. No return value. 1343 */ 1344 static void tegra124_car_barrier(void) 1345 { 1346 readl_relaxed(clk_base + RST_DFLL_DVCO); 1347 } 1348 1349 /** 1350 * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 1351 * 1352 * Assert the reset line of the DFLL's DVCO. No return value. 1353 */ 1354 static void tegra124_clock_assert_dfll_dvco_reset(void) 1355 { 1356 u32 v; 1357 1358 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 1359 v |= (1 << DVFS_DFLL_RESET_SHIFT); 1360 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 1361 tegra124_car_barrier(); 1362 } 1363 1364 /** 1365 * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 1366 * 1367 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 1368 * operate. No return value. 1369 */ 1370 static void tegra124_clock_deassert_dfll_dvco_reset(void) 1371 { 1372 u32 v; 1373 1374 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 1375 v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 1376 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 1377 tegra124_car_barrier(); 1378 } 1379 1380 static int tegra124_reset_assert(unsigned long id) 1381 { 1382 if (id == TEGRA124_RST_DFLL_DVCO) 1383 tegra124_clock_assert_dfll_dvco_reset(); 1384 else 1385 return -EINVAL; 1386 1387 return 0; 1388 } 1389 1390 static int tegra124_reset_deassert(unsigned long id) 1391 { 1392 if (id == TEGRA124_RST_DFLL_DVCO) 1393 tegra124_clock_deassert_dfll_dvco_reset(); 1394 else 1395 return -EINVAL; 1396 1397 return 0; 1398 } 1399 1400 /** 1401 * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs 1402 * 1403 * Program an initial clock rate and enable or disable clocks needed 1404 * by the rest of the kernel, for Tegra132 SoCs. It is intended to be 1405 * called by assigning a pointer to it to tegra_clk_apply_init_table - 1406 * this will be called as an arch_initcall. No return value. 1407 */ 1408 static void __init tegra132_clock_apply_init_table(void) 1409 { 1410 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); 1411 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX); 1412 } 1413 1414 /** 1415 * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132 1416 * @np: struct device_node * of the DT node for the SoC CAR IP block 1417 * 1418 * Register most of the clocks controlled by the CAR IP block, along 1419 * with a few clocks controlled by the PMC IP block. Everything in 1420 * this function should be common to Tegra124 and Tegra132. XXX The 1421 * PMC clock initialization should probably be moved to PMC-specific 1422 * driver code. No return value. 1423 */ 1424 static void __init tegra124_132_clock_init_pre(struct device_node *np) 1425 { 1426 struct device_node *node; 1427 u32 plld_base; 1428 1429 clk_base = of_iomap(np, 0); 1430 if (!clk_base) { 1431 pr_err("ioremap tegra124/tegra132 CAR failed\n"); 1432 return; 1433 } 1434 1435 node = of_find_matching_node(NULL, pmc_match); 1436 if (!node) { 1437 pr_err("Failed to find pmc node\n"); 1438 WARN_ON(1); 1439 return; 1440 } 1441 1442 pmc_base = of_iomap(node, 0); 1443 if (!pmc_base) { 1444 pr_err("Can't map pmc registers\n"); 1445 WARN_ON(1); 1446 return; 1447 } 1448 1449 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 1450 TEGRA124_CAR_BANK_COUNT); 1451 if (!clks) 1452 return; 1453 1454 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq, 1455 ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq, 1456 &pll_ref_freq) < 0) 1457 return; 1458 1459 tegra_fixed_clk_init(tegra124_clks); 1460 tegra124_pll_init(clk_base, pmc_base); 1461 tegra124_periph_clk_init(clk_base, pmc_base); 1462 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, 1463 tegra124_audio_plls, 1464 ARRAY_SIZE(tegra124_audio_plls), 24576000); 1465 tegra_pmc_clk_init(pmc_base, tegra124_clks); 1466 1467 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */ 1468 plld_base = readl(clk_base + PLLD_BASE); 1469 plld_base &= ~BIT(25); 1470 writel(plld_base, clk_base + PLLD_BASE); 1471 } 1472 1473 /** 1474 * tegra124_132_clock_init_post - clock initialization postamble for T124/T132 1475 * @np: struct device_node * of the DT node for the SoC CAR IP block 1476 * 1477 * Register most of the along with a few clocks controlled by the PMC 1478 * IP block. Everything in this function should be common to Tegra124 1479 * and Tegra132. This function must be called after 1480 * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will 1481 * not be set. No return value. 1482 */ 1483 static void __init tegra124_132_clock_init_post(struct device_node *np) 1484 { 1485 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, 1486 &pll_x_params); 1487 tegra_init_special_resets(1, tegra124_reset_assert, 1488 tegra124_reset_deassert); 1489 tegra_add_of_provider(np, of_clk_src_onecell_get); 1490 1491 clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, 1492 &emc_lock); 1493 1494 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1495 1496 tegra_cpu_car_ops = &tegra124_cpu_car_ops; 1497 } 1498 1499 /** 1500 * tegra124_clock_init - Tegra124-specific clock initialization 1501 * @np: struct device_node * of the DT node for the SoC CAR IP block 1502 * 1503 * Register most SoC clocks for the Tegra124 system-on-chip. Most of 1504 * this code is shared between the Tegra124 and Tegra132 SoCs, 1505 * although some of the initial clock settings and CPU clocks differ. 1506 * Intended to be called by the OF init code when a DT node with the 1507 * "nvidia,tegra124-car" string is encountered, and declared with 1508 * CLK_OF_DECLARE. No return value. 1509 */ 1510 static void __init tegra124_clock_init(struct device_node *np) 1511 { 1512 tegra124_132_clock_init_pre(np); 1513 tegra_clk_apply_init_table = tegra124_clock_apply_init_table; 1514 tegra124_132_clock_init_post(np); 1515 } 1516 1517 /** 1518 * tegra132_clock_init - Tegra132-specific clock initialization 1519 * @np: struct device_node * of the DT node for the SoC CAR IP block 1520 * 1521 * Register most SoC clocks for the Tegra132 system-on-chip. Most of 1522 * this code is shared between the Tegra124 and Tegra132 SoCs, 1523 * although some of the initial clock settings and CPU clocks differ. 1524 * Intended to be called by the OF init code when a DT node with the 1525 * "nvidia,tegra132-car" string is encountered, and declared with 1526 * CLK_OF_DECLARE. No return value. 1527 */ 1528 static void __init tegra132_clock_init(struct device_node *np) 1529 { 1530 tegra124_132_clock_init_pre(np); 1531 1532 /* 1533 * On Tegra132, these clocks are controlled by the 1534 * CLUSTER_clocks IP block, located in the CPU complex 1535 */ 1536 tegra124_clks[tegra_clk_cclk_g].present = false; 1537 tegra124_clks[tegra_clk_cclk_lp].present = false; 1538 tegra124_clks[tegra_clk_pll_x].present = false; 1539 tegra124_clks[tegra_clk_pll_x_out0].present = false; 1540 1541 tegra_clk_apply_init_table = tegra132_clock_apply_init_table; 1542 tegra124_132_clock_init_post(np); 1543 } 1544 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init); 1545 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init); 1546