1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/clk/tegra/clk-emc.c 4 * 5 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Author: 8 * Mikko Perttunen <mperttunen@nvidia.com> 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/clk/tegra.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of_address.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/sort.h> 23 #include <linux/string.h> 24 25 #include <soc/tegra/fuse.h> 26 27 #include "clk.h" 28 29 #define CLK_SOURCE_EMC 0x19c 30 31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0 32 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff 33 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \ 34 CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT) 35 36 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29 37 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7 38 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \ 39 CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT) 40 41 static const char * const emc_parent_clk_names[] = { 42 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", 43 "pll_c2", "pll_c3", "pll_c_ud" 44 }; 45 46 /* 47 * List of clock sources for various parents the EMC clock can have. 48 * When we change the timing to a timing with a parent that has the same 49 * clock source as the current parent, we must first change to a backup 50 * timing that has a different clock source. 51 */ 52 53 #define EMC_SRC_PLL_M 0 54 #define EMC_SRC_PLL_C 1 55 #define EMC_SRC_PLL_P 2 56 #define EMC_SRC_CLK_M 3 57 #define EMC_SRC_PLL_C2 4 58 #define EMC_SRC_PLL_C3 5 59 60 static const char emc_parent_clk_sources[] = { 61 EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M, 62 EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C 63 }; 64 65 struct emc_timing { 66 unsigned long rate, parent_rate; 67 u8 parent_index; 68 struct clk *parent; 69 u32 ram_code; 70 }; 71 72 struct tegra_clk_emc { 73 struct clk_hw hw; 74 void __iomem *clk_regs; 75 struct clk *prev_parent; 76 bool changing_timing; 77 78 struct device_node *emc_node; 79 struct tegra_emc *emc; 80 81 int num_timings; 82 struct emc_timing *timings; 83 spinlock_t *lock; 84 85 tegra124_emc_prepare_timing_change_cb *prepare_timing_change; 86 tegra124_emc_complete_timing_change_cb *complete_timing_change; 87 }; 88 89 /* Common clock framework callback implementations */ 90 91 static unsigned long emc_recalc_rate(struct clk_hw *hw, 92 unsigned long parent_rate) 93 { 94 struct tegra_clk_emc *tegra; 95 u32 val, div; 96 97 tegra = container_of(hw, struct tegra_clk_emc, hw); 98 99 /* 100 * CCF wrongly assumes that the parent won't change during set_rate, 101 * so get the parent rate explicitly. 102 */ 103 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 104 105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); 106 div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK; 107 108 return parent_rate / (div + 2) * 2; 109 } 110 111 /* 112 * Rounds up unless no higher rate exists, in which case down. This way is 113 * safer since things have EMC rate floors. Also don't touch parent_rate 114 * since we don't want the CCF to play with our parent clocks. 115 */ 116 static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 117 { 118 struct tegra_clk_emc *tegra; 119 u8 ram_code = tegra_read_ram_code(); 120 struct emc_timing *timing = NULL; 121 int i, k, t; 122 123 tegra = container_of(hw, struct tegra_clk_emc, hw); 124 125 for (k = 0; k < tegra->num_timings; k++) { 126 if (tegra->timings[k].ram_code == ram_code) 127 break; 128 } 129 130 for (t = k; t < tegra->num_timings; t++) { 131 if (tegra->timings[t].ram_code != ram_code) 132 break; 133 } 134 135 for (i = k; i < t; i++) { 136 timing = tegra->timings + i; 137 138 if (timing->rate < req->rate && i != t - 1) 139 continue; 140 141 if (timing->rate > req->max_rate) { 142 i = max(i, k + 1); 143 req->rate = tegra->timings[i - 1].rate; 144 return 0; 145 } 146 147 if (timing->rate < req->min_rate) 148 continue; 149 150 req->rate = timing->rate; 151 return 0; 152 } 153 154 if (timing) { 155 req->rate = timing->rate; 156 return 0; 157 } 158 159 req->rate = clk_hw_get_rate(hw); 160 return 0; 161 } 162 163 static u8 emc_get_parent(struct clk_hw *hw) 164 { 165 struct tegra_clk_emc *tegra; 166 u32 val; 167 168 tegra = container_of(hw, struct tegra_clk_emc, hw); 169 170 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); 171 172 return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT) 173 & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK; 174 } 175 176 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra) 177 { 178 struct platform_device *pdev; 179 180 if (tegra->emc) 181 return tegra->emc; 182 183 if (!tegra->prepare_timing_change || !tegra->complete_timing_change) 184 return NULL; 185 186 if (!tegra->emc_node) 187 return NULL; 188 189 pdev = of_find_device_by_node(tegra->emc_node); 190 if (!pdev) { 191 pr_err("%s: could not get external memory controller\n", 192 __func__); 193 return NULL; 194 } 195 196 of_node_put(tegra->emc_node); 197 tegra->emc_node = NULL; 198 199 tegra->emc = platform_get_drvdata(pdev); 200 if (!tegra->emc) { 201 pr_err("%s: cannot find EMC driver\n", __func__); 202 return NULL; 203 } 204 205 return tegra->emc; 206 } 207 208 static int emc_set_timing(struct tegra_clk_emc *tegra, 209 struct emc_timing *timing) 210 { 211 int err; 212 u8 div; 213 u32 car_value; 214 unsigned long flags = 0; 215 struct tegra_emc *emc = emc_ensure_emc_driver(tegra); 216 217 if (!emc) 218 return -ENOENT; 219 220 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, 221 timing->parent_rate, __clk_get_name(timing->parent)); 222 223 if (emc_get_parent(&tegra->hw) == timing->parent_index && 224 clk_get_rate(timing->parent) != timing->parent_rate) { 225 WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n", 226 __clk_get_name(timing->parent), 227 clk_get_rate(timing->parent), 228 timing->parent_rate); 229 return -EINVAL; 230 } 231 232 tegra->changing_timing = true; 233 234 err = clk_set_rate(timing->parent, timing->parent_rate); 235 if (err) { 236 pr_err("cannot change parent %s rate to %ld: %d\n", 237 __clk_get_name(timing->parent), timing->parent_rate, 238 err); 239 240 return err; 241 } 242 243 err = clk_prepare_enable(timing->parent); 244 if (err) { 245 pr_err("cannot enable parent clock: %d\n", err); 246 return err; 247 } 248 249 div = timing->parent_rate / (timing->rate / 2) - 2; 250 251 err = tegra->prepare_timing_change(emc, timing->rate); 252 if (err) 253 return err; 254 255 spin_lock_irqsave(tegra->lock, flags); 256 257 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); 258 259 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0); 260 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index); 261 262 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0); 263 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div); 264 265 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); 266 267 spin_unlock_irqrestore(tegra->lock, flags); 268 269 tegra->complete_timing_change(emc, timing->rate); 270 271 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); 272 clk_disable_unprepare(tegra->prev_parent); 273 274 tegra->prev_parent = timing->parent; 275 tegra->changing_timing = false; 276 277 return 0; 278 } 279 280 /* 281 * Get backup timing to use as an intermediate step when a change between 282 * two timings with the same clock source has been requested. First try to 283 * find a timing with a higher clock rate to avoid a rate below any set rate 284 * floors. If that is not possible, find a lower rate. 285 */ 286 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra, 287 int timing_index) 288 { 289 int i; 290 u32 ram_code = tegra_read_ram_code(); 291 struct emc_timing *timing; 292 293 for (i = timing_index+1; i < tegra->num_timings; i++) { 294 timing = tegra->timings + i; 295 if (timing->ram_code != ram_code) 296 break; 297 298 if (emc_parent_clk_sources[timing->parent_index] != 299 emc_parent_clk_sources[ 300 tegra->timings[timing_index].parent_index]) 301 return timing; 302 } 303 304 for (i = timing_index-1; i >= 0; --i) { 305 timing = tegra->timings + i; 306 if (timing->ram_code != ram_code) 307 break; 308 309 if (emc_parent_clk_sources[timing->parent_index] != 310 emc_parent_clk_sources[ 311 tegra->timings[timing_index].parent_index]) 312 return timing; 313 } 314 315 return NULL; 316 } 317 318 static int emc_set_rate(struct clk_hw *hw, unsigned long rate, 319 unsigned long parent_rate) 320 { 321 struct tegra_clk_emc *tegra; 322 struct emc_timing *timing = NULL; 323 int i, err; 324 u32 ram_code = tegra_read_ram_code(); 325 326 tegra = container_of(hw, struct tegra_clk_emc, hw); 327 328 if (clk_hw_get_rate(hw) == rate) 329 return 0; 330 331 /* 332 * When emc_set_timing changes the parent rate, CCF will propagate 333 * that downward to us, so ignore any set_rate calls while a rate 334 * change is already going on. 335 */ 336 if (tegra->changing_timing) 337 return 0; 338 339 for (i = 0; i < tegra->num_timings; i++) { 340 if (tegra->timings[i].rate == rate && 341 tegra->timings[i].ram_code == ram_code) { 342 timing = tegra->timings + i; 343 break; 344 } 345 } 346 347 if (!timing) { 348 pr_err("cannot switch to rate %ld without emc table\n", rate); 349 return -EINVAL; 350 } 351 352 if (emc_parent_clk_sources[emc_get_parent(hw)] == 353 emc_parent_clk_sources[timing->parent_index] && 354 clk_get_rate(timing->parent) != timing->parent_rate) { 355 /* 356 * Parent clock source not changed but parent rate has changed, 357 * need to temporarily switch to another parent 358 */ 359 360 struct emc_timing *backup_timing; 361 362 backup_timing = get_backup_timing(tegra, i); 363 if (!backup_timing) { 364 pr_err("cannot find backup timing\n"); 365 return -EINVAL; 366 } 367 368 pr_debug("using %ld as backup rate when going to %ld\n", 369 backup_timing->rate, rate); 370 371 err = emc_set_timing(tegra, backup_timing); 372 if (err) { 373 pr_err("cannot set backup timing: %d\n", err); 374 return err; 375 } 376 } 377 378 return emc_set_timing(tegra, timing); 379 } 380 381 /* Initialization and deinitialization */ 382 383 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra, 384 struct emc_timing *timing, 385 struct device_node *node) 386 { 387 int err, i; 388 u32 tmp; 389 390 err = of_property_read_u32(node, "clock-frequency", &tmp); 391 if (err) { 392 pr_err("timing %pOF: failed to read rate\n", node); 393 return err; 394 } 395 396 timing->rate = tmp; 397 398 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp); 399 if (err) { 400 pr_err("timing %pOF: failed to read parent rate\n", node); 401 return err; 402 } 403 404 timing->parent_rate = tmp; 405 406 timing->parent = of_clk_get_by_name(node, "emc-parent"); 407 if (IS_ERR(timing->parent)) { 408 pr_err("timing %pOF: failed to get parent clock\n", node); 409 return PTR_ERR(timing->parent); 410 } 411 412 timing->parent_index = 0xff; 413 i = match_string(emc_parent_clk_names, ARRAY_SIZE(emc_parent_clk_names), 414 __clk_get_name(timing->parent)); 415 if (i < 0) { 416 pr_err("timing %pOF: %s is not a valid parent\n", 417 node, __clk_get_name(timing->parent)); 418 clk_put(timing->parent); 419 return -EINVAL; 420 } 421 422 timing->parent_index = i; 423 return 0; 424 } 425 426 static int cmp_timings(const void *_a, const void *_b) 427 { 428 const struct emc_timing *a = _a; 429 const struct emc_timing *b = _b; 430 431 if (a->rate < b->rate) 432 return -1; 433 else if (a->rate == b->rate) 434 return 0; 435 else 436 return 1; 437 } 438 439 static int load_timings_from_dt(struct tegra_clk_emc *tegra, 440 struct device_node *node, 441 u32 ram_code) 442 { 443 struct emc_timing *timings_ptr; 444 struct device_node *child; 445 int child_count = of_get_child_count(node); 446 int i = 0, err; 447 size_t size; 448 449 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing); 450 451 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL); 452 if (!tegra->timings) 453 return -ENOMEM; 454 455 timings_ptr = tegra->timings + tegra->num_timings; 456 tegra->num_timings += child_count; 457 458 for_each_child_of_node(node, child) { 459 struct emc_timing *timing = timings_ptr + (i++); 460 461 err = load_one_timing_from_dt(tegra, timing, child); 462 if (err) { 463 of_node_put(child); 464 return err; 465 } 466 467 timing->ram_code = ram_code; 468 } 469 470 sort(timings_ptr, child_count, sizeof(struct emc_timing), 471 cmp_timings, NULL); 472 473 return 0; 474 } 475 476 static const struct clk_ops tegra_clk_emc_ops = { 477 .recalc_rate = emc_recalc_rate, 478 .determine_rate = emc_determine_rate, 479 .set_rate = emc_set_rate, 480 .get_parent = emc_get_parent, 481 }; 482 483 struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, 484 spinlock_t *lock) 485 { 486 struct tegra_clk_emc *tegra; 487 struct clk_init_data init; 488 struct device_node *node; 489 u32 node_ram_code; 490 struct clk *clk; 491 int err; 492 493 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL); 494 if (!tegra) 495 return ERR_PTR(-ENOMEM); 496 497 tegra->clk_regs = base; 498 tegra->lock = lock; 499 500 tegra->num_timings = 0; 501 502 for_each_child_of_node(np, node) { 503 err = of_property_read_u32(node, "nvidia,ram-code", 504 &node_ram_code); 505 if (err) 506 continue; 507 508 /* 509 * Store timings for all ram codes as we cannot read the 510 * fuses until the apbmisc driver is loaded. 511 */ 512 err = load_timings_from_dt(tegra, node, node_ram_code); 513 if (err) { 514 of_node_put(node); 515 return ERR_PTR(err); 516 } 517 } 518 519 if (tegra->num_timings == 0) 520 pr_warn("%s: no memory timings registered\n", __func__); 521 522 tegra->emc_node = of_parse_phandle(np, 523 "nvidia,external-memory-controller", 0); 524 if (!tegra->emc_node) 525 pr_warn("%s: couldn't find node for EMC driver\n", __func__); 526 527 init.name = "emc"; 528 init.ops = &tegra_clk_emc_ops; 529 init.flags = CLK_IS_CRITICAL; 530 init.parent_names = emc_parent_clk_names; 531 init.num_parents = ARRAY_SIZE(emc_parent_clk_names); 532 533 tegra->hw.init = &init; 534 535 clk = clk_register(NULL, &tegra->hw); 536 if (IS_ERR(clk)) 537 return clk; 538 539 tegra->prev_parent = clk_hw_get_parent_by_index( 540 &tegra->hw, emc_get_parent(&tegra->hw))->clk; 541 tegra->changing_timing = false; 542 543 /* Allow debugging tools to see the EMC clock */ 544 clk_register_clkdev(clk, "emc", "tegra-clk-debug"); 545 546 return clk; 547 }; 548 549 void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, 550 tegra124_emc_complete_timing_change_cb *complete_cb) 551 { 552 struct clk *clk = __clk_lookup("emc"); 553 struct tegra_clk_emc *tegra; 554 struct clk_hw *hw; 555 556 if (clk) { 557 hw = __clk_get_hw(clk); 558 tegra = container_of(hw, struct tegra_clk_emc, hw); 559 560 tegra->prepare_timing_change = prep_cb; 561 tegra->complete_timing_change = complete_cb; 562 } 563 } 564 EXPORT_SYMBOL_GPL(tegra124_clk_set_emc_callbacks); 565 566 bool tegra124_clk_emc_driver_available(struct clk_hw *hw) 567 { 568 struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw); 569 570 return tegra->prepare_timing_change && tegra->complete_timing_change; 571 } 572