1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/clkdev.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/delay.h> 24 #include <linux/export.h> 25 #include <linux/clk/tegra.h> 26 27 #include "clk.h" 28 29 #define RST_DEVICES_L 0x004 30 #define RST_DEVICES_H 0x008 31 #define RST_DEVICES_U 0x00C 32 #define RST_DFLL_DVCO 0x2F4 33 #define RST_DEVICES_V 0x358 34 #define RST_DEVICES_W 0x35C 35 #define RST_DEVICES_X 0x28C 36 #define RST_DEVICES_SET_L 0x300 37 #define RST_DEVICES_CLR_L 0x304 38 #define RST_DEVICES_SET_H 0x308 39 #define RST_DEVICES_CLR_H 0x30c 40 #define RST_DEVICES_SET_U 0x310 41 #define RST_DEVICES_CLR_U 0x314 42 #define RST_DEVICES_SET_V 0x430 43 #define RST_DEVICES_CLR_V 0x434 44 #define RST_DEVICES_SET_W 0x438 45 #define RST_DEVICES_CLR_W 0x43c 46 #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 47 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ 48 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 49 #define RST_DEVICES_NUM 5 50 51 /* RST_DFLL_DVCO bitfields */ 52 #define DVFS_DFLL_RESET_SHIFT 0 53 54 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */ 55 #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ 56 #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ 57 #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */ 58 #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */ 59 #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */ 60 #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */ 61 62 /* CPU_FINETRIM_R bitfields */ 63 #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */ 64 #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT) 65 #define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */ 66 #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT) 67 #define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */ 68 #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT) 69 #define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */ 70 #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT) 71 #define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */ 72 #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT) 73 #define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ 74 #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) 75 76 #define CLK_OUT_ENB_L 0x010 77 #define CLK_OUT_ENB_H 0x014 78 #define CLK_OUT_ENB_U 0x018 79 #define CLK_OUT_ENB_V 0x360 80 #define CLK_OUT_ENB_W 0x364 81 #define CLK_OUT_ENB_X 0x280 82 #define CLK_OUT_ENB_SET_L 0x320 83 #define CLK_OUT_ENB_CLR_L 0x324 84 #define CLK_OUT_ENB_SET_H 0x328 85 #define CLK_OUT_ENB_CLR_H 0x32c 86 #define CLK_OUT_ENB_SET_U 0x330 87 #define CLK_OUT_ENB_CLR_U 0x334 88 #define CLK_OUT_ENB_SET_V 0x440 89 #define CLK_OUT_ENB_CLR_V 0x444 90 #define CLK_OUT_ENB_SET_W 0x448 91 #define CLK_OUT_ENB_CLR_W 0x44c 92 #define CLK_OUT_ENB_SET_X 0x284 93 #define CLK_OUT_ENB_CLR_X 0x288 94 #define CLK_OUT_ENB_NUM 6 95 96 #define PLLC_BASE 0x80 97 #define PLLC_MISC2 0x88 98 #define PLLC_MISC 0x8c 99 #define PLLC2_BASE 0x4e8 100 #define PLLC2_MISC 0x4ec 101 #define PLLC3_BASE 0x4fc 102 #define PLLC3_MISC 0x500 103 #define PLLM_BASE 0x90 104 #define PLLM_MISC 0x9c 105 #define PLLP_BASE 0xa0 106 #define PLLP_MISC 0xac 107 #define PLLX_BASE 0xe0 108 #define PLLX_MISC 0xe4 109 #define PLLX_MISC2 0x514 110 #define PLLX_MISC3 0x518 111 #define PLLD_BASE 0xd0 112 #define PLLD_MISC 0xdc 113 #define PLLD2_BASE 0x4b8 114 #define PLLD2_MISC 0x4bc 115 #define PLLE_BASE 0xe8 116 #define PLLE_MISC 0xec 117 #define PLLA_BASE 0xb0 118 #define PLLA_MISC 0xbc 119 #define PLLU_BASE 0xc0 120 #define PLLU_MISC 0xcc 121 #define PLLRE_BASE 0x4c4 122 #define PLLRE_MISC 0x4c8 123 124 #define PLL_MISC_LOCK_ENABLE 18 125 #define PLLC_MISC_LOCK_ENABLE 24 126 #define PLLDU_MISC_LOCK_ENABLE 22 127 #define PLLE_MISC_LOCK_ENABLE 9 128 #define PLLRE_MISC_LOCK_ENABLE 30 129 130 #define PLLC_IDDQ_BIT 26 131 #define PLLX_IDDQ_BIT 3 132 #define PLLRE_IDDQ_BIT 16 133 134 #define PLL_BASE_LOCK BIT(27) 135 #define PLLE_MISC_LOCK BIT(11) 136 #define PLLRE_MISC_LOCK BIT(24) 137 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) 138 139 #define PLLE_AUX 0x48c 140 #define PLLC_OUT 0x84 141 #define PLLM_OUT 0x94 142 #define PLLP_OUTA 0xa4 143 #define PLLP_OUTB 0xa8 144 #define PLLA_OUT 0xb4 145 146 #define AUDIO_SYNC_CLK_I2S0 0x4a0 147 #define AUDIO_SYNC_CLK_I2S1 0x4a4 148 #define AUDIO_SYNC_CLK_I2S2 0x4a8 149 #define AUDIO_SYNC_CLK_I2S3 0x4ac 150 #define AUDIO_SYNC_CLK_I2S4 0x4b0 151 #define AUDIO_SYNC_CLK_SPDIF 0x4b4 152 153 #define AUDIO_SYNC_DOUBLER 0x49c 154 155 #define PMC_CLK_OUT_CNTRL 0x1a8 156 #define PMC_DPD_PADS_ORIDE 0x1c 157 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 158 #define PMC_CTRL 0 159 #define PMC_CTRL_BLINK_ENB 7 160 #define PMC_BLINK_TIMER 0x40 161 162 #define OSC_CTRL 0x50 163 #define OSC_CTRL_OSC_FREQ_SHIFT 28 164 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 165 166 #define PLLXC_SW_MAX_P 6 167 168 #define CCLKG_BURST_POLICY 0x368 169 #define CCLKLP_BURST_POLICY 0x370 170 #define SCLK_BURST_POLICY 0x028 171 #define SYSTEM_CLK_RATE 0x030 172 173 #define UTMIP_PLL_CFG2 0x488 174 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 175 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 176 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 177 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 178 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 179 180 #define UTMIP_PLL_CFG1 0x484 181 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 182 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 183 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 184 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 185 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 186 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 187 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 188 189 #define UTMIPLL_HW_PWRDN_CFG0 0x52c 190 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 191 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 192 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 193 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 194 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 195 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 196 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 197 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 198 199 #define CLK_SOURCE_I2S0 0x1d8 200 #define CLK_SOURCE_I2S1 0x100 201 #define CLK_SOURCE_I2S2 0x104 202 #define CLK_SOURCE_NDFLASH 0x160 203 #define CLK_SOURCE_I2S3 0x3bc 204 #define CLK_SOURCE_I2S4 0x3c0 205 #define CLK_SOURCE_SPDIF_OUT 0x108 206 #define CLK_SOURCE_SPDIF_IN 0x10c 207 #define CLK_SOURCE_PWM 0x110 208 #define CLK_SOURCE_ADX 0x638 209 #define CLK_SOURCE_AMX 0x63c 210 #define CLK_SOURCE_HDA 0x428 211 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4 212 #define CLK_SOURCE_SBC1 0x134 213 #define CLK_SOURCE_SBC2 0x118 214 #define CLK_SOURCE_SBC3 0x11c 215 #define CLK_SOURCE_SBC4 0x1b4 216 #define CLK_SOURCE_SBC5 0x3c8 217 #define CLK_SOURCE_SBC6 0x3cc 218 #define CLK_SOURCE_SATA_OOB 0x420 219 #define CLK_SOURCE_SATA 0x424 220 #define CLK_SOURCE_NDSPEED 0x3f8 221 #define CLK_SOURCE_VFIR 0x168 222 #define CLK_SOURCE_SDMMC1 0x150 223 #define CLK_SOURCE_SDMMC2 0x154 224 #define CLK_SOURCE_SDMMC3 0x1bc 225 #define CLK_SOURCE_SDMMC4 0x164 226 #define CLK_SOURCE_VDE 0x1c8 227 #define CLK_SOURCE_CSITE 0x1d4 228 #define CLK_SOURCE_LA 0x1f8 229 #define CLK_SOURCE_TRACE 0x634 230 #define CLK_SOURCE_OWR 0x1cc 231 #define CLK_SOURCE_NOR 0x1d0 232 #define CLK_SOURCE_MIPI 0x174 233 #define CLK_SOURCE_I2C1 0x124 234 #define CLK_SOURCE_I2C2 0x198 235 #define CLK_SOURCE_I2C3 0x1b8 236 #define CLK_SOURCE_I2C4 0x3c4 237 #define CLK_SOURCE_I2C5 0x128 238 #define CLK_SOURCE_UARTA 0x178 239 #define CLK_SOURCE_UARTB 0x17c 240 #define CLK_SOURCE_UARTC 0x1a0 241 #define CLK_SOURCE_UARTD 0x1c0 242 #define CLK_SOURCE_UARTE 0x1c4 243 #define CLK_SOURCE_UARTA_DBG 0x178 244 #define CLK_SOURCE_UARTB_DBG 0x17c 245 #define CLK_SOURCE_UARTC_DBG 0x1a0 246 #define CLK_SOURCE_UARTD_DBG 0x1c0 247 #define CLK_SOURCE_UARTE_DBG 0x1c4 248 #define CLK_SOURCE_3D 0x158 249 #define CLK_SOURCE_2D 0x15c 250 #define CLK_SOURCE_VI_SENSOR 0x1a8 251 #define CLK_SOURCE_VI 0x148 252 #define CLK_SOURCE_EPP 0x16c 253 #define CLK_SOURCE_MSENC 0x1f0 254 #define CLK_SOURCE_TSEC 0x1f4 255 #define CLK_SOURCE_HOST1X 0x180 256 #define CLK_SOURCE_HDMI 0x18c 257 #define CLK_SOURCE_DISP1 0x138 258 #define CLK_SOURCE_DISP2 0x13c 259 #define CLK_SOURCE_CILAB 0x614 260 #define CLK_SOURCE_CILCD 0x618 261 #define CLK_SOURCE_CILE 0x61c 262 #define CLK_SOURCE_DSIALP 0x620 263 #define CLK_SOURCE_DSIBLP 0x624 264 #define CLK_SOURCE_TSENSOR 0x3b8 265 #define CLK_SOURCE_D_AUDIO 0x3d0 266 #define CLK_SOURCE_DAM0 0x3d8 267 #define CLK_SOURCE_DAM1 0x3dc 268 #define CLK_SOURCE_DAM2 0x3e0 269 #define CLK_SOURCE_ACTMON 0x3e8 270 #define CLK_SOURCE_EXTERN1 0x3ec 271 #define CLK_SOURCE_EXTERN2 0x3f0 272 #define CLK_SOURCE_EXTERN3 0x3f4 273 #define CLK_SOURCE_I2CSLOW 0x3fc 274 #define CLK_SOURCE_SE 0x42c 275 #define CLK_SOURCE_MSELECT 0x3b4 276 #define CLK_SOURCE_DFLL_REF 0x62c 277 #define CLK_SOURCE_DFLL_SOC 0x630 278 #define CLK_SOURCE_SOC_THERM 0x644 279 #define CLK_SOURCE_XUSB_HOST_SRC 0x600 280 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604 281 #define CLK_SOURCE_XUSB_FS_SRC 0x608 282 #define CLK_SOURCE_XUSB_SS_SRC 0x610 283 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c 284 #define CLK_SOURCE_EMC 0x19c 285 286 /* PLLM override registers */ 287 #define PMC_PLLM_WB0_OVERRIDE 0x1dc 288 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 289 290 /* Tegra CPU clock and reset control regs */ 291 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 292 293 #ifdef CONFIG_PM_SLEEP 294 static struct cpu_clk_suspend_context { 295 u32 clk_csite_src; 296 u32 cclkg_burst; 297 u32 cclkg_divider; 298 } tegra114_cpu_clk_sctx; 299 #endif 300 301 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 302 303 static void __iomem *clk_base; 304 static void __iomem *pmc_base; 305 306 static DEFINE_SPINLOCK(pll_d_lock); 307 static DEFINE_SPINLOCK(pll_d2_lock); 308 static DEFINE_SPINLOCK(pll_u_lock); 309 static DEFINE_SPINLOCK(pll_div_lock); 310 static DEFINE_SPINLOCK(pll_re_lock); 311 static DEFINE_SPINLOCK(clk_doubler_lock); 312 static DEFINE_SPINLOCK(clk_out_lock); 313 static DEFINE_SPINLOCK(sysrate_lock); 314 315 static struct div_nmp pllxc_nmp = { 316 .divm_shift = 0, 317 .divm_width = 8, 318 .divn_shift = 8, 319 .divn_width = 8, 320 .divp_shift = 20, 321 .divp_width = 4, 322 }; 323 324 static struct pdiv_map pllxc_p[] = { 325 { .pdiv = 1, .hw_val = 0 }, 326 { .pdiv = 2, .hw_val = 1 }, 327 { .pdiv = 3, .hw_val = 2 }, 328 { .pdiv = 4, .hw_val = 3 }, 329 { .pdiv = 5, .hw_val = 4 }, 330 { .pdiv = 6, .hw_val = 5 }, 331 { .pdiv = 8, .hw_val = 6 }, 332 { .pdiv = 10, .hw_val = 7 }, 333 { .pdiv = 12, .hw_val = 8 }, 334 { .pdiv = 16, .hw_val = 9 }, 335 { .pdiv = 12, .hw_val = 10 }, 336 { .pdiv = 16, .hw_val = 11 }, 337 { .pdiv = 20, .hw_val = 12 }, 338 { .pdiv = 24, .hw_val = 13 }, 339 { .pdiv = 32, .hw_val = 14 }, 340 { .pdiv = 0, .hw_val = 0 }, 341 }; 342 343 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 344 { 12000000, 624000000, 104, 0, 2}, 345 { 12000000, 600000000, 100, 0, 2}, 346 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 347 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 348 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 349 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 350 { 0, 0, 0, 0, 0, 0 }, 351 }; 352 353 static struct tegra_clk_pll_params pll_c_params = { 354 .input_min = 12000000, 355 .input_max = 800000000, 356 .cf_min = 12000000, 357 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 358 .vco_min = 600000000, 359 .vco_max = 1400000000, 360 .base_reg = PLLC_BASE, 361 .misc_reg = PLLC_MISC, 362 .lock_mask = PLL_BASE_LOCK, 363 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 364 .lock_delay = 300, 365 .iddq_reg = PLLC_MISC, 366 .iddq_bit_idx = PLLC_IDDQ_BIT, 367 .max_p = PLLXC_SW_MAX_P, 368 .dyn_ramp_reg = PLLC_MISC2, 369 .stepa_shift = 17, 370 .stepb_shift = 9, 371 .pdiv_tohw = pllxc_p, 372 .div_nmp = &pllxc_nmp, 373 }; 374 375 static struct div_nmp pllcx_nmp = { 376 .divm_shift = 0, 377 .divm_width = 2, 378 .divn_shift = 8, 379 .divn_width = 8, 380 .divp_shift = 20, 381 .divp_width = 3, 382 }; 383 384 static struct pdiv_map pllc_p[] = { 385 { .pdiv = 1, .hw_val = 0 }, 386 { .pdiv = 2, .hw_val = 1 }, 387 { .pdiv = 4, .hw_val = 3 }, 388 { .pdiv = 8, .hw_val = 5 }, 389 { .pdiv = 16, .hw_val = 7 }, 390 { .pdiv = 0, .hw_val = 0 }, 391 }; 392 393 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 394 {12000000, 600000000, 100, 0, 2}, 395 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 396 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 397 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 398 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 399 {0, 0, 0, 0, 0, 0}, 400 }; 401 402 static struct tegra_clk_pll_params pll_c2_params = { 403 .input_min = 12000000, 404 .input_max = 48000000, 405 .cf_min = 12000000, 406 .cf_max = 19200000, 407 .vco_min = 600000000, 408 .vco_max = 1200000000, 409 .base_reg = PLLC2_BASE, 410 .misc_reg = PLLC2_MISC, 411 .lock_mask = PLL_BASE_LOCK, 412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 413 .lock_delay = 300, 414 .pdiv_tohw = pllc_p, 415 .div_nmp = &pllcx_nmp, 416 .max_p = 7, 417 .ext_misc_reg[0] = 0x4f0, 418 .ext_misc_reg[1] = 0x4f4, 419 .ext_misc_reg[2] = 0x4f8, 420 }; 421 422 static struct tegra_clk_pll_params pll_c3_params = { 423 .input_min = 12000000, 424 .input_max = 48000000, 425 .cf_min = 12000000, 426 .cf_max = 19200000, 427 .vco_min = 600000000, 428 .vco_max = 1200000000, 429 .base_reg = PLLC3_BASE, 430 .misc_reg = PLLC3_MISC, 431 .lock_mask = PLL_BASE_LOCK, 432 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 433 .lock_delay = 300, 434 .pdiv_tohw = pllc_p, 435 .div_nmp = &pllcx_nmp, 436 .max_p = 7, 437 .ext_misc_reg[0] = 0x504, 438 .ext_misc_reg[1] = 0x508, 439 .ext_misc_reg[2] = 0x50c, 440 }; 441 442 static struct div_nmp pllm_nmp = { 443 .divm_shift = 0, 444 .divm_width = 8, 445 .override_divm_shift = 0, 446 .divn_shift = 8, 447 .divn_width = 8, 448 .override_divn_shift = 8, 449 .divp_shift = 20, 450 .divp_width = 1, 451 .override_divp_shift = 27, 452 }; 453 454 static struct pdiv_map pllm_p[] = { 455 { .pdiv = 1, .hw_val = 0 }, 456 { .pdiv = 2, .hw_val = 1 }, 457 { .pdiv = 0, .hw_val = 0 }, 458 }; 459 460 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 461 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ 462 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ 463 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ 464 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ 465 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 466 {0, 0, 0, 0, 0, 0}, 467 }; 468 469 static struct tegra_clk_pll_params pll_m_params = { 470 .input_min = 12000000, 471 .input_max = 500000000, 472 .cf_min = 12000000, 473 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 474 .vco_min = 400000000, 475 .vco_max = 1066000000, 476 .base_reg = PLLM_BASE, 477 .misc_reg = PLLM_MISC, 478 .lock_mask = PLL_BASE_LOCK, 479 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 480 .lock_delay = 300, 481 .max_p = 2, 482 .pdiv_tohw = pllm_p, 483 .div_nmp = &pllm_nmp, 484 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 485 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 486 }; 487 488 static struct div_nmp pllp_nmp = { 489 .divm_shift = 0, 490 .divm_width = 5, 491 .divn_shift = 8, 492 .divn_width = 10, 493 .divp_shift = 20, 494 .divp_width = 3, 495 }; 496 497 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 498 {12000000, 216000000, 432, 12, 1, 8}, 499 {13000000, 216000000, 432, 13, 1, 8}, 500 {16800000, 216000000, 360, 14, 1, 8}, 501 {19200000, 216000000, 360, 16, 1, 8}, 502 {26000000, 216000000, 432, 26, 1, 8}, 503 {0, 0, 0, 0, 0, 0}, 504 }; 505 506 static struct tegra_clk_pll_params pll_p_params = { 507 .input_min = 2000000, 508 .input_max = 31000000, 509 .cf_min = 1000000, 510 .cf_max = 6000000, 511 .vco_min = 200000000, 512 .vco_max = 700000000, 513 .base_reg = PLLP_BASE, 514 .misc_reg = PLLP_MISC, 515 .lock_mask = PLL_BASE_LOCK, 516 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 517 .lock_delay = 300, 518 .div_nmp = &pllp_nmp, 519 }; 520 521 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 522 {9600000, 282240000, 147, 5, 0, 4}, 523 {9600000, 368640000, 192, 5, 0, 4}, 524 {9600000, 240000000, 200, 8, 0, 8}, 525 526 {28800000, 282240000, 245, 25, 0, 8}, 527 {28800000, 368640000, 320, 25, 0, 8}, 528 {28800000, 240000000, 200, 24, 0, 8}, 529 {0, 0, 0, 0, 0, 0}, 530 }; 531 532 533 static struct tegra_clk_pll_params pll_a_params = { 534 .input_min = 2000000, 535 .input_max = 31000000, 536 .cf_min = 1000000, 537 .cf_max = 6000000, 538 .vco_min = 200000000, 539 .vco_max = 700000000, 540 .base_reg = PLLA_BASE, 541 .misc_reg = PLLA_MISC, 542 .lock_mask = PLL_BASE_LOCK, 543 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 544 .lock_delay = 300, 545 .div_nmp = &pllp_nmp, 546 }; 547 548 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 549 {12000000, 216000000, 864, 12, 2, 12}, 550 {13000000, 216000000, 864, 13, 2, 12}, 551 {16800000, 216000000, 720, 14, 2, 12}, 552 {19200000, 216000000, 720, 16, 2, 12}, 553 {26000000, 216000000, 864, 26, 2, 12}, 554 555 {12000000, 594000000, 594, 12, 0, 12}, 556 {13000000, 594000000, 594, 13, 0, 12}, 557 {16800000, 594000000, 495, 14, 0, 12}, 558 {19200000, 594000000, 495, 16, 0, 12}, 559 {26000000, 594000000, 594, 26, 0, 12}, 560 561 {12000000, 1000000000, 1000, 12, 0, 12}, 562 {13000000, 1000000000, 1000, 13, 0, 12}, 563 {19200000, 1000000000, 625, 12, 0, 12}, 564 {26000000, 1000000000, 1000, 26, 0, 12}, 565 566 {0, 0, 0, 0, 0, 0}, 567 }; 568 569 static struct tegra_clk_pll_params pll_d_params = { 570 .input_min = 2000000, 571 .input_max = 40000000, 572 .cf_min = 1000000, 573 .cf_max = 6000000, 574 .vco_min = 500000000, 575 .vco_max = 1000000000, 576 .base_reg = PLLD_BASE, 577 .misc_reg = PLLD_MISC, 578 .lock_mask = PLL_BASE_LOCK, 579 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 580 .lock_delay = 1000, 581 .div_nmp = &pllp_nmp, 582 }; 583 584 static struct tegra_clk_pll_params pll_d2_params = { 585 .input_min = 2000000, 586 .input_max = 40000000, 587 .cf_min = 1000000, 588 .cf_max = 6000000, 589 .vco_min = 500000000, 590 .vco_max = 1000000000, 591 .base_reg = PLLD2_BASE, 592 .misc_reg = PLLD2_MISC, 593 .lock_mask = PLL_BASE_LOCK, 594 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 595 .lock_delay = 1000, 596 .div_nmp = &pllp_nmp, 597 }; 598 599 static struct pdiv_map pllu_p[] = { 600 { .pdiv = 1, .hw_val = 1 }, 601 { .pdiv = 2, .hw_val = 0 }, 602 { .pdiv = 0, .hw_val = 0 }, 603 }; 604 605 static struct div_nmp pllu_nmp = { 606 .divm_shift = 0, 607 .divm_width = 5, 608 .divn_shift = 8, 609 .divn_width = 10, 610 .divp_shift = 20, 611 .divp_width = 1, 612 }; 613 614 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 615 {12000000, 480000000, 960, 12, 0, 12}, 616 {13000000, 480000000, 960, 13, 0, 12}, 617 {16800000, 480000000, 400, 7, 0, 5}, 618 {19200000, 480000000, 200, 4, 0, 3}, 619 {26000000, 480000000, 960, 26, 0, 12}, 620 {0, 0, 0, 0, 0, 0}, 621 }; 622 623 static struct tegra_clk_pll_params pll_u_params = { 624 .input_min = 2000000, 625 .input_max = 40000000, 626 .cf_min = 1000000, 627 .cf_max = 6000000, 628 .vco_min = 480000000, 629 .vco_max = 960000000, 630 .base_reg = PLLU_BASE, 631 .misc_reg = PLLU_MISC, 632 .lock_mask = PLL_BASE_LOCK, 633 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 634 .lock_delay = 1000, 635 .pdiv_tohw = pllu_p, 636 .div_nmp = &pllu_nmp, 637 }; 638 639 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 640 /* 1 GHz */ 641 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 642 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 643 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 644 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 645 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 646 647 {0, 0, 0, 0, 0, 0}, 648 }; 649 650 static struct tegra_clk_pll_params pll_x_params = { 651 .input_min = 12000000, 652 .input_max = 800000000, 653 .cf_min = 12000000, 654 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 655 .vco_min = 700000000, 656 .vco_max = 2400000000U, 657 .base_reg = PLLX_BASE, 658 .misc_reg = PLLX_MISC, 659 .lock_mask = PLL_BASE_LOCK, 660 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 661 .lock_delay = 300, 662 .iddq_reg = PLLX_MISC3, 663 .iddq_bit_idx = PLLX_IDDQ_BIT, 664 .max_p = PLLXC_SW_MAX_P, 665 .dyn_ramp_reg = PLLX_MISC2, 666 .stepa_shift = 16, 667 .stepb_shift = 24, 668 .pdiv_tohw = pllxc_p, 669 .div_nmp = &pllxc_nmp, 670 }; 671 672 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 673 /* PLLE special case: use cpcon field to store cml divider value */ 674 {336000000, 100000000, 100, 21, 16, 11}, 675 {312000000, 100000000, 200, 26, 24, 13}, 676 {0, 0, 0, 0, 0, 0}, 677 }; 678 679 static struct div_nmp plle_nmp = { 680 .divm_shift = 0, 681 .divm_width = 8, 682 .divn_shift = 8, 683 .divn_width = 8, 684 .divp_shift = 24, 685 .divp_width = 4, 686 }; 687 688 static struct tegra_clk_pll_params pll_e_params = { 689 .input_min = 12000000, 690 .input_max = 1000000000, 691 .cf_min = 12000000, 692 .cf_max = 75000000, 693 .vco_min = 1600000000, 694 .vco_max = 2400000000U, 695 .base_reg = PLLE_BASE, 696 .misc_reg = PLLE_MISC, 697 .aux_reg = PLLE_AUX, 698 .lock_mask = PLLE_MISC_LOCK, 699 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 700 .lock_delay = 300, 701 .div_nmp = &plle_nmp, 702 }; 703 704 static struct div_nmp pllre_nmp = { 705 .divm_shift = 0, 706 .divm_width = 8, 707 .divn_shift = 8, 708 .divn_width = 8, 709 .divp_shift = 16, 710 .divp_width = 4, 711 }; 712 713 static struct tegra_clk_pll_params pll_re_vco_params = { 714 .input_min = 12000000, 715 .input_max = 1000000000, 716 .cf_min = 12000000, 717 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 718 .vco_min = 300000000, 719 .vco_max = 600000000, 720 .base_reg = PLLRE_BASE, 721 .misc_reg = PLLRE_MISC, 722 .lock_mask = PLLRE_MISC_LOCK, 723 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 724 .lock_delay = 300, 725 .iddq_reg = PLLRE_MISC, 726 .iddq_bit_idx = PLLRE_IDDQ_BIT, 727 .div_nmp = &pllre_nmp, 728 }; 729 730 /* Peripheral clock registers */ 731 732 static struct tegra_clk_periph_regs periph_l_regs = { 733 .enb_reg = CLK_OUT_ENB_L, 734 .enb_set_reg = CLK_OUT_ENB_SET_L, 735 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 736 .rst_reg = RST_DEVICES_L, 737 .rst_set_reg = RST_DEVICES_SET_L, 738 .rst_clr_reg = RST_DEVICES_CLR_L, 739 }; 740 741 static struct tegra_clk_periph_regs periph_h_regs = { 742 .enb_reg = CLK_OUT_ENB_H, 743 .enb_set_reg = CLK_OUT_ENB_SET_H, 744 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 745 .rst_reg = RST_DEVICES_H, 746 .rst_set_reg = RST_DEVICES_SET_H, 747 .rst_clr_reg = RST_DEVICES_CLR_H, 748 }; 749 750 static struct tegra_clk_periph_regs periph_u_regs = { 751 .enb_reg = CLK_OUT_ENB_U, 752 .enb_set_reg = CLK_OUT_ENB_SET_U, 753 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 754 .rst_reg = RST_DEVICES_U, 755 .rst_set_reg = RST_DEVICES_SET_U, 756 .rst_clr_reg = RST_DEVICES_CLR_U, 757 }; 758 759 static struct tegra_clk_periph_regs periph_v_regs = { 760 .enb_reg = CLK_OUT_ENB_V, 761 .enb_set_reg = CLK_OUT_ENB_SET_V, 762 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 763 .rst_reg = RST_DEVICES_V, 764 .rst_set_reg = RST_DEVICES_SET_V, 765 .rst_clr_reg = RST_DEVICES_CLR_V, 766 }; 767 768 static struct tegra_clk_periph_regs periph_w_regs = { 769 .enb_reg = CLK_OUT_ENB_W, 770 .enb_set_reg = CLK_OUT_ENB_SET_W, 771 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 772 .rst_reg = RST_DEVICES_W, 773 .rst_set_reg = RST_DEVICES_SET_W, 774 .rst_clr_reg = RST_DEVICES_CLR_W, 775 }; 776 777 /* possible OSC frequencies in Hz */ 778 static unsigned long tegra114_input_freq[] = { 779 [0] = 13000000, 780 [1] = 16800000, 781 [4] = 19200000, 782 [5] = 38400000, 783 [8] = 12000000, 784 [9] = 48000000, 785 [12] = 260000000, 786 }; 787 788 #define MASK(x) (BIT(x) - 1) 789 790 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 791 _clk_num, _regs, _gate_flags, _clk_id) \ 792 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 793 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 794 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 795 _parents##_idx, 0) 796 797 #define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 798 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 799 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 800 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 801 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 802 _parents##_idx, flags) 803 804 #define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 805 _clk_num, _regs, _gate_flags, _clk_id) \ 806 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 807 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \ 808 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 809 _parents##_idx, 0) 810 811 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 812 _clk_num, _regs, _gate_flags, _clk_id) \ 813 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 814 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 815 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 816 _clk_id, _parents##_idx, 0) 817 818 #define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 819 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 820 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 821 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 822 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 823 _clk_id, _parents##_idx, flags) 824 825 #define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\ 826 _clk_num, _regs, _gate_flags, _clk_id) \ 827 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 828 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 829 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 830 _clk_id, _parents##_idx, 0) 831 832 #define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 833 _clk_num, _regs, _clk_id) \ 834 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 835 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\ 836 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \ 837 _parents##_idx, 0) 838 839 #define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\ 840 _clk_num, _regs, _clk_id) \ 841 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 842 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \ 843 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0) 844 845 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 846 _mux_shift, _mux_mask, _clk_num, _regs, \ 847 _gate_flags, _clk_id) \ 848 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 849 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \ 850 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 851 _clk_id, _parents##_idx, 0) 852 853 #define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \ 854 _clk_num, _regs, _gate_flags, _clk_id) \ 855 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \ 856 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 857 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 858 _clk_id, _parents##_idx, 0) 859 860 #define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\ 861 _regs, _gate_flags, _clk_id) \ 862 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \ 863 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \ 864 periph_clk_enb_refcnt, _gate_flags , _clk_id, \ 865 mux_d_audio_clk_idx, 0) 866 867 enum tegra114_clk { 868 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12, 869 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19, 870 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27, 871 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40, 872 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48, 873 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56, 874 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65, 875 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73, 876 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80, 877 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91, 878 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102, 879 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1, 880 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x, 881 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120, 882 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128, 883 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148, 884 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192, 885 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k, 886 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2, 887 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3, 888 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0, 889 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0, 890 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync, 891 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0, 892 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3, 893 blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src, 894 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp, 895 dfll_ref = 264, dfll_soc, 896 897 /* Mux clocks */ 898 899 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux, 900 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux, 901 dsib_mux, clk_max, 902 }; 903 904 struct utmi_clk_param { 905 /* Oscillator Frequency in KHz */ 906 u32 osc_frequency; 907 /* UTMIP PLL Enable Delay Count */ 908 u8 enable_delay_count; 909 /* UTMIP PLL Stable count */ 910 u8 stable_count; 911 /* UTMIP PLL Active delay count */ 912 u8 active_delay_count; 913 /* UTMIP PLL Xtal frequency count */ 914 u8 xtal_freq_count; 915 }; 916 917 static const struct utmi_clk_param utmi_parameters[] = { 918 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 919 .stable_count = 0x33, .active_delay_count = 0x05, 920 .xtal_freq_count = 0x7F}, 921 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 922 .stable_count = 0x4B, .active_delay_count = 0x06, 923 .xtal_freq_count = 0xBB}, 924 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 925 .stable_count = 0x2F, .active_delay_count = 0x04, 926 .xtal_freq_count = 0x76}, 927 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 928 .stable_count = 0x66, .active_delay_count = 0x09, 929 .xtal_freq_count = 0xFE}, 930 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 931 .stable_count = 0x41, .active_delay_count = 0x0A, 932 .xtal_freq_count = 0xA4}, 933 }; 934 935 /* peripheral mux definitions */ 936 937 #define MUX_I2S_SPDIF(_id) \ 938 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 939 #_id, "pll_p",\ 940 "clk_m"}; 941 MUX_I2S_SPDIF(audio0) 942 MUX_I2S_SPDIF(audio1) 943 MUX_I2S_SPDIF(audio2) 944 MUX_I2S_SPDIF(audio3) 945 MUX_I2S_SPDIF(audio4) 946 MUX_I2S_SPDIF(audio) 947 948 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 949 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 950 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 951 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 952 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 953 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 954 955 static const char *mux_pllp_pllc_pllm_clkm[] = { 956 "pll_p", "pll_c", "pll_m", "clk_m" 957 }; 958 #define mux_pllp_pllc_pllm_clkm_idx NULL 959 960 static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 961 #define mux_pllp_pllc_pllm_idx NULL 962 963 static const char *mux_pllp_pllc_clk32_clkm[] = { 964 "pll_p", "pll_c", "clk_32k", "clk_m" 965 }; 966 #define mux_pllp_pllc_clk32_clkm_idx NULL 967 968 static const char *mux_plla_pllc_pllp_clkm[] = { 969 "pll_a_out0", "pll_c", "pll_p", "clk_m" 970 }; 971 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 972 973 static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 974 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 975 }; 976 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 977 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 978 }; 979 980 static const char *mux_pllp_clkm[] = { 981 "pll_p", "clk_m" 982 }; 983 static u32 mux_pllp_clkm_idx[] = { 984 [0] = 0, [1] = 3, 985 }; 986 987 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 988 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 989 }; 990 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 991 992 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 993 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 994 "pll_d2_out0", "clk_m" 995 }; 996 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 997 998 static const char *mux_pllm_pllc_pllp_plla[] = { 999 "pll_m", "pll_c", "pll_p", "pll_a_out0" 1000 }; 1001 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 1002 1003 static const char *mux_pllp_pllc_clkm[] = { 1004 "pll_p", "pll_c", "pll_m" 1005 }; 1006 static u32 mux_pllp_pllc_clkm_idx[] = { 1007 [0] = 0, [1] = 1, [2] = 3, 1008 }; 1009 1010 static const char *mux_pllp_pllc_clkm_clk32[] = { 1011 "pll_p", "pll_c", "clk_m", "clk_32k" 1012 }; 1013 #define mux_pllp_pllc_clkm_clk32_idx NULL 1014 1015 static const char *mux_plla_clk32_pllp_clkm_plle[] = { 1016 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 1017 }; 1018 #define mux_plla_clk32_pllp_clkm_plle_idx NULL 1019 1020 static const char *mux_clkm_pllp_pllc_pllre[] = { 1021 "clk_m", "pll_p", "pll_c", "pll_re_out" 1022 }; 1023 static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 1024 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 1025 }; 1026 1027 static const char *mux_clkm_48M_pllp_480M[] = { 1028 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 1029 }; 1030 #define mux_clkm_48M_pllp_480M_idx NULL 1031 1032 static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 1033 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 1034 }; 1035 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 1036 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 1037 }; 1038 1039 static const char *mux_plld_out0_plld2_out0[] = { 1040 "pll_d_out0", "pll_d2_out0", 1041 }; 1042 #define mux_plld_out0_plld2_out0_idx NULL 1043 1044 static const char *mux_d_audio_clk[] = { 1045 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 1046 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1047 }; 1048 static u32 mux_d_audio_clk_idx[] = { 1049 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 1050 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 1051 }; 1052 1053 static const char *mux_pllmcp_clkm[] = { 1054 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 1055 }; 1056 1057 static const struct clk_div_table pll_re_div_table[] = { 1058 { .val = 0, .div = 1 }, 1059 { .val = 1, .div = 2 }, 1060 { .val = 2, .div = 3 }, 1061 { .val = 3, .div = 4 }, 1062 { .val = 4, .div = 5 }, 1063 { .val = 5, .div = 6 }, 1064 { .val = 0, .div = 0 }, 1065 }; 1066 1067 static struct clk *clks[clk_max]; 1068 static struct clk_onecell_data clk_data; 1069 1070 static unsigned long osc_freq; 1071 static unsigned long pll_ref_freq; 1072 1073 static int __init tegra114_osc_clk_init(void __iomem *clk_base) 1074 { 1075 struct clk *clk; 1076 u32 val, pll_ref_div; 1077 1078 val = readl_relaxed(clk_base + OSC_CTRL); 1079 1080 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; 1081 if (!osc_freq) { 1082 WARN_ON(1); 1083 return -EINVAL; 1084 } 1085 1086 /* clk_m */ 1087 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1088 osc_freq); 1089 clk_register_clkdev(clk, "clk_m", NULL); 1090 clks[clk_m] = clk; 1091 1092 /* pll_ref */ 1093 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 1094 pll_ref_div = 1 << val; 1095 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1096 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1097 clk_register_clkdev(clk, "pll_ref", NULL); 1098 clks[pll_ref] = clk; 1099 1100 pll_ref_freq = osc_freq / pll_ref_div; 1101 1102 return 0; 1103 } 1104 1105 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 1106 { 1107 struct clk *clk; 1108 1109 /* clk_32k */ 1110 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1111 32768); 1112 clk_register_clkdev(clk, "clk_32k", NULL); 1113 clks[clk_32k] = clk; 1114 1115 /* clk_m_div2 */ 1116 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1117 CLK_SET_RATE_PARENT, 1, 2); 1118 clk_register_clkdev(clk, "clk_m_div2", NULL); 1119 clks[clk_m_div2] = clk; 1120 1121 /* clk_m_div4 */ 1122 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1123 CLK_SET_RATE_PARENT, 1, 4); 1124 clk_register_clkdev(clk, "clk_m_div4", NULL); 1125 clks[clk_m_div4] = clk; 1126 1127 } 1128 1129 static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 1130 { 1131 u32 reg; 1132 int i; 1133 1134 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1135 if (osc_freq == utmi_parameters[i].osc_frequency) 1136 break; 1137 } 1138 1139 if (i >= ARRAY_SIZE(utmi_parameters)) { 1140 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 1141 osc_freq); 1142 return; 1143 } 1144 1145 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 1146 1147 /* Program UTMIP PLL stable and active counts */ 1148 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 1149 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1150 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 1151 1152 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1153 1154 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 1155 active_delay_count); 1156 1157 /* Remove power downs from UTMIP PLL control bits */ 1158 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1159 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1160 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1161 1162 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 1163 1164 /* Program UTMIP PLL delay and oscillator frequency counts */ 1165 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1166 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1167 1168 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 1169 enable_delay_count); 1170 1171 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1172 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 1173 xtal_freq_count); 1174 1175 /* Remove power downs from UTMIP PLL control bits */ 1176 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1177 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1178 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1179 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1180 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1181 1182 /* Setup HW control of UTMIPLL */ 1183 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1184 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1185 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1186 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1187 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1188 1189 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1190 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1191 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1192 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1193 1194 udelay(1); 1195 1196 /* Setup SW override of UTMIPLL assuming USB2.0 1197 ports are assigned to USB2 */ 1198 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1199 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1200 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1201 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1202 1203 udelay(1); 1204 1205 /* Enable HW control UTMIPLL */ 1206 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1207 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1208 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1209 } 1210 1211 static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params) 1212 { 1213 pll_params->vco_min = 1214 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq; 1215 } 1216 1217 static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1218 void __iomem *clk_base) 1219 { 1220 u32 val; 1221 u32 step_a, step_b; 1222 1223 switch (pll_ref_freq) { 1224 case 12000000: 1225 case 13000000: 1226 case 26000000: 1227 step_a = 0x2B; 1228 step_b = 0x0B; 1229 break; 1230 case 16800000: 1231 step_a = 0x1A; 1232 step_b = 0x09; 1233 break; 1234 case 19200000: 1235 step_a = 0x12; 1236 step_b = 0x08; 1237 break; 1238 default: 1239 pr_err("%s: Unexpected reference rate %lu\n", 1240 __func__, pll_ref_freq); 1241 WARN_ON(1); 1242 return -EINVAL; 1243 } 1244 1245 val = step_a << pll_params->stepa_shift; 1246 val |= step_b << pll_params->stepb_shift; 1247 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1248 1249 return 0; 1250 } 1251 1252 static void __init _init_iddq(struct tegra_clk_pll_params *pll_params, 1253 void __iomem *clk_base) 1254 { 1255 u32 val, val_iddq; 1256 1257 val = readl_relaxed(clk_base + pll_params->base_reg); 1258 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1259 1260 if (val & BIT(30)) 1261 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1262 else { 1263 val_iddq |= BIT(pll_params->iddq_bit_idx); 1264 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1265 } 1266 } 1267 1268 static void __init tegra114_pll_init(void __iomem *clk_base, 1269 void __iomem *pmc) 1270 { 1271 u32 val; 1272 struct clk *clk; 1273 1274 /* PLLC */ 1275 _clip_vco_min(&pll_c_params); 1276 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1277 _init_iddq(&pll_c_params, clk_base); 1278 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1279 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1280 pll_c_freq_table, NULL); 1281 clk_register_clkdev(clk, "pll_c", NULL); 1282 clks[pll_c] = clk; 1283 1284 /* PLLC_OUT1 */ 1285 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1286 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1287 8, 8, 1, NULL); 1288 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1289 clk_base + PLLC_OUT, 1, 0, 1290 CLK_SET_RATE_PARENT, 0, NULL); 1291 clk_register_clkdev(clk, "pll_c_out1", NULL); 1292 clks[pll_c_out1] = clk; 1293 } 1294 1295 /* PLLC2 */ 1296 _clip_vco_min(&pll_c2_params); 1297 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1298 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1299 pll_cx_freq_table, NULL); 1300 clk_register_clkdev(clk, "pll_c2", NULL); 1301 clks[pll_c2] = clk; 1302 1303 /* PLLC3 */ 1304 _clip_vco_min(&pll_c3_params); 1305 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1306 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1307 pll_cx_freq_table, NULL); 1308 clk_register_clkdev(clk, "pll_c3", NULL); 1309 clks[pll_c3] = clk; 1310 1311 /* PLLP */ 1312 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0, 1313 408000000, &pll_p_params, 1314 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 1315 pll_p_freq_table, NULL); 1316 clk_register_clkdev(clk, "pll_p", NULL); 1317 clks[pll_p] = clk; 1318 1319 /* PLLP_OUT1 */ 1320 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 1321 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1322 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1323 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 1324 clk_base + PLLP_OUTA, 1, 0, 1325 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1326 &pll_div_lock); 1327 clk_register_clkdev(clk, "pll_p_out1", NULL); 1328 clks[pll_p_out1] = clk; 1329 1330 /* PLLP_OUT2 */ 1331 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 1332 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1333 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24, 1334 8, 1, &pll_div_lock); 1335 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 1336 clk_base + PLLP_OUTA, 17, 16, 1337 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1338 &pll_div_lock); 1339 clk_register_clkdev(clk, "pll_p_out2", NULL); 1340 clks[pll_p_out2] = clk; 1341 1342 /* PLLP_OUT3 */ 1343 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 1344 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1345 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1346 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 1347 clk_base + PLLP_OUTB, 1, 0, 1348 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1349 &pll_div_lock); 1350 clk_register_clkdev(clk, "pll_p_out3", NULL); 1351 clks[pll_p_out3] = clk; 1352 1353 /* PLLP_OUT4 */ 1354 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 1355 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1356 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1357 &pll_div_lock); 1358 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 1359 clk_base + PLLP_OUTB, 17, 16, 1360 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1361 &pll_div_lock); 1362 clk_register_clkdev(clk, "pll_p_out4", NULL); 1363 clks[pll_p_out4] = clk; 1364 1365 /* PLLM */ 1366 _clip_vco_min(&pll_m_params); 1367 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1368 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1369 &pll_m_params, TEGRA_PLL_USE_LOCK, 1370 pll_m_freq_table, NULL); 1371 clk_register_clkdev(clk, "pll_m", NULL); 1372 clks[pll_m] = clk; 1373 1374 /* PLLM_OUT1 */ 1375 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1376 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1377 8, 8, 1, NULL); 1378 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1379 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1380 CLK_SET_RATE_PARENT, 0, NULL); 1381 clk_register_clkdev(clk, "pll_m_out1", NULL); 1382 clks[pll_m_out1] = clk; 1383 1384 /* PLLM_UD */ 1385 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1386 CLK_SET_RATE_PARENT, 1, 1); 1387 1388 /* PLLX */ 1389 _clip_vco_min(&pll_x_params); 1390 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) { 1391 _init_iddq(&pll_x_params, clk_base); 1392 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, 1393 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params, 1394 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL); 1395 clk_register_clkdev(clk, "pll_x", NULL); 1396 clks[pll_x] = clk; 1397 } 1398 1399 /* PLLX_OUT0 */ 1400 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 1401 CLK_SET_RATE_PARENT, 1, 2); 1402 clk_register_clkdev(clk, "pll_x_out0", NULL); 1403 clks[pll_x_out0] = clk; 1404 1405 /* PLLU */ 1406 val = readl(clk_base + pll_u_params.base_reg); 1407 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1408 writel(val, clk_base + pll_u_params.base_reg); 1409 1410 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1411 0, &pll_u_params, TEGRA_PLLU | 1412 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1413 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock); 1414 clk_register_clkdev(clk, "pll_u", NULL); 1415 clks[pll_u] = clk; 1416 1417 tegra114_utmi_param_configure(clk_base); 1418 1419 /* PLLU_480M */ 1420 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1421 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1422 22, 0, &pll_u_lock); 1423 clk_register_clkdev(clk, "pll_u_480M", NULL); 1424 clks[pll_u_480M] = clk; 1425 1426 /* PLLU_60M */ 1427 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1428 CLK_SET_RATE_PARENT, 1, 8); 1429 clk_register_clkdev(clk, "pll_u_60M", NULL); 1430 clks[pll_u_60M] = clk; 1431 1432 /* PLLU_48M */ 1433 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1434 CLK_SET_RATE_PARENT, 1, 10); 1435 clk_register_clkdev(clk, "pll_u_48M", NULL); 1436 clks[pll_u_48M] = clk; 1437 1438 /* PLLU_12M */ 1439 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1440 CLK_SET_RATE_PARENT, 1, 40); 1441 clk_register_clkdev(clk, "pll_u_12M", NULL); 1442 clks[pll_u_12M] = clk; 1443 1444 /* PLLD */ 1445 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1446 0, &pll_d_params, 1447 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1448 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock); 1449 clk_register_clkdev(clk, "pll_d", NULL); 1450 clks[pll_d] = clk; 1451 1452 /* PLLD_OUT0 */ 1453 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1454 CLK_SET_RATE_PARENT, 1, 2); 1455 clk_register_clkdev(clk, "pll_d_out0", NULL); 1456 clks[pll_d_out0] = clk; 1457 1458 /* PLLD2 */ 1459 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1460 0, &pll_d2_params, 1461 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1462 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock); 1463 clk_register_clkdev(clk, "pll_d2", NULL); 1464 clks[pll_d2] = clk; 1465 1466 /* PLLD2_OUT0 */ 1467 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1468 CLK_SET_RATE_PARENT, 1, 2); 1469 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1470 clks[pll_d2_out0] = clk; 1471 1472 /* PLLA */ 1473 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0, 1474 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1475 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1476 clk_register_clkdev(clk, "pll_a", NULL); 1477 clks[pll_a] = clk; 1478 1479 /* PLLA_OUT0 */ 1480 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1481 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1482 8, 8, 1, NULL); 1483 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1484 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1485 CLK_SET_RATE_PARENT, 0, NULL); 1486 clk_register_clkdev(clk, "pll_a_out0", NULL); 1487 clks[pll_a_out0] = clk; 1488 1489 /* PLLRE */ 1490 _clip_vco_min(&pll_re_vco_params); 1491 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1492 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1493 NULL, &pll_re_lock, pll_ref_freq); 1494 clk_register_clkdev(clk, "pll_re_vco", NULL); 1495 clks[pll_re_vco] = clk; 1496 1497 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1498 clk_base + PLLRE_BASE, 16, 4, 0, 1499 pll_re_div_table, &pll_re_lock); 1500 clk_register_clkdev(clk, "pll_re_out", NULL); 1501 clks[pll_re_out] = clk; 1502 1503 /* PLLE */ 1504 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1505 clk_base, 0, 100000000, &pll_e_params, 1506 pll_e_freq_table, NULL); 1507 clk_register_clkdev(clk, "pll_e_out0", NULL); 1508 clks[pll_e_out0] = clk; 1509 } 1510 1511 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1512 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1513 }; 1514 1515 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1516 "clk_m_div4", "extern1", 1517 }; 1518 1519 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1520 "clk_m_div4", "extern2", 1521 }; 1522 1523 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1524 "clk_m_div4", "extern3", 1525 }; 1526 1527 static void __init tegra114_audio_clk_init(void __iomem *clk_base) 1528 { 1529 struct clk *clk; 1530 1531 /* spdif_in_sync */ 1532 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1533 24000000); 1534 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1535 clks[spdif_in_sync] = clk; 1536 1537 /* i2s0_sync */ 1538 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1539 clk_register_clkdev(clk, "i2s0_sync", NULL); 1540 clks[i2s0_sync] = clk; 1541 1542 /* i2s1_sync */ 1543 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1544 clk_register_clkdev(clk, "i2s1_sync", NULL); 1545 clks[i2s1_sync] = clk; 1546 1547 /* i2s2_sync */ 1548 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1549 clk_register_clkdev(clk, "i2s2_sync", NULL); 1550 clks[i2s2_sync] = clk; 1551 1552 /* i2s3_sync */ 1553 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1554 clk_register_clkdev(clk, "i2s3_sync", NULL); 1555 clks[i2s3_sync] = clk; 1556 1557 /* i2s4_sync */ 1558 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1559 clk_register_clkdev(clk, "i2s4_sync", NULL); 1560 clks[i2s4_sync] = clk; 1561 1562 /* vimclk_sync */ 1563 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1564 clk_register_clkdev(clk, "vimclk_sync", NULL); 1565 clks[vimclk_sync] = clk; 1566 1567 /* audio0 */ 1568 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1569 ARRAY_SIZE(mux_audio_sync_clk), 1570 CLK_SET_RATE_NO_REPARENT, 1571 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1572 NULL); 1573 clks[audio0_mux] = clk; 1574 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1575 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1576 CLK_GATE_SET_TO_DISABLE, NULL); 1577 clk_register_clkdev(clk, "audio0", NULL); 1578 clks[audio0] = clk; 1579 1580 /* audio1 */ 1581 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1582 ARRAY_SIZE(mux_audio_sync_clk), 1583 CLK_SET_RATE_NO_REPARENT, 1584 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1585 NULL); 1586 clks[audio1_mux] = clk; 1587 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1588 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1589 CLK_GATE_SET_TO_DISABLE, NULL); 1590 clk_register_clkdev(clk, "audio1", NULL); 1591 clks[audio1] = clk; 1592 1593 /* audio2 */ 1594 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1595 ARRAY_SIZE(mux_audio_sync_clk), 1596 CLK_SET_RATE_NO_REPARENT, 1597 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1598 NULL); 1599 clks[audio2_mux] = clk; 1600 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1601 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1602 CLK_GATE_SET_TO_DISABLE, NULL); 1603 clk_register_clkdev(clk, "audio2", NULL); 1604 clks[audio2] = clk; 1605 1606 /* audio3 */ 1607 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1608 ARRAY_SIZE(mux_audio_sync_clk), 1609 CLK_SET_RATE_NO_REPARENT, 1610 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1611 NULL); 1612 clks[audio3_mux] = clk; 1613 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1614 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1615 CLK_GATE_SET_TO_DISABLE, NULL); 1616 clk_register_clkdev(clk, "audio3", NULL); 1617 clks[audio3] = clk; 1618 1619 /* audio4 */ 1620 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1621 ARRAY_SIZE(mux_audio_sync_clk), 1622 CLK_SET_RATE_NO_REPARENT, 1623 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1624 NULL); 1625 clks[audio4_mux] = clk; 1626 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1627 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1628 CLK_GATE_SET_TO_DISABLE, NULL); 1629 clk_register_clkdev(clk, "audio4", NULL); 1630 clks[audio4] = clk; 1631 1632 /* spdif */ 1633 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1634 ARRAY_SIZE(mux_audio_sync_clk), 1635 CLK_SET_RATE_NO_REPARENT, 1636 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1637 NULL); 1638 clks[spdif_mux] = clk; 1639 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1640 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1641 CLK_GATE_SET_TO_DISABLE, NULL); 1642 clk_register_clkdev(clk, "spdif", NULL); 1643 clks[spdif] = clk; 1644 1645 /* audio0_2x */ 1646 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1647 CLK_SET_RATE_PARENT, 2, 1); 1648 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1649 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 1650 0, &clk_doubler_lock); 1651 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1652 TEGRA_PERIPH_NO_RESET, clk_base, 1653 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1654 periph_clk_enb_refcnt); 1655 clk_register_clkdev(clk, "audio0_2x", NULL); 1656 clks[audio0_2x] = clk; 1657 1658 /* audio1_2x */ 1659 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1660 CLK_SET_RATE_PARENT, 2, 1); 1661 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1662 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 1663 0, &clk_doubler_lock); 1664 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1665 TEGRA_PERIPH_NO_RESET, clk_base, 1666 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1667 periph_clk_enb_refcnt); 1668 clk_register_clkdev(clk, "audio1_2x", NULL); 1669 clks[audio1_2x] = clk; 1670 1671 /* audio2_2x */ 1672 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1673 CLK_SET_RATE_PARENT, 2, 1); 1674 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1675 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 1676 0, &clk_doubler_lock); 1677 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1678 TEGRA_PERIPH_NO_RESET, clk_base, 1679 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1680 periph_clk_enb_refcnt); 1681 clk_register_clkdev(clk, "audio2_2x", NULL); 1682 clks[audio2_2x] = clk; 1683 1684 /* audio3_2x */ 1685 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1686 CLK_SET_RATE_PARENT, 2, 1); 1687 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1688 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 1689 0, &clk_doubler_lock); 1690 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1691 TEGRA_PERIPH_NO_RESET, clk_base, 1692 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1693 periph_clk_enb_refcnt); 1694 clk_register_clkdev(clk, "audio3_2x", NULL); 1695 clks[audio3_2x] = clk; 1696 1697 /* audio4_2x */ 1698 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1699 CLK_SET_RATE_PARENT, 2, 1); 1700 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1701 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 1702 0, &clk_doubler_lock); 1703 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1704 TEGRA_PERIPH_NO_RESET, clk_base, 1705 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1706 periph_clk_enb_refcnt); 1707 clk_register_clkdev(clk, "audio4_2x", NULL); 1708 clks[audio4_2x] = clk; 1709 1710 /* spdif_2x */ 1711 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1712 CLK_SET_RATE_PARENT, 2, 1); 1713 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1714 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 1715 0, &clk_doubler_lock); 1716 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1717 TEGRA_PERIPH_NO_RESET, clk_base, 1718 CLK_SET_RATE_PARENT, 118, 1719 &periph_v_regs, periph_clk_enb_refcnt); 1720 clk_register_clkdev(clk, "spdif_2x", NULL); 1721 clks[spdif_2x] = clk; 1722 } 1723 1724 static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 1725 { 1726 struct clk *clk; 1727 1728 /* clk_out_1 */ 1729 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1730 ARRAY_SIZE(clk_out1_parents), 1731 CLK_SET_RATE_NO_REPARENT, 1732 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1733 &clk_out_lock); 1734 clks[clk_out_1_mux] = clk; 1735 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1736 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1737 &clk_out_lock); 1738 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1739 clks[clk_out_1] = clk; 1740 1741 /* clk_out_2 */ 1742 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1743 ARRAY_SIZE(clk_out2_parents), 1744 CLK_SET_RATE_NO_REPARENT, 1745 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1746 &clk_out_lock); 1747 clks[clk_out_2_mux] = clk; 1748 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1749 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1750 &clk_out_lock); 1751 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1752 clks[clk_out_2] = clk; 1753 1754 /* clk_out_3 */ 1755 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1756 ARRAY_SIZE(clk_out3_parents), 1757 CLK_SET_RATE_NO_REPARENT, 1758 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1759 &clk_out_lock); 1760 clks[clk_out_3_mux] = clk; 1761 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1762 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1763 &clk_out_lock); 1764 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1765 clks[clk_out_3] = clk; 1766 1767 /* blink */ 1768 /* clear the blink timer register to directly output clk_32k */ 1769 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1770 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1771 pmc_base + PMC_DPD_PADS_ORIDE, 1772 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1773 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1774 pmc_base + PMC_CTRL, 1775 PMC_CTRL_BLINK_ENB, 0, NULL); 1776 clk_register_clkdev(clk, "blink", NULL); 1777 clks[blink] = clk; 1778 1779 } 1780 1781 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1782 "pll_p", "pll_p_out2", "unused", 1783 "clk_32k", "pll_m_out1" }; 1784 1785 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1786 "pll_p", "pll_p_out4", "unused", 1787 "unused", "pll_x" }; 1788 1789 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1790 "pll_p", "pll_p_out4", "unused", 1791 "unused", "pll_x", "pll_x_out0" }; 1792 1793 static void __init tegra114_super_clk_init(void __iomem *clk_base) 1794 { 1795 struct clk *clk; 1796 1797 /* CCLKG */ 1798 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1799 ARRAY_SIZE(cclk_g_parents), 1800 CLK_SET_RATE_PARENT, 1801 clk_base + CCLKG_BURST_POLICY, 1802 0, 4, 0, 0, NULL); 1803 clk_register_clkdev(clk, "cclk_g", NULL); 1804 clks[cclk_g] = clk; 1805 1806 /* CCLKLP */ 1807 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1808 ARRAY_SIZE(cclk_lp_parents), 1809 CLK_SET_RATE_PARENT, 1810 clk_base + CCLKLP_BURST_POLICY, 1811 0, 4, 8, 9, NULL); 1812 clk_register_clkdev(clk, "cclk_lp", NULL); 1813 clks[cclk_lp] = clk; 1814 1815 /* SCLK */ 1816 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1817 ARRAY_SIZE(sclk_parents), 1818 CLK_SET_RATE_PARENT, 1819 clk_base + SCLK_BURST_POLICY, 1820 0, 4, 0, 0, NULL); 1821 clk_register_clkdev(clk, "sclk", NULL); 1822 clks[sclk] = clk; 1823 1824 /* HCLK */ 1825 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1826 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1827 &sysrate_lock); 1828 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | 1829 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1830 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1831 clk_register_clkdev(clk, "hclk", NULL); 1832 clks[hclk] = clk; 1833 1834 /* PCLK */ 1835 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1836 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1837 &sysrate_lock); 1838 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | 1839 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1840 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1841 clk_register_clkdev(clk, "pclk", NULL); 1842 clks[pclk] = clk; 1843 } 1844 1845 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1846 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1847 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1848 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1849 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1850 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1851 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1852 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1853 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm), 1854 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx), 1855 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx), 1856 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda), 1857 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x), 1858 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1859 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1860 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1861 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1862 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1863 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1864 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1865 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1866 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1867 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1868 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1869 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1870 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1871 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1872 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED), 1873 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1874 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace), 1875 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1876 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1877 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1878 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1), 1879 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2), 1880 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3), 1881 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4), 1882 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5), 1883 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1884 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1885 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1886 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1887 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d), 1888 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d), 1889 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1890 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1891 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1892 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc), 1893 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec), 1894 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1895 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1896 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab), 1897 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd), 1898 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile), 1899 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp), 1900 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp), 1901 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1902 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1903 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1904 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1905 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1906 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1907 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se), 1908 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED), 1909 TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_ref), 1910 TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_soc), 1911 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm), 1912 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src), 1913 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src), 1914 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src), 1915 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src), 1916 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src), 1917 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio), 1918 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0), 1919 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1), 1920 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2), 1921 }; 1922 1923 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1924 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1), 1925 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2), 1926 }; 1927 1928 static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1929 { 1930 struct tegra_periph_init_data *data; 1931 struct clk *clk; 1932 int i; 1933 u32 val; 1934 1935 /* apbdma */ 1936 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1937 0, 34, &periph_h_regs, 1938 periph_clk_enb_refcnt); 1939 clks[apbdma] = clk; 1940 1941 /* rtc */ 1942 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1943 TEGRA_PERIPH_ON_APB | 1944 TEGRA_PERIPH_NO_RESET, clk_base, 1945 0, 4, &periph_l_regs, 1946 periph_clk_enb_refcnt); 1947 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1948 clks[rtc] = clk; 1949 1950 /* kbc */ 1951 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1952 TEGRA_PERIPH_ON_APB | 1953 TEGRA_PERIPH_NO_RESET, clk_base, 1954 0, 36, &periph_h_regs, 1955 periph_clk_enb_refcnt); 1956 clks[kbc] = clk; 1957 1958 /* timer */ 1959 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 1960 0, 5, &periph_l_regs, 1961 periph_clk_enb_refcnt); 1962 clk_register_clkdev(clk, NULL, "timer"); 1963 clks[timer] = clk; 1964 1965 /* kfuse */ 1966 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1967 TEGRA_PERIPH_ON_APB, clk_base, 0, 40, 1968 &periph_h_regs, periph_clk_enb_refcnt); 1969 clks[kfuse] = clk; 1970 1971 /* fuse */ 1972 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1973 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1974 &periph_h_regs, periph_clk_enb_refcnt); 1975 clks[fuse] = clk; 1976 1977 /* fuse_burn */ 1978 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1979 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1980 &periph_h_regs, periph_clk_enb_refcnt); 1981 clks[fuse_burn] = clk; 1982 1983 /* apbif */ 1984 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 1985 TEGRA_PERIPH_ON_APB, clk_base, 0, 107, 1986 &periph_v_regs, periph_clk_enb_refcnt); 1987 clks[apbif] = clk; 1988 1989 /* hda2hdmi */ 1990 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1991 TEGRA_PERIPH_ON_APB, clk_base, 0, 128, 1992 &periph_w_regs, periph_clk_enb_refcnt); 1993 clks[hda2hdmi] = clk; 1994 1995 /* vcp */ 1996 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 1997 29, &periph_l_regs, 1998 periph_clk_enb_refcnt); 1999 clks[vcp] = clk; 2000 2001 /* bsea */ 2002 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 2003 0, 62, &periph_h_regs, 2004 periph_clk_enb_refcnt); 2005 clks[bsea] = clk; 2006 2007 /* bsev */ 2008 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 2009 0, 63, &periph_h_regs, 2010 periph_clk_enb_refcnt); 2011 clks[bsev] = clk; 2012 2013 /* mipi-cal */ 2014 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 2015 0, 56, &periph_h_regs, 2016 periph_clk_enb_refcnt); 2017 clks[mipi_cal] = clk; 2018 2019 /* usbd */ 2020 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 2021 0, 22, &periph_l_regs, 2022 periph_clk_enb_refcnt); 2023 clks[usbd] = clk; 2024 2025 /* usb2 */ 2026 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 2027 0, 58, &periph_h_regs, 2028 periph_clk_enb_refcnt); 2029 clks[usb2] = clk; 2030 2031 /* usb3 */ 2032 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 2033 0, 59, &periph_h_regs, 2034 periph_clk_enb_refcnt); 2035 clks[usb3] = clk; 2036 2037 /* csi */ 2038 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 2039 0, 52, &periph_h_regs, 2040 periph_clk_enb_refcnt); 2041 clks[csi] = clk; 2042 2043 /* isp */ 2044 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 2045 23, &periph_l_regs, 2046 periph_clk_enb_refcnt); 2047 clks[isp] = clk; 2048 2049 /* csus */ 2050 clk = tegra_clk_register_periph_gate("csus", "clk_m", 2051 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, 2052 &periph_u_regs, periph_clk_enb_refcnt); 2053 clks[csus] = clk; 2054 2055 /* dds */ 2056 clk = tegra_clk_register_periph_gate("dds", "clk_m", 2057 TEGRA_PERIPH_ON_APB, clk_base, 0, 150, 2058 &periph_w_regs, periph_clk_enb_refcnt); 2059 clks[dds] = clk; 2060 2061 /* dp2 */ 2062 clk = tegra_clk_register_periph_gate("dp2", "clk_m", 2063 TEGRA_PERIPH_ON_APB, clk_base, 0, 152, 2064 &periph_w_regs, periph_clk_enb_refcnt); 2065 clks[dp2] = clk; 2066 2067 /* dtv */ 2068 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 2069 TEGRA_PERIPH_ON_APB, clk_base, 0, 79, 2070 &periph_u_regs, periph_clk_enb_refcnt); 2071 clks[dtv] = clk; 2072 2073 /* dsia */ 2074 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2075 ARRAY_SIZE(mux_plld_out0_plld2_out0), 2076 CLK_SET_RATE_NO_REPARENT, 2077 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2078 clks[dsia_mux] = clk; 2079 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2080 0, 48, &periph_h_regs, 2081 periph_clk_enb_refcnt); 2082 clks[dsia] = clk; 2083 2084 /* dsib */ 2085 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2086 ARRAY_SIZE(mux_plld_out0_plld2_out0), 2087 CLK_SET_RATE_NO_REPARENT, 2088 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2089 clks[dsib_mux] = clk; 2090 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2091 0, 82, &periph_u_regs, 2092 periph_clk_enb_refcnt); 2093 clks[dsib] = clk; 2094 2095 /* xusb_hs_src */ 2096 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); 2097 val |= BIT(25); /* always select PLLU_60M */ 2098 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); 2099 2100 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 2101 1, 1); 2102 clks[xusb_hs_src] = clk; 2103 2104 /* xusb_host */ 2105 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, 2106 clk_base, 0, 89, &periph_u_regs, 2107 periph_clk_enb_refcnt); 2108 clks[xusb_host] = clk; 2109 2110 /* xusb_ss */ 2111 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, 2112 clk_base, 0, 156, &periph_w_regs, 2113 periph_clk_enb_refcnt); 2114 clks[xusb_host] = clk; 2115 2116 /* xusb_dev */ 2117 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, 2118 clk_base, 0, 95, &periph_u_regs, 2119 periph_clk_enb_refcnt); 2120 clks[xusb_dev] = clk; 2121 2122 /* emc */ 2123 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2124 ARRAY_SIZE(mux_pllmcp_clkm), 2125 CLK_SET_RATE_NO_REPARENT, 2126 clk_base + CLK_SOURCE_EMC, 2127 29, 3, 0, NULL); 2128 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2129 CLK_IGNORE_UNUSED, 57, &periph_h_regs, 2130 periph_clk_enb_refcnt); 2131 clks[emc] = clk; 2132 2133 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 2134 data = &tegra_periph_clk_list[i]; 2135 clk = tegra_clk_register_periph(data->name, data->parent_names, 2136 data->num_parents, &data->periph, 2137 clk_base, data->offset, data->flags); 2138 clks[data->clk_id] = clk; 2139 } 2140 2141 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 2142 data = &tegra_periph_nodiv_clk_list[i]; 2143 clk = tegra_clk_register_periph_nodiv(data->name, 2144 data->parent_names, data->num_parents, 2145 &data->periph, clk_base, data->offset); 2146 clks[data->clk_id] = clk; 2147 } 2148 } 2149 2150 /* Tegra114 CPU clock and reset control functions */ 2151 static void tegra114_wait_cpu_in_reset(u32 cpu) 2152 { 2153 unsigned int reg; 2154 2155 do { 2156 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 2157 cpu_relax(); 2158 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 2159 } 2160 static void tegra114_disable_cpu_clock(u32 cpu) 2161 { 2162 /* flow controller would take care in the power sequence. */ 2163 } 2164 2165 #ifdef CONFIG_PM_SLEEP 2166 static void tegra114_cpu_clock_suspend(void) 2167 { 2168 /* switch coresite to clk_m, save off original source */ 2169 tegra114_cpu_clk_sctx.clk_csite_src = 2170 readl(clk_base + CLK_SOURCE_CSITE); 2171 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 2172 2173 tegra114_cpu_clk_sctx.cclkg_burst = 2174 readl(clk_base + CCLKG_BURST_POLICY); 2175 tegra114_cpu_clk_sctx.cclkg_divider = 2176 readl(clk_base + CCLKG_BURST_POLICY + 4); 2177 } 2178 2179 static void tegra114_cpu_clock_resume(void) 2180 { 2181 writel(tegra114_cpu_clk_sctx.clk_csite_src, 2182 clk_base + CLK_SOURCE_CSITE); 2183 2184 writel(tegra114_cpu_clk_sctx.cclkg_burst, 2185 clk_base + CCLKG_BURST_POLICY); 2186 writel(tegra114_cpu_clk_sctx.cclkg_divider, 2187 clk_base + CCLKG_BURST_POLICY + 4); 2188 } 2189 #endif 2190 2191 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = { 2192 .wait_for_reset = tegra114_wait_cpu_in_reset, 2193 .disable_clock = tegra114_disable_cpu_clock, 2194 #ifdef CONFIG_PM_SLEEP 2195 .suspend = tegra114_cpu_clock_suspend, 2196 .resume = tegra114_cpu_clock_resume, 2197 #endif 2198 }; 2199 2200 static const struct of_device_id pmc_match[] __initconst = { 2201 { .compatible = "nvidia,tegra114-pmc" }, 2202 {}, 2203 }; 2204 2205 /* 2206 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 2207 * breaks 2208 */ 2209 static struct tegra_clk_init_table init_table[] __initdata = { 2210 {uarta, pll_p, 408000000, 0}, 2211 {uartb, pll_p, 408000000, 0}, 2212 {uartc, pll_p, 408000000, 0}, 2213 {uartd, pll_p, 408000000, 0}, 2214 {pll_a, clk_max, 564480000, 1}, 2215 {pll_a_out0, clk_max, 11289600, 1}, 2216 {extern1, pll_a_out0, 0, 1}, 2217 {clk_out_1_mux, extern1, 0, 1}, 2218 {clk_out_1, clk_max, 0, 1}, 2219 {i2s0, pll_a_out0, 11289600, 0}, 2220 {i2s1, pll_a_out0, 11289600, 0}, 2221 {i2s2, pll_a_out0, 11289600, 0}, 2222 {i2s3, pll_a_out0, 11289600, 0}, 2223 {i2s4, pll_a_out0, 11289600, 0}, 2224 {dfll_soc, pll_p, 51000000, 1}, 2225 {dfll_ref, pll_p, 51000000, 1}, 2226 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 2227 }; 2228 2229 static void __init tegra114_clock_apply_init_table(void) 2230 { 2231 tegra_init_from_table(init_table, clks, clk_max); 2232 } 2233 2234 2235 /** 2236 * tegra114_car_barrier - wait for pending writes to the CAR to complete 2237 * 2238 * Wait for any outstanding writes to the CAR MMIO space from this CPU 2239 * to complete before continuing execution. No return value. 2240 */ 2241 static void tegra114_car_barrier(void) 2242 { 2243 wmb(); /* probably unnecessary */ 2244 readl_relaxed(clk_base + CPU_FINETRIM_SELECT); 2245 } 2246 2247 /** 2248 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays 2249 * 2250 * When the CPU rail voltage is in the high-voltage range, use the 2251 * built-in hardwired clock propagation delays in the CPU clock 2252 * shaper. No return value. 2253 */ 2254 void tegra114_clock_tune_cpu_trimmers_high(void) 2255 { 2256 u32 select = 0; 2257 2258 /* Use hardwired rise->rise & fall->fall clock propagation delays */ 2259 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2260 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2261 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2262 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 2263 2264 tegra114_car_barrier(); 2265 } 2266 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high); 2267 2268 /** 2269 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays 2270 * 2271 * When the CPU rail voltage is in the low-voltage range, use the 2272 * extended clock propagation delays set by 2273 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to 2274 * maintain the input clock duty cycle that the FCPU subsystem 2275 * expects. No return value. 2276 */ 2277 void tegra114_clock_tune_cpu_trimmers_low(void) 2278 { 2279 u32 select = 0; 2280 2281 /* 2282 * Use software-specified rise->rise & fall->fall clock 2283 * propagation delays (from 2284 * tegra114_clock_tune_cpu_trimmers_init() 2285 */ 2286 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2287 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2288 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2289 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 2290 2291 tegra114_car_barrier(); 2292 } 2293 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low); 2294 2295 /** 2296 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays 2297 * 2298 * Program extended clock propagation delays into the FCPU clock 2299 * shaper and enable them. XXX Define the purpose - peak current 2300 * reduction? No return value. 2301 */ 2302 /* XXX Initial voltage rail state assumption issues? */ 2303 void tegra114_clock_tune_cpu_trimmers_init(void) 2304 { 2305 u32 dr = 0, r = 0; 2306 2307 /* Increment the rise->rise clock delay by four steps */ 2308 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK | 2309 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK | 2310 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK); 2311 writel_relaxed(r, clk_base + CPU_FINETRIM_R); 2312 2313 /* 2314 * Use the rise->rise clock propagation delay specified in the 2315 * r field 2316 */ 2317 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2318 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2319 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2320 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); 2321 2322 tegra114_clock_tune_cpu_trimmers_low(); 2323 } 2324 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); 2325 2326 /** 2327 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 2328 * 2329 * Assert the reset line of the DFLL's DVCO. No return value. 2330 */ 2331 void tegra114_clock_assert_dfll_dvco_reset(void) 2332 { 2333 u32 v; 2334 2335 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 2336 v |= (1 << DVFS_DFLL_RESET_SHIFT); 2337 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 2338 tegra114_car_barrier(); 2339 } 2340 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); 2341 2342 /** 2343 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 2344 * 2345 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 2346 * operate. No return value. 2347 */ 2348 void tegra114_clock_deassert_dfll_dvco_reset(void) 2349 { 2350 u32 v; 2351 2352 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 2353 v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 2354 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 2355 tegra114_car_barrier(); 2356 } 2357 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); 2358 2359 static void __init tegra114_clock_init(struct device_node *np) 2360 { 2361 struct device_node *node; 2362 int i; 2363 2364 clk_base = of_iomap(np, 0); 2365 if (!clk_base) { 2366 pr_err("ioremap tegra114 CAR failed\n"); 2367 return; 2368 } 2369 2370 node = of_find_matching_node(NULL, pmc_match); 2371 if (!node) { 2372 pr_err("Failed to find pmc node\n"); 2373 WARN_ON(1); 2374 return; 2375 } 2376 2377 pmc_base = of_iomap(node, 0); 2378 if (!pmc_base) { 2379 pr_err("Can't map pmc registers\n"); 2380 WARN_ON(1); 2381 return; 2382 } 2383 2384 if (tegra114_osc_clk_init(clk_base) < 0) 2385 return; 2386 2387 tegra114_fixed_clk_init(clk_base); 2388 tegra114_pll_init(clk_base, pmc_base); 2389 tegra114_periph_clk_init(clk_base); 2390 tegra114_audio_clk_init(clk_base); 2391 tegra114_pmc_clk_init(pmc_base); 2392 tegra114_super_clk_init(clk_base); 2393 2394 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2395 if (IS_ERR(clks[i])) { 2396 pr_err 2397 ("Tegra114 clk %d: register failed with %ld\n", 2398 i, PTR_ERR(clks[i])); 2399 } 2400 if (!clks[i]) 2401 clks[i] = ERR_PTR(-EINVAL); 2402 } 2403 2404 clk_data.clks = clks; 2405 clk_data.clk_num = ARRAY_SIZE(clks); 2406 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2407 2408 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 2409 2410 tegra_cpu_car_ops = &tegra114_cpu_car_ops; 2411 } 2412 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); 2413