1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/delay.h> 12 #include <linux/export.h> 13 #include <linux/clk/tegra.h> 14 15 #include "clk.h" 16 #include "clk-id.h" 17 18 #define CLK_SOURCE_I2S0 0x1d8 19 #define CLK_SOURCE_I2S1 0x100 20 #define CLK_SOURCE_I2S2 0x104 21 #define CLK_SOURCE_NDFLASH 0x160 22 #define CLK_SOURCE_I2S3 0x3bc 23 #define CLK_SOURCE_I2S4 0x3c0 24 #define CLK_SOURCE_SPDIF_OUT 0x108 25 #define CLK_SOURCE_SPDIF_IN 0x10c 26 #define CLK_SOURCE_PWM 0x110 27 #define CLK_SOURCE_ADX 0x638 28 #define CLK_SOURCE_ADX1 0x670 29 #define CLK_SOURCE_AMX 0x63c 30 #define CLK_SOURCE_AMX1 0x674 31 #define CLK_SOURCE_HDA 0x428 32 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4 33 #define CLK_SOURCE_SBC1 0x134 34 #define CLK_SOURCE_SBC2 0x118 35 #define CLK_SOURCE_SBC3 0x11c 36 #define CLK_SOURCE_SBC4 0x1b4 37 #define CLK_SOURCE_SBC5 0x3c8 38 #define CLK_SOURCE_SBC6 0x3cc 39 #define CLK_SOURCE_SATA_OOB 0x420 40 #define CLK_SOURCE_SATA 0x424 41 #define CLK_SOURCE_NDSPEED 0x3f8 42 #define CLK_SOURCE_VFIR 0x168 43 #define CLK_SOURCE_SDMMC1 0x150 44 #define CLK_SOURCE_SDMMC2 0x154 45 #define CLK_SOURCE_SDMMC3 0x1bc 46 #define CLK_SOURCE_SDMMC4 0x164 47 #define CLK_SOURCE_CVE 0x140 48 #define CLK_SOURCE_TVO 0x188 49 #define CLK_SOURCE_TVDAC 0x194 50 #define CLK_SOURCE_VDE 0x1c8 51 #define CLK_SOURCE_CSITE 0x1d4 52 #define CLK_SOURCE_LA 0x1f8 53 #define CLK_SOURCE_TRACE 0x634 54 #define CLK_SOURCE_OWR 0x1cc 55 #define CLK_SOURCE_NOR 0x1d0 56 #define CLK_SOURCE_MIPI 0x174 57 #define CLK_SOURCE_I2C1 0x124 58 #define CLK_SOURCE_I2C2 0x198 59 #define CLK_SOURCE_I2C3 0x1b8 60 #define CLK_SOURCE_I2C4 0x3c4 61 #define CLK_SOURCE_I2C5 0x128 62 #define CLK_SOURCE_I2C6 0x65c 63 #define CLK_SOURCE_UARTA 0x178 64 #define CLK_SOURCE_UARTB 0x17c 65 #define CLK_SOURCE_UARTC 0x1a0 66 #define CLK_SOURCE_UARTD 0x1c0 67 #define CLK_SOURCE_UARTE 0x1c4 68 #define CLK_SOURCE_3D 0x158 69 #define CLK_SOURCE_2D 0x15c 70 #define CLK_SOURCE_MPE 0x170 71 #define CLK_SOURCE_VI_SENSOR 0x1a8 72 #define CLK_SOURCE_VI 0x148 73 #define CLK_SOURCE_EPP 0x16c 74 #define CLK_SOURCE_MSENC 0x1f0 75 #define CLK_SOURCE_TSEC 0x1f4 76 #define CLK_SOURCE_HOST1X 0x180 77 #define CLK_SOURCE_HDMI 0x18c 78 #define CLK_SOURCE_DISP1 0x138 79 #define CLK_SOURCE_DISP2 0x13c 80 #define CLK_SOURCE_CILAB 0x614 81 #define CLK_SOURCE_CILCD 0x618 82 #define CLK_SOURCE_CILE 0x61c 83 #define CLK_SOURCE_DSIALP 0x620 84 #define CLK_SOURCE_DSIBLP 0x624 85 #define CLK_SOURCE_TSENSOR 0x3b8 86 #define CLK_SOURCE_D_AUDIO 0x3d0 87 #define CLK_SOURCE_DAM0 0x3d8 88 #define CLK_SOURCE_DAM1 0x3dc 89 #define CLK_SOURCE_DAM2 0x3e0 90 #define CLK_SOURCE_ACTMON 0x3e8 91 #define CLK_SOURCE_EXTERN1 0x3ec 92 #define CLK_SOURCE_EXTERN2 0x3f0 93 #define CLK_SOURCE_EXTERN3 0x3f4 94 #define CLK_SOURCE_I2CSLOW 0x3fc 95 #define CLK_SOURCE_SE 0x42c 96 #define CLK_SOURCE_MSELECT 0x3b4 97 #define CLK_SOURCE_DFLL_REF 0x62c 98 #define CLK_SOURCE_DFLL_SOC 0x630 99 #define CLK_SOURCE_SOC_THERM 0x644 100 #define CLK_SOURCE_XUSB_HOST_SRC 0x600 101 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604 102 #define CLK_SOURCE_XUSB_FS_SRC 0x608 103 #define CLK_SOURCE_XUSB_SS_SRC 0x610 104 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c 105 #define CLK_SOURCE_ISP 0x144 106 #define CLK_SOURCE_SOR0 0x414 107 #define CLK_SOURCE_DPAUX 0x418 108 #define CLK_SOURCE_ENTROPY 0x628 109 #define CLK_SOURCE_VI_SENSOR2 0x658 110 #define CLK_SOURCE_HDMI_AUDIO 0x668 111 #define CLK_SOURCE_VIC03 0x678 112 #define CLK_SOURCE_CLK72MHZ 0x66c 113 #define CLK_SOURCE_DBGAPB 0x718 114 #define CLK_SOURCE_NVENC 0x6a0 115 #define CLK_SOURCE_NVDEC 0x698 116 #define CLK_SOURCE_NVJPG 0x69c 117 #define CLK_SOURCE_APE 0x6c0 118 #define CLK_SOURCE_SDMMC_LEGACY 0x694 119 #define CLK_SOURCE_QSPI 0x6c4 120 #define CLK_SOURCE_VI_I2C 0x6c8 121 #define CLK_SOURCE_MIPIBIF 0x660 122 #define CLK_SOURCE_UARTAPE 0x710 123 #define CLK_SOURCE_TSECB 0x6d8 124 #define CLK_SOURCE_MAUD 0x6d4 125 #define CLK_SOURCE_USB2_HSIC_TRK 0x6cc 126 #define CLK_SOURCE_DMIC1 0x64c 127 #define CLK_SOURCE_DMIC2 0x650 128 #define CLK_SOURCE_DMIC3 0x6bc 129 130 #define MASK(x) (BIT(x) - 1) 131 132 #define MUX(_name, _parents, _offset, \ 133 _clk_num, _gate_flags, _clk_id) \ 134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 135 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 136 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\ 137 NULL) 138 139 #define MUX_FLAGS(_name, _parents, _offset,\ 140 _clk_num, _gate_flags, _clk_id, flags)\ 141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 142 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 143 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\ 144 NULL) 145 146 #define MUX8(_name, _parents, _offset, \ 147 _clk_num, _gate_flags, _clk_id) \ 148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 149 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 150 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\ 151 NULL) 152 153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ 154 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ 155 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 156 0, TEGRA_PERIPH_NO_GATE, _clk_id,\ 157 _parents##_idx, 0, _lock) 158 159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ 160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ 161 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 162 0, TEGRA_PERIPH_NO_GATE, _clk_id,\ 163 _parents##_idx, 0, NULL) 164 165 #define INT(_name, _parents, _offset, \ 166 _clk_num, _gate_flags, _clk_id) \ 167 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 168 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 169 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 170 _clk_id, _parents##_idx, 0, NULL) 171 172 #define INT_FLAGS(_name, _parents, _offset,\ 173 _clk_num, _gate_flags, _clk_id, flags)\ 174 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 175 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 176 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 177 _clk_id, _parents##_idx, flags, NULL) 178 179 #define INT8(_name, _parents, _offset,\ 180 _clk_num, _gate_flags, _clk_id) \ 181 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 182 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 183 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 184 _clk_id, _parents##_idx, 0, NULL) 185 186 #define UART(_name, _parents, _offset,\ 187 _clk_num, _clk_id) \ 188 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 189 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ 190 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ 191 _parents##_idx, 0, NULL) 192 193 #define UART8(_name, _parents, _offset,\ 194 _clk_num, _clk_id) \ 195 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 196 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ 197 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ 198 _parents##_idx, 0, NULL) 199 200 #define I2C(_name, _parents, _offset,\ 201 _clk_num, _clk_id) \ 202 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 203 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ 204 _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \ 205 _parents##_idx, 0, NULL) 206 207 #define XUSB(_name, _parents, _offset, \ 208 _clk_num, _gate_flags, _clk_id) \ 209 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ 210 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 211 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 212 _clk_id, _parents##_idx, 0, NULL) 213 214 #define AUDIO(_name, _offset, _clk_num,\ 215 _gate_flags, _clk_id) \ 216 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \ 217 _offset, 16, 0xE01F, 0, 0, 8, 1, \ 218 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \ 219 _clk_id, mux_d_audio_clk_idx, 0, NULL) 220 221 #define NODIV(_name, _parents, _offset, \ 222 _mux_shift, _mux_mask, _clk_num, \ 223 _gate_flags, _clk_id, _lock) \ 224 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 225 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\ 226 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\ 227 _clk_id, _parents##_idx, 0, _lock) 228 229 #define GATE(_name, _parent_name, \ 230 _clk_num, _gate_flags, _clk_id, _flags) \ 231 { \ 232 .name = _name, \ 233 .clk_id = _clk_id, \ 234 .p.parent_name = _parent_name, \ 235 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \ 236 _clk_num, _gate_flags, NULL, NULL), \ 237 .flags = _flags \ 238 } 239 240 #define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \ 241 { \ 242 .name = _name, \ 243 .clk_id = _clk_id, \ 244 .p.parent_name = _parent_name, \ 245 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \ 246 TEGRA_DIVIDER_ROUND_UP, 0, 0, \ 247 NULL, NULL), \ 248 .offset = _offset, \ 249 .flags = _flags, \ 250 } 251 252 #define PLLP_BASE 0xa0 253 #define PLLP_MISC 0xac 254 #define PLLP_MISC1 0x680 255 #define PLLP_OUTA 0xa4 256 #define PLLP_OUTB 0xa8 257 #define PLLP_OUTC 0x67c 258 259 #define PLL_BASE_LOCK BIT(27) 260 #define PLL_MISC_LOCK_ENABLE 18 261 262 static DEFINE_SPINLOCK(PLLP_OUTA_lock); 263 static DEFINE_SPINLOCK(PLLP_OUTB_lock); 264 static DEFINE_SPINLOCK(PLLP_OUTC_lock); 265 static DEFINE_SPINLOCK(sor0_lock); 266 267 #define MUX_I2S_SPDIF(_id) \ 268 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 269 #_id, "pll_p",\ 270 "clk_m"}; 271 MUX_I2S_SPDIF(audio0) 272 MUX_I2S_SPDIF(audio1) 273 MUX_I2S_SPDIF(audio2) 274 MUX_I2S_SPDIF(audio3) 275 MUX_I2S_SPDIF(audio4) 276 MUX_I2S_SPDIF(audio) 277 278 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 279 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 280 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 281 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 282 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 283 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 284 285 static const char *mux_pllp_pllc_pllm_clkm[] = { 286 "pll_p", "pll_c", "pll_m", "clk_m" 287 }; 288 #define mux_pllp_pllc_pllm_clkm_idx NULL 289 290 static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 291 #define mux_pllp_pllc_pllm_idx NULL 292 293 static const char *mux_pllp_pllc_clk32_clkm[] = { 294 "pll_p", "pll_c", "clk_32k", "clk_m" 295 }; 296 #define mux_pllp_pllc_clk32_clkm_idx NULL 297 298 static const char *mux_plla_pllc_pllp_clkm[] = { 299 "pll_a_out0", "pll_c", "pll_p", "clk_m" 300 }; 301 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 302 303 static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 304 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 305 }; 306 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 307 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 308 }; 309 310 static const char *mux_pllp_clkm[] = { 311 "pll_p", "clk_m" 312 }; 313 static u32 mux_pllp_clkm_idx[] = { 314 [0] = 0, [1] = 3, 315 }; 316 317 static const char *mux_pllp_clkm_2[] = { 318 "pll_p", "clk_m" 319 }; 320 static u32 mux_pllp_clkm_2_idx[] = { 321 [0] = 2, [1] = 6, 322 }; 323 324 static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = { 325 "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m" 326 }; 327 static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = { 328 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7, 329 }; 330 331 static const char * 332 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = { 333 "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m", 334 "pll_a_out0", "pll_c4_out0" 335 }; 336 static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = { 337 [0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7, 338 }; 339 340 static const char *mux_pllc_pllp_plla[] = { 341 "pll_c", "pll_p", "pll_a_out0" 342 }; 343 static u32 mux_pllc_pllp_plla_idx[] = { 344 [0] = 1, [1] = 2, [2] = 3, 345 }; 346 347 static const char *mux_clkm_pllc_pllp_plla[] = { 348 "clk_m", "pll_c", "pll_p", "pll_a_out0" 349 }; 350 #define mux_clkm_pllc_pllp_plla_idx NULL 351 352 static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = { 353 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m" 354 }; 355 static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = { 356 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, 357 }; 358 359 static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = { 360 "pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0", 361 }; 362 static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = { 363 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7, 364 }; 365 366 static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = { 367 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0", 368 }; 369 #define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \ 370 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx 371 372 static const char * 373 mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = { 374 "pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p", 375 "pll_c4_out2", "clk_m" 376 }; 377 #define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL 378 379 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 380 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 381 }; 382 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 383 384 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 385 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 386 "pll_d2_out0", "clk_m" 387 }; 388 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 389 390 static const char *mux_pllm_pllc_pllp_plla[] = { 391 "pll_m", "pll_c", "pll_p", "pll_a_out0" 392 }; 393 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 394 395 static const char *mux_pllp_pllc_clkm[] = { 396 "pll_p", "pll_c", "clk_m" 397 }; 398 static u32 mux_pllp_pllc_clkm_idx[] = { 399 [0] = 0, [1] = 1, [2] = 3, 400 }; 401 402 static const char *mux_pllp_pllc_clkm_1[] = { 403 "pll_p", "pll_c", "clk_m" 404 }; 405 static u32 mux_pllp_pllc_clkm_1_idx[] = { 406 [0] = 0, [1] = 2, [2] = 5, 407 }; 408 409 static const char *mux_pllp_pllc_plla_clkm[] = { 410 "pll_p", "pll_c", "pll_a_out0", "clk_m" 411 }; 412 static u32 mux_pllp_pllc_plla_clkm_idx[] = { 413 [0] = 0, [1] = 2, [2] = 4, [3] = 6, 414 }; 415 416 static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = { 417 "pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2" 418 }; 419 static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = { 420 [0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7, 421 }; 422 423 static const char * 424 mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = { 425 "pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1", 426 "clk_m", "pll_c4_out0" 427 }; 428 static u32 429 mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = { 430 [0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7, 431 }; 432 433 static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = { 434 "pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0" 435 }; 436 static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = { 437 [0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7, 438 }; 439 440 static const char *mux_pllp_pllc2_c_c3_clkm[] = { 441 "pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m" 442 }; 443 static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = { 444 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6, 445 }; 446 447 static const char *mux_pllp_clkm_clk32_plle[] = { 448 "pll_p", "clk_m", "clk_32k", "pll_e" 449 }; 450 static u32 mux_pllp_clkm_clk32_plle_idx[] = { 451 [0] = 0, [1] = 2, [2] = 4, [3] = 6, 452 }; 453 454 static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = { 455 "pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0" 456 }; 457 #define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL 458 459 static const char *mux_pllp_out3_clkm_pllp_pllc4[] = { 460 "pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1", 461 "pll_c4_out2" 462 }; 463 static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = { 464 [0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7, 465 }; 466 467 static const char *mux_clkm_pllp_pllre[] = { 468 "clk_m", "pll_p_out_xusb", "pll_re_out" 469 }; 470 static u32 mux_clkm_pllp_pllre_idx[] = { 471 [0] = 0, [1] = 1, [2] = 5, 472 }; 473 474 static const char *mux_pllp_pllc_clkm_clk32[] = { 475 "pll_p", "pll_c", "clk_m", "clk_32k" 476 }; 477 #define mux_pllp_pllc_clkm_clk32_idx NULL 478 479 static const char *mux_plla_clk32_pllp_clkm_plle[] = { 480 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 481 }; 482 #define mux_plla_clk32_pllp_clkm_plle_idx NULL 483 484 static const char *mux_clkm_pllp_pllc_pllre[] = { 485 "clk_m", "pll_p", "pll_c", "pll_re_out" 486 }; 487 static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 488 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 489 }; 490 491 static const char *mux_clkm_48M_pllp_480M[] = { 492 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 493 }; 494 static u32 mux_clkm_48M_pllp_480M_idx[] = { 495 [0] = 0, [1] = 2, [2] = 4, [3] = 6, 496 }; 497 498 static const char *mux_clkm_pllre_clk32_480M[] = { 499 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M" 500 }; 501 #define mux_clkm_pllre_clk32_480M_idx NULL 502 503 static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 504 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 505 }; 506 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 507 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 508 }; 509 510 static const char *mux_pllp_out3_pllp_pllc_clkm[] = { 511 "pll_p_out3", "pll_p", "pll_c", "clk_m" 512 }; 513 static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = { 514 [0] = 0, [1] = 1, [2] = 2, [3] = 6, 515 }; 516 517 static const char *mux_ss_div2_60M[] = { 518 "xusb_ss_div2", "pll_u_60M" 519 }; 520 #define mux_ss_div2_60M_idx NULL 521 522 static const char *mux_ss_div2_60M_ss[] = { 523 "xusb_ss_div2", "pll_u_60M", "xusb_ss_src" 524 }; 525 #define mux_ss_div2_60M_ss_idx NULL 526 527 static const char *mux_ss_clkm[] = { 528 "xusb_ss_src", "clk_m" 529 }; 530 #define mux_ss_clkm_idx NULL 531 532 static const char *mux_d_audio_clk[] = { 533 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 534 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 535 }; 536 static u32 mux_d_audio_clk_idx[] = { 537 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 538 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 539 }; 540 541 static const char *mux_pllp_plld_pllc_clkm[] = { 542 "pll_p", "pll_d_out0", "pll_c", "clk_m" 543 }; 544 #define mux_pllp_plld_pllc_clkm_idx NULL 545 static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = { 546 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4", 547 }; 548 static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = { 549 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7, 550 }; 551 552 static const char *mux_pllp_clkm1[] = { 553 "pll_p", "clk_m", 554 }; 555 #define mux_pllp_clkm1_idx NULL 556 557 static const char *mux_pllp3_pllc_clkm[] = { 558 "pll_p_out3", "pll_c", "pll_c2", "clk_m", 559 }; 560 #define mux_pllp3_pllc_clkm_idx NULL 561 562 static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = { 563 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m" 564 }; 565 #define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL 566 567 static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = { 568 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4", 569 }; 570 static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = { 571 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7, 572 }; 573 574 /* SOR1 mux'es */ 575 static const char *mux_pllp_plld_plld2_clkm[] = { 576 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m" 577 }; 578 static u32 mux_pllp_plld_plld2_clkm_idx[] = { 579 [0] = 0, [1] = 2, [2] = 5, [3] = 6 580 }; 581 582 static const char *mux_pllp_pllre_clkm[] = { 583 "pll_p", "pll_re_out1", "clk_m" 584 }; 585 586 static u32 mux_pllp_pllre_clkm_idx[] = { 587 [0] = 0, [1] = 2, [2] = 3, 588 }; 589 590 static const char *mux_clkm_plldp_sor0lvds[] = { 591 "clk_m", "pll_dp", "sor0_lvds", 592 }; 593 #define mux_clkm_plldp_sor0lvds_idx NULL 594 595 static const char * const mux_dmic1[] = { 596 "pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m" 597 }; 598 #define mux_dmic1_idx NULL 599 600 static const char * const mux_dmic2[] = { 601 "pll_a_out0", "dmic2_sync_clk", "pll_p", "clk_m" 602 }; 603 #define mux_dmic2_idx NULL 604 605 static const char * const mux_dmic3[] = { 606 "pll_a_out0", "dmic3_sync_clk", "pll_p", "clk_m" 607 }; 608 #define mux_dmic3_idx NULL 609 610 static struct tegra_periph_init_data periph_clks[] = { 611 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio), 612 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0), 613 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1), 614 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2), 615 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1), 616 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2), 617 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3), 618 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4), 619 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5), 620 I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6), 621 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), 622 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), 623 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), 624 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), 625 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), 626 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), 627 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), 628 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8), 629 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8), 630 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9), 631 INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10), 632 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8), 633 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc), 634 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec), 635 INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8), 636 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8), 637 INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9), 638 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), 639 INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), 640 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8), 641 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8), 642 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03), 643 INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8), 644 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED), 645 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0), 646 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1), 647 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2), 648 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3), 649 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4), 650 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), 651 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in), 652 MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8), 653 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), 654 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx), 655 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx), 656 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), 657 MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8), 658 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), 659 MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8), 660 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), 661 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1), 662 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2), 663 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3), 664 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4), 665 MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9), 666 MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9), 667 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), 668 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), 669 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), 670 MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8), 671 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor), 672 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi), 673 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor), 674 MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9), 675 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab), 676 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd), 677 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile), 678 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp), 679 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp), 680 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor), 681 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon), 682 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref), 683 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc), 684 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow), 685 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1), 686 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2), 687 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3), 688 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4), 689 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5), 690 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6), 691 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve), 692 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo), 693 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac), 694 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash), 695 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed), 696 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob), 697 MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8), 698 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), 699 MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8), 700 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), 701 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), 702 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2), 703 MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8), 704 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8), 705 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8), 706 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8), 707 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8), 708 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8), 709 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8), 710 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8), 711 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8), 712 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8), 713 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8), 714 MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9), 715 MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9), 716 MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9), 717 MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9), 718 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), 719 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), 720 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), 721 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1), 722 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), 723 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), 724 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), 725 MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8), 726 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), 727 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8), 728 MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9), 729 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy), 730 MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8), 731 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio), 732 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz), 733 MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8), 734 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock), 735 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED), 736 MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED), 737 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL), 738 NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL), 739 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL), 740 NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL), 741 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock), 742 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), 743 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), 744 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), 745 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), 746 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), 747 UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8), 748 UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8), 749 UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8), 750 UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8), 751 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), 752 XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8), 753 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), 754 XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8), 755 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), 756 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src), 757 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8), 758 NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL), 759 NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL), 760 NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL), 761 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), 762 XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8), 763 MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb), 764 MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc), 765 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec), 766 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg), 767 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape), 768 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy), 769 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi), 770 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c), 771 MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif), 772 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape), 773 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb), 774 MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud), 775 MUX8("dmic1", mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1), 776 MUX8("dmic2", mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2), 777 MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3), 778 }; 779 780 static struct tegra_periph_init_data gate_clks[] = { 781 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), 782 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), 783 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), 784 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), 785 GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), 786 GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), 787 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), 788 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), 789 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), 790 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), 791 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), 792 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0), 793 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0), 794 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0), 795 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0), 796 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0), 797 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0), 798 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0), 799 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0), 800 GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0), 801 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0), 802 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0), 803 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0), 804 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0), 805 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0), 806 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0), 807 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0), 808 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL), 809 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), 810 GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0), 811 GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0), 812 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0), 813 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), 814 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0), 815 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0), 816 GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0), 817 GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0), 818 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0), 819 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0), 820 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0), 821 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0), 822 GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0), 823 GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0), 824 GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0), 825 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0), 826 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0), 827 GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0), 828 GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0), 829 }; 830 831 static struct tegra_periph_init_data div_clks[] = { 832 DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0), 833 }; 834 835 struct pll_out_data { 836 char *div_name; 837 char *pll_out_name; 838 u32 offset; 839 int clk_id; 840 u8 div_shift; 841 u8 div_flags; 842 u8 rst_shift; 843 spinlock_t *lock; 844 }; 845 846 #define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \ 847 {\ 848 .div_name = "pll_p_out" #_num "_div",\ 849 .pll_out_name = "pll_p_out" #_num,\ 850 .offset = _offset,\ 851 .div_shift = _div_shift,\ 852 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\ 853 TEGRA_DIVIDER_ROUND_UP,\ 854 .rst_shift = _rst_shift,\ 855 .clk_id = tegra_clk_ ## _id,\ 856 .lock = &_offset ##_lock,\ 857 } 858 859 static struct pll_out_data pllp_out_clks[] = { 860 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1), 861 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2), 862 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int), 863 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3), 864 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4), 865 PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5), 866 }; 867 868 static void __init periph_clk_init(void __iomem *clk_base, 869 struct tegra_clk *tegra_clks) 870 { 871 int i; 872 struct clk *clk; 873 struct clk **dt_clk; 874 875 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { 876 const struct tegra_clk_periph_regs *bank; 877 struct tegra_periph_init_data *data; 878 879 data = periph_clks + i; 880 881 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 882 if (!dt_clk) 883 continue; 884 885 bank = get_reg_bank(data->periph.gate.clk_num); 886 if (!bank) 887 continue; 888 889 data->periph.gate.regs = bank; 890 clk = tegra_clk_register_periph_data(clk_base, data); 891 *dt_clk = clk; 892 } 893 } 894 895 static void __init gate_clk_init(void __iomem *clk_base, 896 struct tegra_clk *tegra_clks) 897 { 898 int i; 899 struct clk *clk; 900 struct clk **dt_clk; 901 902 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { 903 struct tegra_periph_init_data *data; 904 905 data = gate_clks + i; 906 907 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 908 if (!dt_clk) 909 continue; 910 911 clk = tegra_clk_register_periph_gate(data->name, 912 data->p.parent_name, data->periph.gate.flags, 913 clk_base, data->flags, 914 data->periph.gate.clk_num, 915 periph_clk_enb_refcnt); 916 *dt_clk = clk; 917 } 918 } 919 920 static void __init div_clk_init(void __iomem *clk_base, 921 struct tegra_clk *tegra_clks) 922 { 923 int i; 924 struct clk *clk; 925 struct clk **dt_clk; 926 927 for (i = 0; i < ARRAY_SIZE(div_clks); i++) { 928 struct tegra_periph_init_data *data; 929 930 data = div_clks + i; 931 932 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 933 if (!dt_clk) 934 continue; 935 936 clk = tegra_clk_register_divider(data->name, 937 data->p.parent_name, clk_base + data->offset, 938 data->flags, data->periph.divider.flags, 939 data->periph.divider.shift, 940 data->periph.divider.width, 941 data->periph.divider.frac_width, 942 data->periph.divider.lock); 943 *dt_clk = clk; 944 } 945 } 946 947 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, 948 struct tegra_clk *tegra_clks, 949 struct tegra_clk_pll_params *pll_params) 950 { 951 struct clk *clk; 952 struct clk **dt_clk; 953 int i; 954 955 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); 956 if (dt_clk) { 957 /* PLLP */ 958 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, 959 pmc_base, 0, pll_params, NULL); 960 clk_register_clkdev(clk, "pll_p", NULL); 961 *dt_clk = clk; 962 } 963 964 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) { 965 struct pll_out_data *data; 966 967 data = pllp_out_clks + i; 968 969 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 970 if (!dt_clk) 971 continue; 972 973 clk = tegra_clk_register_divider(data->div_name, "pll_p", 974 clk_base + data->offset, 0, data->div_flags, 975 data->div_shift, 8, 1, data->lock); 976 clk = tegra_clk_register_pll_out(data->pll_out_name, 977 data->div_name, clk_base + data->offset, 978 data->rst_shift + 1, data->rst_shift, 979 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 980 data->lock); 981 *dt_clk = clk; 982 } 983 984 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu, 985 tegra_clks); 986 if (dt_clk) { 987 /* 988 * Tegra210 has control on enabling/disabling PLLP branches to 989 * CPU, register a gate clock "pll_p_out_cpu" for this gating 990 * function and parent "pll_p_out4" to it, so when we are 991 * re-parenting CPU off from "pll_p_out4" the PLLP branching to 992 * CPU can be disabled automatically. 993 */ 994 clk = tegra_clk_register_divider("pll_p_out4_div", 995 "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24, 996 8, 1, &PLLP_OUTB_lock); 997 998 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks); 999 if (dt_clk) { 1000 clk = tegra_clk_register_pll_out("pll_p_out4", 1001 "pll_p_out4_div", clk_base + PLLP_OUTB, 1002 17, 16, CLK_IGNORE_UNUSED | 1003 CLK_SET_RATE_PARENT, 0, 1004 &PLLP_OUTB_lock); 1005 *dt_clk = clk; 1006 } 1007 } 1008 1009 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks); 1010 if (dt_clk) { 1011 /* PLLP_OUT_HSIO */ 1012 clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p", 1013 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1014 clk_base + PLLP_MISC1, 29, 0, NULL); 1015 *dt_clk = clk; 1016 } 1017 1018 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks); 1019 if (dt_clk) { 1020 /* PLLP_OUT_XUSB */ 1021 clk = clk_register_gate(NULL, "pll_p_out_xusb", 1022 "pll_p_out_hsio", CLK_SET_RATE_PARENT | 1023 CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0, 1024 NULL); 1025 clk_register_clkdev(clk, "pll_p_out_xusb", NULL); 1026 *dt_clk = clk; 1027 } 1028 } 1029 1030 void __init tegra_periph_clk_init(void __iomem *clk_base, 1031 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 1032 struct tegra_clk_pll_params *pll_params) 1033 { 1034 init_pllp(clk_base, pmc_base, tegra_clks, pll_params); 1035 periph_clk_init(clk_base, tegra_clks); 1036 gate_clk_init(clk_base, tegra_clks); 1037 div_clk_init(clk_base, tegra_clks); 1038 } 1039