1 /*
2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #include <linux/io.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/clk/tegra.h>
25 
26 #include "clk.h"
27 #include "clk-id.h"
28 
29 #define CLK_SOURCE_I2S0 0x1d8
30 #define CLK_SOURCE_I2S1 0x100
31 #define CLK_SOURCE_I2S2 0x104
32 #define CLK_SOURCE_NDFLASH 0x160
33 #define CLK_SOURCE_I2S3 0x3bc
34 #define CLK_SOURCE_I2S4 0x3c0
35 #define CLK_SOURCE_SPDIF_OUT 0x108
36 #define CLK_SOURCE_SPDIF_IN 0x10c
37 #define CLK_SOURCE_PWM 0x110
38 #define CLK_SOURCE_ADX 0x638
39 #define CLK_SOURCE_ADX1 0x670
40 #define CLK_SOURCE_AMX 0x63c
41 #define CLK_SOURCE_AMX1 0x674
42 #define CLK_SOURCE_HDA 0x428
43 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
44 #define CLK_SOURCE_SBC1 0x134
45 #define CLK_SOURCE_SBC2 0x118
46 #define CLK_SOURCE_SBC3 0x11c
47 #define CLK_SOURCE_SBC4 0x1b4
48 #define CLK_SOURCE_SBC5 0x3c8
49 #define CLK_SOURCE_SBC6 0x3cc
50 #define CLK_SOURCE_SATA_OOB 0x420
51 #define CLK_SOURCE_SATA 0x424
52 #define CLK_SOURCE_NDSPEED 0x3f8
53 #define CLK_SOURCE_VFIR 0x168
54 #define CLK_SOURCE_SDMMC1 0x150
55 #define CLK_SOURCE_SDMMC2 0x154
56 #define CLK_SOURCE_SDMMC3 0x1bc
57 #define CLK_SOURCE_SDMMC4 0x164
58 #define CLK_SOURCE_CVE 0x140
59 #define CLK_SOURCE_TVO 0x188
60 #define CLK_SOURCE_TVDAC 0x194
61 #define CLK_SOURCE_VDE 0x1c8
62 #define CLK_SOURCE_CSITE 0x1d4
63 #define CLK_SOURCE_LA 0x1f8
64 #define CLK_SOURCE_TRACE 0x634
65 #define CLK_SOURCE_OWR 0x1cc
66 #define CLK_SOURCE_NOR 0x1d0
67 #define CLK_SOURCE_MIPI 0x174
68 #define CLK_SOURCE_I2C1 0x124
69 #define CLK_SOURCE_I2C2 0x198
70 #define CLK_SOURCE_I2C3 0x1b8
71 #define CLK_SOURCE_I2C4 0x3c4
72 #define CLK_SOURCE_I2C5 0x128
73 #define CLK_SOURCE_I2C6 0x65c
74 #define CLK_SOURCE_UARTA 0x178
75 #define CLK_SOURCE_UARTB 0x17c
76 #define CLK_SOURCE_UARTC 0x1a0
77 #define CLK_SOURCE_UARTD 0x1c0
78 #define CLK_SOURCE_UARTE 0x1c4
79 #define CLK_SOURCE_3D 0x158
80 #define CLK_SOURCE_2D 0x15c
81 #define CLK_SOURCE_MPE 0x170
82 #define CLK_SOURCE_UARTE 0x1c4
83 #define CLK_SOURCE_VI_SENSOR 0x1a8
84 #define CLK_SOURCE_VI 0x148
85 #define CLK_SOURCE_EPP 0x16c
86 #define CLK_SOURCE_MSENC 0x1f0
87 #define CLK_SOURCE_TSEC 0x1f4
88 #define CLK_SOURCE_HOST1X 0x180
89 #define CLK_SOURCE_HDMI 0x18c
90 #define CLK_SOURCE_DISP1 0x138
91 #define CLK_SOURCE_DISP2 0x13c
92 #define CLK_SOURCE_CILAB 0x614
93 #define CLK_SOURCE_CILCD 0x618
94 #define CLK_SOURCE_CILE 0x61c
95 #define CLK_SOURCE_DSIALP 0x620
96 #define CLK_SOURCE_DSIBLP 0x624
97 #define CLK_SOURCE_TSENSOR 0x3b8
98 #define CLK_SOURCE_D_AUDIO 0x3d0
99 #define CLK_SOURCE_DAM0 0x3d8
100 #define CLK_SOURCE_DAM1 0x3dc
101 #define CLK_SOURCE_DAM2 0x3e0
102 #define CLK_SOURCE_ACTMON 0x3e8
103 #define CLK_SOURCE_EXTERN1 0x3ec
104 #define CLK_SOURCE_EXTERN2 0x3f0
105 #define CLK_SOURCE_EXTERN3 0x3f4
106 #define CLK_SOURCE_I2CSLOW 0x3fc
107 #define CLK_SOURCE_SE 0x42c
108 #define CLK_SOURCE_MSELECT 0x3b4
109 #define CLK_SOURCE_DFLL_REF 0x62c
110 #define CLK_SOURCE_DFLL_SOC 0x630
111 #define CLK_SOURCE_SOC_THERM 0x644
112 #define CLK_SOURCE_XUSB_HOST_SRC 0x600
113 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604
114 #define CLK_SOURCE_XUSB_FS_SRC 0x608
115 #define CLK_SOURCE_XUSB_SS_SRC 0x610
116 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
117 #define CLK_SOURCE_ISP 0x144
118 #define CLK_SOURCE_SOR0 0x414
119 #define CLK_SOURCE_DPAUX 0x418
120 #define CLK_SOURCE_SATA_OOB 0x420
121 #define CLK_SOURCE_SATA 0x424
122 #define CLK_SOURCE_ENTROPY 0x628
123 #define CLK_SOURCE_VI_SENSOR2 0x658
124 #define CLK_SOURCE_HDMI_AUDIO 0x668
125 #define CLK_SOURCE_VIC03 0x678
126 #define CLK_SOURCE_CLK72MHZ 0x66c
127 #define CLK_SOURCE_DBGAPB 0x718
128 #define CLK_SOURCE_NVENC 0x6a0
129 #define CLK_SOURCE_NVDEC 0x698
130 #define CLK_SOURCE_NVJPG 0x69c
131 #define CLK_SOURCE_APE 0x6c0
132 #define CLK_SOURCE_SOR1 0x410
133 #define CLK_SOURCE_SDMMC_LEGACY 0x694
134 #define CLK_SOURCE_QSPI 0x6c4
135 #define CLK_SOURCE_VI_I2C 0x6c8
136 #define CLK_SOURCE_MIPIBIF 0x660
137 #define CLK_SOURCE_UARTAPE 0x710
138 #define CLK_SOURCE_TSECB 0x6d8
139 #define CLK_SOURCE_MAUD 0x6d4
140 #define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
141 
142 #define MASK(x) (BIT(x) - 1)
143 
144 #define MUX(_name, _parents, _offset,	\
145 			    _clk_num, _gate_flags, _clk_id)	\
146 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
147 			30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
148 			_clk_num,  _gate_flags, _clk_id, _parents##_idx, 0,\
149 			NULL)
150 
151 #define MUX_FLAGS(_name, _parents, _offset,\
152 			    _clk_num, _gate_flags, _clk_id, flags)\
153 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
154 			30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
155 			_clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
156 			NULL)
157 
158 #define MUX8(_name, _parents, _offset, \
159 			     _clk_num, _gate_flags, _clk_id)	\
160 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
161 			29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
162 			_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
163 			NULL)
164 
165 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)	\
166 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,	\
167 			      29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
168 			      0, TEGRA_PERIPH_NO_GATE, _clk_id,\
169 			      _parents##_idx, 0, _lock)
170 
171 #define INT(_name, _parents, _offset,	\
172 			    _clk_num, _gate_flags, _clk_id)	\
173 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
174 			30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
175 			TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
176 			_clk_id, _parents##_idx, 0, NULL)
177 
178 #define INT_FLAGS(_name, _parents, _offset,\
179 			    _clk_num, _gate_flags, _clk_id, flags)\
180 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
181 			30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
182 			TEGRA_DIVIDER_ROUND_UP, _clk_num,  _gate_flags,\
183 			_clk_id, _parents##_idx, flags, NULL)
184 
185 #define INT8(_name, _parents, _offset,\
186 			    _clk_num, _gate_flags, _clk_id)	\
187 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
188 			29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
189 			TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
190 			_clk_id, _parents##_idx, 0, NULL)
191 
192 #define UART(_name, _parents, _offset,\
193 			     _clk_num, _clk_id)			\
194 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
195 			30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
196 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
197 			_parents##_idx, 0, NULL)
198 
199 #define UART8(_name, _parents, _offset,\
200 			     _clk_num, _clk_id)			\
201 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
202 			29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
203 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
204 			_parents##_idx, 0, NULL)
205 
206 #define I2C(_name, _parents, _offset,\
207 			     _clk_num, _clk_id)			\
208 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
209 			30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
210 			_clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
211 
212 #define XUSB(_name, _parents, _offset, \
213 			     _clk_num, _gate_flags, _clk_id)	 \
214 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
215 			29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
216 			TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
217 			_clk_id, _parents##_idx, 0, NULL)
218 
219 #define AUDIO(_name, _offset,  _clk_num,\
220 				 _gate_flags, _clk_id)		\
221 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk,	\
222 			_offset, 16, 0xE01F, 0, 0, 8, 1,		\
223 			TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,	\
224 			_clk_id, mux_d_audio_clk_idx, 0, NULL)
225 
226 #define NODIV(_name, _parents, _offset, \
227 			      _mux_shift, _mux_mask, _clk_num, \
228 			      _gate_flags, _clk_id, _lock)		\
229 	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
230 			_mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
231 			_clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
232 			_clk_id, _parents##_idx, 0, _lock)
233 
234 #define GATE(_name, _parent_name,	\
235 			     _clk_num, _gate_flags,  _clk_id, _flags)	\
236 	{								\
237 		.name = _name,						\
238 		.clk_id = _clk_id,					\
239 		.p.parent_name = _parent_name,				\
240 		.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0,		\
241 				_clk_num, _gate_flags, NULL, NULL),	\
242 		.flags = _flags						\
243 	}
244 
245 #define DIV8(_name, _parent_name, _offset, _clk_id, _flags)		\
246 	{								\
247 		.name = _name,						\
248 		.clk_id = _clk_id,					\
249 		.p.parent_name = _parent_name,				\
250 		.periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1,		\
251 				TEGRA_DIVIDER_ROUND_UP, 0, 0,		\
252 				NULL, NULL),				\
253 		.offset = _offset,					\
254 		.flags = _flags,					\
255 	}
256 
257 #define PLLP_BASE 0xa0
258 #define PLLP_MISC 0xac
259 #define PLLP_MISC1 0x680
260 #define PLLP_OUTA 0xa4
261 #define PLLP_OUTB 0xa8
262 #define PLLP_OUTC 0x67c
263 
264 #define PLL_BASE_LOCK BIT(27)
265 #define PLL_MISC_LOCK_ENABLE 18
266 
267 static DEFINE_SPINLOCK(PLLP_OUTA_lock);
268 static DEFINE_SPINLOCK(PLLP_OUTB_lock);
269 static DEFINE_SPINLOCK(PLLP_OUTC_lock);
270 static DEFINE_SPINLOCK(sor0_lock);
271 static DEFINE_SPINLOCK(sor1_lock);
272 
273 #define MUX_I2S_SPDIF(_id)						\
274 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
275 							   #_id, "pll_p",\
276 							   "clk_m"};
277 MUX_I2S_SPDIF(audio0)
278 MUX_I2S_SPDIF(audio1)
279 MUX_I2S_SPDIF(audio2)
280 MUX_I2S_SPDIF(audio3)
281 MUX_I2S_SPDIF(audio4)
282 MUX_I2S_SPDIF(audio)
283 
284 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
285 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
286 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
287 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
288 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
289 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
290 
291 static const char *mux_pllp_pllc_pllm_clkm[] = {
292 	"pll_p", "pll_c", "pll_m", "clk_m"
293 };
294 #define mux_pllp_pllc_pllm_clkm_idx NULL
295 
296 static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
297 #define mux_pllp_pllc_pllm_idx NULL
298 
299 static const char *mux_pllp_pllc_clk32_clkm[] = {
300 	"pll_p", "pll_c", "clk_32k", "clk_m"
301 };
302 #define mux_pllp_pllc_clk32_clkm_idx NULL
303 
304 static const char *mux_plla_pllc_pllp_clkm[] = {
305 	"pll_a_out0", "pll_c", "pll_p", "clk_m"
306 };
307 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
308 
309 static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
310 	"pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
311 };
312 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
313 	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
314 };
315 
316 static const char *mux_pllp_clkm[] = {
317 	"pll_p", "clk_m"
318 };
319 static u32 mux_pllp_clkm_idx[] = {
320 	[0] = 0, [1] = 3,
321 };
322 
323 static const char *mux_pllp_clkm_2[] = {
324 	"pll_p", "clk_m"
325 };
326 static u32 mux_pllp_clkm_2_idx[] = {
327 	[0] = 2, [1] = 6,
328 };
329 
330 static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
331 	"pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
332 };
333 static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
334 	[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
335 };
336 
337 static const char *
338 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
339 	"pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
340 	"pll_a_out0", "pll_c4_out0"
341 };
342 static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
343 	[0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
344 };
345 
346 static const char *mux_pllc_pllp_plla[] = {
347 	"pll_c", "pll_p", "pll_a_out0"
348 };
349 static u32 mux_pllc_pllp_plla_idx[] = {
350 	[0] = 1, [1] = 2, [2] = 3,
351 };
352 
353 static const char *mux_clkm_pllc_pllp_plla[] = {
354 	"clk_m", "pll_c", "pll_p", "pll_a_out0"
355 };
356 #define mux_clkm_pllc_pllp_plla_idx NULL
357 
358 static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
359 	"pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
360 };
361 static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
362 	[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
363 };
364 
365 static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
366 	"pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
367 };
368 static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
369 	[0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
370 };
371 
372 static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
373 	"pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
374 };
375 #define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
376 	mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
377 
378 static const char *
379 mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
380 	"pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
381 	"pll_c4_out2", "clk_m"
382 };
383 #define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
384 
385 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
386 	"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
387 };
388 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
389 
390 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
391 	"pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
392 	"pll_d2_out0", "clk_m"
393 };
394 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
395 
396 static const char *mux_pllm_pllc_pllp_plla[] = {
397 	"pll_m", "pll_c", "pll_p", "pll_a_out0"
398 };
399 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
400 
401 static const char *mux_pllp_pllc_clkm[] = {
402 	"pll_p", "pll_c", "clk_m"
403 };
404 static u32 mux_pllp_pllc_clkm_idx[] = {
405 	[0] = 0, [1] = 1, [2] = 3,
406 };
407 
408 static const char *mux_pllp_pllc_clkm_1[] = {
409 	"pll_p", "pll_c", "clk_m"
410 };
411 static u32 mux_pllp_pllc_clkm_1_idx[] = {
412 	[0] = 0, [1] = 2, [2] = 5,
413 };
414 
415 static const char *mux_pllp_pllc_plla_clkm[] = {
416 	"pll_p", "pll_c", "pll_a_out0", "clk_m"
417 };
418 static u32 mux_pllp_pllc_plla_clkm_idx[] = {
419 	[0] = 0, [1] = 2, [2] = 4, [3] = 6,
420 };
421 
422 static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
423 	"pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
424 };
425 static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
426 	[0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
427 };
428 
429 static const char *
430 mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
431 	"pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
432 	"clk_m", "pll_c4_out0"
433 };
434 static u32
435 mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
436 	[0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
437 };
438 
439 static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
440 	"pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
441 };
442 static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
443 	[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
444 };
445 
446 static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
447 	"pll_p",
448 	"pll_c4_out2", "pll_c4_out0",	/* LJ input */
449 	"pll_c4_out2", "pll_c4_out1",
450 	"pll_c4_out1",			/* LJ input */
451 	"clk_m", "pll_c4_out0"
452 };
453 #define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
454 
455 static const char *mux_pllp_pllc2_c_c3_clkm[] = {
456 	"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
457 };
458 static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
459 	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
460 };
461 
462 static const char *mux_pllp_clkm_clk32_plle[] = {
463 	"pll_p", "clk_m", "clk_32k", "pll_e"
464 };
465 static u32 mux_pllp_clkm_clk32_plle_idx[] = {
466 	[0] = 0, [1] = 2, [2] = 4, [3] = 6,
467 };
468 
469 static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
470 	"pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
471 };
472 #define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
473 
474 static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
475 	"pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
476 	"pll_c4_out2"
477 };
478 static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
479 	[0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
480 };
481 
482 static const char *mux_clkm_pllp_pllre[] = {
483 	"clk_m", "pll_p_out_xusb", "pll_re_out"
484 };
485 static u32 mux_clkm_pllp_pllre_idx[] = {
486 	[0] = 0, [1] = 1, [2] = 5,
487 };
488 
489 static const char *mux_pllp_pllc_clkm_clk32[] = {
490 	"pll_p", "pll_c", "clk_m", "clk_32k"
491 };
492 #define mux_pllp_pllc_clkm_clk32_idx NULL
493 
494 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
495 	"pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
496 };
497 #define mux_plla_clk32_pllp_clkm_plle_idx NULL
498 
499 static const char *mux_clkm_pllp_pllc_pllre[] = {
500 	"clk_m", "pll_p", "pll_c", "pll_re_out"
501 };
502 static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
503 	[0] = 0, [1] = 1, [2] = 3, [3] = 5,
504 };
505 
506 static const char *mux_clkm_48M_pllp_480M[] = {
507 	"clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
508 };
509 static u32 mux_clkm_48M_pllp_480M_idx[] = {
510 	[0] = 0, [1] = 2, [2] = 4, [3] = 6,
511 };
512 
513 static const char *mux_clkm_pllre_clk32_480M[] = {
514 	"clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
515 };
516 #define mux_clkm_pllre_clk32_480M_idx NULL
517 
518 static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
519 	"clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
520 };
521 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
522 	[0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
523 };
524 
525 static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
526 	"pll_p_out3", "pll_p", "pll_c", "clk_m"
527 };
528 static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
529 	[0] = 0, [1] = 1, [2] = 2, [3] = 6,
530 };
531 
532 static const char *mux_ss_div2_60M[] = {
533 	"xusb_ss_div2", "pll_u_60M"
534 };
535 #define mux_ss_div2_60M_idx NULL
536 
537 static const char *mux_ss_div2_60M_ss[] = {
538 	"xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
539 };
540 #define mux_ss_div2_60M_ss_idx NULL
541 
542 static const char *mux_ss_clkm[] = {
543 	"xusb_ss_src", "clk_m"
544 };
545 #define mux_ss_clkm_idx NULL
546 
547 static const char *mux_d_audio_clk[] = {
548 	"pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
549 	"i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
550 };
551 static u32 mux_d_audio_clk_idx[] = {
552 	[0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
553 	[5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
554 };
555 
556 static const char *mux_pllp_plld_pllc_clkm[] = {
557 	"pll_p", "pll_d_out0", "pll_c", "clk_m"
558 };
559 #define mux_pllp_plld_pllc_clkm_idx NULL
560 static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
561 	"pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
562 };
563 static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
564 	[0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
565 };
566 
567 static const char *mux_pllp_clkm1[] = {
568 	"pll_p", "clk_m",
569 };
570 #define mux_pllp_clkm1_idx NULL
571 
572 static const char *mux_pllp3_pllc_clkm[] = {
573 	"pll_p_out3", "pll_c", "pll_c2", "clk_m",
574 };
575 #define mux_pllp3_pllc_clkm_idx NULL
576 
577 static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
578 	"pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
579 };
580 #define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
581 
582 static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
583 	"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
584 };
585 static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
586 	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
587 };
588 
589 /* SOR1 mux'es */
590 static const char *mux_pllp_plld_plld2_clkm[] = {
591 	"pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
592 };
593 static u32 mux_pllp_plld_plld2_clkm_idx[] = {
594 	[0] = 0, [1] = 2, [2] = 5, [3] = 6
595 };
596 
597 static const char *mux_plldp_sor1_src[] = {
598 	"pll_dp", "clk_sor1_src"
599 };
600 #define mux_plldp_sor1_src_idx NULL
601 
602 static const char *mux_clkm_sor1_brick_sor1_src[] = {
603 	"clk_m", "sor1_brick", "sor1_src", "sor1_brick"
604 };
605 #define mux_clkm_sor1_brick_sor1_src_idx NULL
606 
607 static const char *mux_pllp_pllre_clkm[] = {
608 	"pll_p", "pll_re_out1", "clk_m"
609 };
610 
611 static u32 mux_pllp_pllre_clkm_idx[] = {
612 	[0] = 0, [1] = 2, [2] = 3,
613 };
614 
615 static const char *mux_clkm_plldp_sor0lvds[] = {
616 	"clk_m", "pll_dp", "sor0_lvds",
617 };
618 #define mux_clkm_plldp_sor0lvds_idx NULL
619 
620 static struct tegra_periph_init_data periph_clks[] = {
621 	AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
622 	AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
623 	AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
624 	AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
625 	I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
626 	I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
627 	I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
628 	I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
629 	I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
630 	I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
631 	INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
632 	INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
633 	INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
634 	INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
635 	INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
636 	INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
637 	INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
638 	INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
639 	INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
640 	INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
641 	INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
642 	INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
643 	INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
644 	INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
645 	INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
646 	INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
647 	INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
648 	INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
649 	INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
650 	INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
651 	INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
652 	INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
653 	INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
654 	INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
655 	MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
656 	MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
657 	MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
658 	MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
659 	MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
660 	MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
661 	MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
662 	MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
663 	MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
664 	MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
665 	MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
666 	MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
667 	MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
668 	MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
669 	MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
670 	MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
671 	MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
672 	MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
673 	MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
674 	MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
675 	MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
676 	MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
677 	MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
678 	MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
679 	MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
680 	MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
681 	MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
682 	MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
683 	MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
684 	MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
685 	MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
686 	MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
687 	MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
688 	MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
689 	MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
690 	MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
691 	MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
692 	MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
693 	MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
694 	MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
695 	MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
696 	MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
697 	MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
698 	MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
699 	MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
700 	MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
701 	MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
702 	MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
703 	MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
704 	MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
705 	MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
706 	MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
707 	MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
708 	MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
709 	MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
710 	MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
711 	MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
712 	MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
713 	MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
714 	MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
715 	MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
716 	MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
717 	MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
718 	MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
719 	MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
720 	MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
721 	MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
722 	MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
723 	MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
724 	MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
725 	MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
726 	MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
727 	MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
728 	MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
729 	MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
730 	MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
731 	MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
732 	MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
733 	MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
734 	MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
735 	MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
736 	MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
737 	MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
738 	MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
739 	MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
740 	MUX8("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_9),
741 	MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149,  0, tegra_clk_entropy),
742 	MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149,  0, tegra_clk_entropy_8),
743 	MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
744 	MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
745 	MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
746 	MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
747 	MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
748 	MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
749 	NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
750 	NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
751 	NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
752 	NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
753 	NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
754 	UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
755 	UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
756 	UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
757 	UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
758 	UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
759 	UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
760 	UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
761 	UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
762 	UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
763 	XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
764 	XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
765 	XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
766 	XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
767 	XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
768 	XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
769 	XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
770 	NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
771 	NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
772 	NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
773 	XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
774 	XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
775 	MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
776 	MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
777 	MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
778 	MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
779 	MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
780 	MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
781 	NODIV("sor1_brick", mux_plldp_sor1_src, CLK_SOURCE_SOR1, 14, MASK(1), 183, 0, tegra_clk_sor1_brick, &sor1_lock),
782 	NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
783 	MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
784 	MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
785 	I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
786 	MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
787 	MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
788 	MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
789 	MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
790 };
791 
792 static struct tegra_periph_init_data gate_clks[] = {
793 	GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
794 	GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
795 	GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
796 	GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
797 	GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
798 	GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
799 	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
800 	GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
801 	GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
802 	GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
803 	GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
804 	GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
805 	GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
806 	GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
807 	GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
808 	GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
809 	GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
810 	GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
811 	GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
812 	GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
813 	GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
814 	GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
815 	GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
816 	GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
817 	GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
818 	GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
819 	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
820 	GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
821 	GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
822 	GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
823 	GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
824 	GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
825 	GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
826 	GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
827 	GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
828 	GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
829 	GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
830 	GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
831 	GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
832 };
833 
834 static struct tegra_periph_init_data div_clks[] = {
835 	DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
836 };
837 
838 struct pll_out_data {
839 	char *div_name;
840 	char *pll_out_name;
841 	u32 offset;
842 	int clk_id;
843 	u8 div_shift;
844 	u8 div_flags;
845 	u8 rst_shift;
846 	spinlock_t *lock;
847 };
848 
849 #define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
850 	{\
851 		.div_name = "pll_p_out" #_num "_div",\
852 		.pll_out_name = "pll_p_out" #_num,\
853 		.offset = _offset,\
854 		.div_shift = _div_shift,\
855 		.div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
856 					TEGRA_DIVIDER_ROUND_UP,\
857 		.rst_shift = _rst_shift,\
858 		.clk_id = tegra_clk_ ## _id,\
859 		.lock = &_offset ##_lock,\
860 	}
861 
862 static struct pll_out_data pllp_out_clks[] = {
863 	PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
864 	PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
865 	PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
866 	PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
867 	PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
868 	PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
869 };
870 
871 static void __init periph_clk_init(void __iomem *clk_base,
872 				struct tegra_clk *tegra_clks)
873 {
874 	int i;
875 	struct clk *clk;
876 	struct clk **dt_clk;
877 
878 	for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
879 		const struct tegra_clk_periph_regs *bank;
880 		struct tegra_periph_init_data *data;
881 
882 		data = periph_clks + i;
883 
884 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
885 		if (!dt_clk)
886 			continue;
887 
888 		bank = get_reg_bank(data->periph.gate.clk_num);
889 		if (!bank)
890 			continue;
891 
892 		data->periph.gate.regs = bank;
893 		clk = tegra_clk_register_periph(data->name,
894 			data->p.parent_names, data->num_parents,
895 			&data->periph, clk_base, data->offset,
896 			data->flags);
897 		*dt_clk = clk;
898 	}
899 }
900 
901 static void __init gate_clk_init(void __iomem *clk_base,
902 				struct tegra_clk *tegra_clks)
903 {
904 	int i;
905 	struct clk *clk;
906 	struct clk **dt_clk;
907 
908 	for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
909 		struct tegra_periph_init_data *data;
910 
911 		data = gate_clks + i;
912 
913 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
914 		if (!dt_clk)
915 			continue;
916 
917 		clk = tegra_clk_register_periph_gate(data->name,
918 				data->p.parent_name, data->periph.gate.flags,
919 				clk_base, data->flags,
920 				data->periph.gate.clk_num,
921 				periph_clk_enb_refcnt);
922 		*dt_clk = clk;
923 	}
924 }
925 
926 static void __init div_clk_init(void __iomem *clk_base,
927 				struct tegra_clk *tegra_clks)
928 {
929 	int i;
930 	struct clk *clk;
931 	struct clk **dt_clk;
932 
933 	for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
934 		struct tegra_periph_init_data *data;
935 
936 		data = div_clks + i;
937 
938 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
939 		if (!dt_clk)
940 			continue;
941 
942 		clk = tegra_clk_register_divider(data->name,
943 				data->p.parent_name, clk_base + data->offset,
944 				data->flags, data->periph.divider.flags,
945 				data->periph.divider.shift,
946 				data->periph.divider.width,
947 				data->periph.divider.frac_width,
948 				data->periph.divider.lock);
949 		*dt_clk = clk;
950 	}
951 }
952 
953 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
954 				struct tegra_clk *tegra_clks,
955 				struct tegra_clk_pll_params *pll_params)
956 {
957 	struct clk *clk;
958 	struct clk **dt_clk;
959 	int i;
960 
961 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
962 	if (dt_clk) {
963 		/* PLLP */
964 		clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
965 					pmc_base, 0, pll_params, NULL);
966 		clk_register_clkdev(clk, "pll_p", NULL);
967 		*dt_clk = clk;
968 	}
969 
970 	for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
971 		struct pll_out_data *data;
972 
973 		data = pllp_out_clks + i;
974 
975 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
976 		if (!dt_clk)
977 			continue;
978 
979 		clk = tegra_clk_register_divider(data->div_name, "pll_p",
980 				clk_base + data->offset, 0, data->div_flags,
981 				data->div_shift, 8, 1, data->lock);
982 		clk = tegra_clk_register_pll_out(data->pll_out_name,
983 				data->div_name, clk_base + data->offset,
984 				data->rst_shift + 1, data->rst_shift,
985 				CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
986 				data->lock);
987 		*dt_clk = clk;
988 	}
989 
990 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
991 			tegra_clks);
992 	if (dt_clk) {
993 		/*
994 		 * Tegra210 has control on enabling/disabling PLLP branches to
995 		 * CPU, register a gate clock "pll_p_out_cpu" for this gating
996 		 * function and parent "pll_p_out4" to it, so when we are
997 		 * re-parenting CPU off from "pll_p_out4" the PLLP branching to
998 		 * CPU can be disabled automatically.
999 		 */
1000 		clk = tegra_clk_register_divider("pll_p_out4_div",
1001 				"pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
1002 				8, 1, &PLLP_OUTB_lock);
1003 
1004 		dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
1005 		if (dt_clk) {
1006 			clk = tegra_clk_register_pll_out("pll_p_out4",
1007 					"pll_p_out4_div", clk_base + PLLP_OUTB,
1008 					17, 16, CLK_IGNORE_UNUSED |
1009 					CLK_SET_RATE_PARENT, 0,
1010 					&PLLP_OUTB_lock);
1011 			*dt_clk = clk;
1012 		}
1013 	}
1014 
1015 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
1016 	if (dt_clk) {
1017 		/* PLLP_OUT_HSIO */
1018 		clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
1019 				CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1020 				clk_base + PLLP_MISC1, 29, 0, NULL);
1021 		*dt_clk = clk;
1022 	}
1023 
1024 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
1025 	if (dt_clk) {
1026 		/* PLLP_OUT_XUSB */
1027 		clk = clk_register_gate(NULL, "pll_p_out_xusb",
1028 				"pll_p_out_hsio", CLK_SET_RATE_PARENT |
1029 				CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
1030 				NULL);
1031 		clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
1032 		*dt_clk = clk;
1033 	}
1034 }
1035 
1036 void __init tegra_periph_clk_init(void __iomem *clk_base,
1037 			void __iomem *pmc_base, struct tegra_clk *tegra_clks,
1038 			struct tegra_clk_pll_params *pll_params)
1039 {
1040 	init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
1041 	periph_clk_init(clk_base, tegra_clks);
1042 	gate_clk_init(clk_base, tegra_clks);
1043 	div_clk_init(clk_base, tegra_clks);
1044 }
1045