1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/clk/tegra.h> 25 26 #include "clk.h" 27 #include "clk-id.h" 28 29 #define AUDIO_SYNC_CLK_I2S0 0x4a0 30 #define AUDIO_SYNC_CLK_I2S1 0x4a4 31 #define AUDIO_SYNC_CLK_I2S2 0x4a8 32 #define AUDIO_SYNC_CLK_I2S3 0x4ac 33 #define AUDIO_SYNC_CLK_I2S4 0x4b0 34 #define AUDIO_SYNC_CLK_SPDIF 0x4b4 35 36 #define AUDIO_SYNC_DOUBLER 0x49c 37 38 #define PLLA_OUT 0xb4 39 40 struct tegra_sync_source_initdata { 41 char *name; 42 unsigned long rate; 43 unsigned long max_rate; 44 int clk_id; 45 }; 46 47 #define SYNC(_name) \ 48 {\ 49 .name = #_name,\ 50 .rate = 24000000,\ 51 .max_rate = 24000000,\ 52 .clk_id = tegra_clk_ ## _name,\ 53 } 54 55 struct tegra_audio_clk_initdata { 56 char *gate_name; 57 char *mux_name; 58 u32 offset; 59 int gate_clk_id; 60 int mux_clk_id; 61 }; 62 63 #define AUDIO(_name, _offset) \ 64 {\ 65 .gate_name = #_name,\ 66 .mux_name = #_name"_mux",\ 67 .offset = _offset,\ 68 .gate_clk_id = tegra_clk_ ## _name,\ 69 .mux_clk_id = tegra_clk_ ## _name ## _mux,\ 70 } 71 72 struct tegra_audio2x_clk_initdata { 73 char *parent; 74 char *gate_name; 75 char *name_2x; 76 char *div_name; 77 int clk_id; 78 int clk_num; 79 u8 div_offset; 80 }; 81 82 #define AUDIO2X(_name, _num, _offset) \ 83 {\ 84 .parent = #_name,\ 85 .gate_name = #_name"_2x",\ 86 .name_2x = #_name"_doubler",\ 87 .div_name = #_name"_div",\ 88 .clk_id = tegra_clk_ ## _name ## _2x,\ 89 .clk_num = _num,\ 90 .div_offset = _offset,\ 91 } 92 93 static DEFINE_SPINLOCK(clk_doubler_lock); 94 95 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 96 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 97 }; 98 99 static struct tegra_sync_source_initdata sync_source_clks[] __initdata = { 100 SYNC(spdif_in_sync), 101 SYNC(i2s0_sync), 102 SYNC(i2s1_sync), 103 SYNC(i2s2_sync), 104 SYNC(i2s3_sync), 105 SYNC(i2s4_sync), 106 SYNC(vimclk_sync), 107 }; 108 109 static struct tegra_audio_clk_initdata audio_clks[] = { 110 AUDIO(audio0, AUDIO_SYNC_CLK_I2S0), 111 AUDIO(audio1, AUDIO_SYNC_CLK_I2S1), 112 AUDIO(audio2, AUDIO_SYNC_CLK_I2S2), 113 AUDIO(audio3, AUDIO_SYNC_CLK_I2S3), 114 AUDIO(audio4, AUDIO_SYNC_CLK_I2S4), 115 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF), 116 }; 117 118 static struct tegra_audio2x_clk_initdata audio2x_clks[] = { 119 AUDIO2X(audio0, 113, 24), 120 AUDIO2X(audio1, 114, 25), 121 AUDIO2X(audio2, 115, 26), 122 AUDIO2X(audio3, 116, 27), 123 AUDIO2X(audio4, 117, 28), 124 AUDIO2X(spdif, 118, 29), 125 }; 126 127 void __init tegra_audio_clk_init(void __iomem *clk_base, 128 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 129 struct tegra_clk_pll_params *pll_a_params) 130 { 131 struct clk *clk; 132 struct clk **dt_clk; 133 int i; 134 135 /* PLLA */ 136 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a, tegra_clks); 137 if (dt_clk) { 138 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, 139 pmc_base, 0, pll_a_params, NULL); 140 *dt_clk = clk; 141 } 142 143 /* PLLA_OUT0 */ 144 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks); 145 if (dt_clk) { 146 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 147 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 148 8, 8, 1, NULL); 149 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 150 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 151 CLK_SET_RATE_PARENT, 0, NULL); 152 *dt_clk = clk; 153 } 154 155 for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) { 156 struct tegra_sync_source_initdata *data; 157 158 data = &sync_source_clks[i]; 159 160 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 161 if (!dt_clk) 162 continue; 163 164 clk = tegra_clk_register_sync_source(data->name, 165 data->rate, data->max_rate); 166 *dt_clk = clk; 167 } 168 169 for (i = 0; i < ARRAY_SIZE(audio_clks); i++) { 170 struct tegra_audio_clk_initdata *data; 171 172 data = &audio_clks[i]; 173 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks); 174 175 if (!dt_clk) 176 continue; 177 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk, 178 ARRAY_SIZE(mux_audio_sync_clk), 179 CLK_SET_RATE_NO_REPARENT, 180 clk_base + data->offset, 0, 3, 0, 181 NULL); 182 *dt_clk = clk; 183 184 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks); 185 if (!dt_clk) 186 continue; 187 188 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, 189 0, clk_base + data->offset, 4, 190 CLK_GATE_SET_TO_DISABLE, NULL); 191 *dt_clk = clk; 192 } 193 194 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) { 195 struct tegra_audio2x_clk_initdata *data; 196 197 data = &audio2x_clks[i]; 198 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 199 if (!dt_clk) 200 continue; 201 202 clk = clk_register_fixed_factor(NULL, data->name_2x, 203 data->parent, CLK_SET_RATE_PARENT, 2, 1); 204 clk = tegra_clk_register_divider(data->div_name, 205 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER, 206 0, 0, data->div_offset, 1, 0, 207 &clk_doubler_lock); 208 clk = tegra_clk_register_periph_gate(data->gate_name, 209 data->div_name, TEGRA_PERIPH_NO_RESET, 210 clk_base, CLK_SET_RATE_PARENT, data->clk_num, 211 periph_clk_enb_refcnt); 212 *dt_clk = clk; 213 } 214 } 215 216