1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk-provider.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/delay.h> 22 #include <linux/export.h> 23 #include <linux/clk/tegra.h> 24 25 #include "clk.h" 26 #include "clk-id.h" 27 28 #define AUDIO_SYNC_CLK_I2S0 0x4a0 29 #define AUDIO_SYNC_CLK_I2S1 0x4a4 30 #define AUDIO_SYNC_CLK_I2S2 0x4a8 31 #define AUDIO_SYNC_CLK_I2S3 0x4ac 32 #define AUDIO_SYNC_CLK_I2S4 0x4b0 33 #define AUDIO_SYNC_CLK_SPDIF 0x4b4 34 #define AUDIO_SYNC_CLK_DMIC1 0x560 35 #define AUDIO_SYNC_CLK_DMIC2 0x564 36 #define AUDIO_SYNC_CLK_DMIC3 0x6b8 37 38 #define AUDIO_SYNC_DOUBLER 0x49c 39 40 #define PLLA_OUT 0xb4 41 42 struct tegra_sync_source_initdata { 43 char *name; 44 unsigned long rate; 45 unsigned long max_rate; 46 int clk_id; 47 }; 48 49 #define SYNC(_name) \ 50 {\ 51 .name = #_name,\ 52 .clk_id = tegra_clk_ ## _name,\ 53 } 54 55 struct tegra_audio_clk_initdata { 56 char *gate_name; 57 char *mux_name; 58 u32 offset; 59 int gate_clk_id; 60 int mux_clk_id; 61 }; 62 63 #define AUDIO(_name, _offset) \ 64 {\ 65 .gate_name = #_name,\ 66 .mux_name = #_name"_mux",\ 67 .offset = _offset,\ 68 .gate_clk_id = tegra_clk_ ## _name,\ 69 .mux_clk_id = tegra_clk_ ## _name ## _mux,\ 70 } 71 72 struct tegra_audio2x_clk_initdata { 73 char *parent; 74 char *gate_name; 75 char *name_2x; 76 char *div_name; 77 int clk_id; 78 int clk_num; 79 u8 div_offset; 80 }; 81 82 #define AUDIO2X(_name, _num, _offset) \ 83 {\ 84 .parent = #_name,\ 85 .gate_name = #_name"_2x",\ 86 .name_2x = #_name"_doubler",\ 87 .div_name = #_name"_div",\ 88 .clk_id = tegra_clk_ ## _name ## _2x,\ 89 .clk_num = _num,\ 90 .div_offset = _offset,\ 91 } 92 93 static DEFINE_SPINLOCK(clk_doubler_lock); 94 95 static const char * const mux_audio_sync_clk[] = { "spdif_in_sync", 96 "i2s0_sync", "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", 97 "pll_a_out0", "vimclk_sync", 98 }; 99 100 static const char * const mux_dmic_sync_clk[] = { "unused", "i2s0_sync", 101 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0", 102 "vimclk_sync", 103 }; 104 105 static struct tegra_sync_source_initdata sync_source_clks[] __initdata = { 106 SYNC(spdif_in_sync), 107 SYNC(i2s0_sync), 108 SYNC(i2s1_sync), 109 SYNC(i2s2_sync), 110 SYNC(i2s3_sync), 111 SYNC(i2s4_sync), 112 SYNC(vimclk_sync), 113 }; 114 115 static struct tegra_audio_clk_initdata audio_clks[] = { 116 AUDIO(audio0, AUDIO_SYNC_CLK_I2S0), 117 AUDIO(audio1, AUDIO_SYNC_CLK_I2S1), 118 AUDIO(audio2, AUDIO_SYNC_CLK_I2S2), 119 AUDIO(audio3, AUDIO_SYNC_CLK_I2S3), 120 AUDIO(audio4, AUDIO_SYNC_CLK_I2S4), 121 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF), 122 }; 123 124 static struct tegra_audio_clk_initdata dmic_clks[] = { 125 AUDIO(dmic1_sync_clk, AUDIO_SYNC_CLK_DMIC1), 126 AUDIO(dmic2_sync_clk, AUDIO_SYNC_CLK_DMIC2), 127 AUDIO(dmic3_sync_clk, AUDIO_SYNC_CLK_DMIC3), 128 }; 129 130 static struct tegra_audio2x_clk_initdata audio2x_clks[] = { 131 AUDIO2X(audio0, 113, 24), 132 AUDIO2X(audio1, 114, 25), 133 AUDIO2X(audio2, 115, 26), 134 AUDIO2X(audio3, 116, 27), 135 AUDIO2X(audio4, 117, 28), 136 AUDIO2X(spdif, 118, 29), 137 }; 138 139 static void __init tegra_audio_sync_clk_init(void __iomem *clk_base, 140 struct tegra_clk *tegra_clks, 141 struct tegra_audio_clk_initdata *sync, 142 int num_sync_clks, 143 const char * const *mux_names, 144 int num_mux_inputs) 145 { 146 struct clk *clk; 147 struct clk **dt_clk; 148 struct tegra_audio_clk_initdata *data; 149 int i; 150 151 for (i = 0, data = sync; i < num_sync_clks; i++, data++) { 152 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks); 153 if (!dt_clk) 154 continue; 155 156 clk = clk_register_mux(NULL, data->mux_name, mux_names, 157 num_mux_inputs, 158 CLK_SET_RATE_NO_REPARENT, 159 clk_base + data->offset, 0, 3, 0, 160 NULL); 161 *dt_clk = clk; 162 163 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks); 164 if (!dt_clk) 165 continue; 166 167 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, 168 0, clk_base + data->offset, 4, 169 CLK_GATE_SET_TO_DISABLE, NULL); 170 *dt_clk = clk; 171 } 172 } 173 174 void __init tegra_audio_clk_init(void __iomem *clk_base, 175 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 176 struct tegra_audio_clk_info *audio_info, 177 unsigned int num_plls, unsigned long sync_max_rate) 178 { 179 struct clk *clk; 180 struct clk **dt_clk; 181 int i; 182 183 if (!audio_info || num_plls < 1) { 184 pr_err("No audio data passed to tegra_audio_clk_init\n"); 185 WARN_ON(1); 186 return; 187 } 188 189 for (i = 0; i < num_plls; i++) { 190 struct tegra_audio_clk_info *info = &audio_info[i]; 191 192 dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks); 193 if (dt_clk) { 194 clk = tegra_clk_register_pll(info->name, info->parent, 195 clk_base, pmc_base, 0, info->pll_params, 196 NULL); 197 *dt_clk = clk; 198 } 199 } 200 201 /* PLLA_OUT0 */ 202 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks); 203 if (dt_clk) { 204 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 205 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 206 8, 8, 1, NULL); 207 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 208 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 209 CLK_SET_RATE_PARENT, 0, NULL); 210 *dt_clk = clk; 211 } 212 213 for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) { 214 struct tegra_sync_source_initdata *data; 215 216 data = &sync_source_clks[i]; 217 218 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 219 if (!dt_clk) 220 continue; 221 222 clk = tegra_clk_register_sync_source(data->name, sync_max_rate); 223 *dt_clk = clk; 224 } 225 226 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks, 227 ARRAY_SIZE(audio_clks), mux_audio_sync_clk, 228 ARRAY_SIZE(mux_audio_sync_clk)); 229 230 /* make sure the DMIC sync clocks have a valid parent */ 231 for (i = 0; i < ARRAY_SIZE(dmic_clks); i++) 232 writel_relaxed(1, clk_base + dmic_clks[i].offset); 233 234 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks, 235 ARRAY_SIZE(dmic_clks), mux_dmic_sync_clk, 236 ARRAY_SIZE(mux_dmic_sync_clk)); 237 238 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) { 239 struct tegra_audio2x_clk_initdata *data; 240 241 data = &audio2x_clks[i]; 242 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 243 if (!dt_clk) 244 continue; 245 246 clk = clk_register_fixed_factor(NULL, data->name_2x, 247 data->parent, CLK_SET_RATE_PARENT, 2, 1); 248 clk = tegra_clk_register_divider(data->div_name, 249 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER, 250 0, 0, data->div_offset, 1, 0, 251 &clk_doubler_lock); 252 clk = tegra_clk_register_periph_gate(data->gate_name, 253 data->div_name, TEGRA_PERIPH_NO_RESET, 254 clk_base, CLK_SET_RATE_PARENT, data->clk_num, 255 periph_clk_enb_refcnt); 256 *dt_clk = clk; 257 } 258 } 259 260