1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 69 #define PLLE_MISC_SETUP_BASE_SHIFT 16 70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 71 #define PLLE_MISC_LOCK_ENABLE BIT(9) 72 #define PLLE_MISC_READY BIT(15) 73 #define PLLE_MISC_SETUP_EX_SHIFT 2 74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 76 PLLE_MISC_SETUP_EX_MASK) 77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 78 79 #define PLLE_SS_CTRL 0x68 80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 82 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 83 #define PLLE_SS_CNTL_CENTER BIT(14) 84 #define PLLE_SS_CNTL_INVERT BIT(15) 85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 86 PLLE_SS_CNTL_SSC_BYP) 87 #define PLLE_SS_MAX_MASK 0x1ff 88 #define PLLE_SS_MAX_VAL 0x25 89 #define PLLE_SS_INC_MASK (0xff << 16) 90 #define PLLE_SS_INC_VAL (0x1 << 16) 91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 93 #define PLLE_SS_COEFFICIENTS_MASK \ 94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 95 #define PLLE_SS_COEFFICIENTS_VAL \ 96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 97 98 #define PLLE_AUX_PLLP_SEL BIT(2) 99 #define PLLE_AUX_USE_LOCKDET BIT(3) 100 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 101 #define PLLE_AUX_SS_SWCTL BIT(6) 102 #define PLLE_AUX_SEQ_ENABLE BIT(24) 103 #define PLLE_AUX_SEQ_START_STATE BIT(25) 104 #define PLLE_AUX_PLLRE_SEL BIT(28) 105 106 #define XUSBIO_PLL_CFG0 0x51c 107 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 108 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 109 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 110 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 111 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 112 113 #define SATA_PLL_CFG0 0x490 114 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 115 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 116 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 117 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 118 119 #define PLLE_MISC_PLLE_PTS BIT(8) 120 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 121 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 122 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 123 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 124 #define PLLE_MISC_VREG_CTRL_SHIFT 2 125 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 126 127 #define PLLCX_MISC_STROBE BIT(31) 128 #define PLLCX_MISC_RESET BIT(30) 129 #define PLLCX_MISC_SDM_DIV_SHIFT 28 130 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 131 #define PLLCX_MISC_FILT_DIV_SHIFT 26 132 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 133 #define PLLCX_MISC_ALPHA_SHIFT 18 134 #define PLLCX_MISC_DIV_LOW_RANGE \ 135 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 136 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 137 #define PLLCX_MISC_DIV_HIGH_RANGE \ 138 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 139 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 140 #define PLLCX_MISC_COEF_LOW_RANGE \ 141 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 142 #define PLLCX_MISC_KA_SHIFT 2 143 #define PLLCX_MISC_KB_SHIFT 9 144 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 145 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 146 PLLCX_MISC_DIV_LOW_RANGE | \ 147 PLLCX_MISC_RESET) 148 #define PLLCX_MISC1_DEFAULT 0x000d2308 149 #define PLLCX_MISC2_DEFAULT 0x30211200 150 #define PLLCX_MISC3_DEFAULT 0x200 151 152 #define PMC_SATA_PWRGT 0x1ac 153 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 154 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 155 156 #define PLLSS_MISC_KCP 0 157 #define PLLSS_MISC_KVCO 0 158 #define PLLSS_MISC_SETUP 0 159 #define PLLSS_EN_SDM 0 160 #define PLLSS_EN_SSC 0 161 #define PLLSS_EN_DITHER2 0 162 #define PLLSS_EN_DITHER 1 163 #define PLLSS_SDM_RESET 0 164 #define PLLSS_CLAMP 0 165 #define PLLSS_SDM_SSC_MAX 0 166 #define PLLSS_SDM_SSC_MIN 0 167 #define PLLSS_SDM_SSC_STEP 0 168 #define PLLSS_SDM_DIN 0 169 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 170 (PLLSS_MISC_KVCO << 24) | \ 171 PLLSS_MISC_SETUP) 172 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 173 (PLLSS_EN_SSC << 30) | \ 174 (PLLSS_EN_DITHER2 << 29) | \ 175 (PLLSS_EN_DITHER << 28) | \ 176 (PLLSS_SDM_RESET) << 27 | \ 177 (PLLSS_CLAMP << 22)) 178 #define PLLSS_CTRL1_DEFAULT \ 179 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 180 #define PLLSS_CTRL2_DEFAULT \ 181 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 182 #define PLLSS_LOCK_OVERRIDE BIT(24) 183 #define PLLSS_REF_SRC_SEL_SHIFT 25 184 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 185 186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 187 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 188 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 189 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 190 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p) 191 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p) 192 193 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 194 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 195 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 196 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 197 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) 198 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) 199 200 #define mask(w) ((1 << (w)) - 1) 201 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 202 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 203 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 204 mask(p->params->div_nmp->divp_width)) 205 #define sdm_din_mask(p) p->params->sdm_din_mask 206 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask 207 208 #define divm_shift(p) (p)->params->div_nmp->divm_shift 209 #define divn_shift(p) (p)->params->div_nmp->divn_shift 210 #define divp_shift(p) (p)->params->div_nmp->divp_shift 211 212 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 213 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 214 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 215 216 #define divm_max(p) (divm_mask(p)) 217 #define divn_max(p) (divn_mask(p)) 218 #define divp_max(p) (1 << (divp_mask(p))) 219 220 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 221 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 222 223 static struct div_nmp default_nmp = { 224 .divn_shift = PLL_BASE_DIVN_SHIFT, 225 .divn_width = PLL_BASE_DIVN_WIDTH, 226 .divm_shift = PLL_BASE_DIVM_SHIFT, 227 .divm_width = PLL_BASE_DIVM_WIDTH, 228 .divp_shift = PLL_BASE_DIVP_SHIFT, 229 .divp_width = PLL_BASE_DIVP_WIDTH, 230 }; 231 232 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 233 { 234 u32 val; 235 236 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 237 return; 238 239 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 240 return; 241 242 val = pll_readl_misc(pll); 243 val |= BIT(pll->params->lock_enable_bit_idx); 244 pll_writel_misc(val, pll); 245 } 246 247 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 248 { 249 int i; 250 u32 val, lock_mask; 251 void __iomem *lock_addr; 252 253 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 254 udelay(pll->params->lock_delay); 255 return 0; 256 } 257 258 lock_addr = pll->clk_base; 259 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 260 lock_addr += pll->params->misc_reg; 261 else 262 lock_addr += pll->params->base_reg; 263 264 lock_mask = pll->params->lock_mask; 265 266 for (i = 0; i < pll->params->lock_delay; i++) { 267 val = readl_relaxed(lock_addr); 268 if ((val & lock_mask) == lock_mask) { 269 udelay(PLL_POST_LOCK_DELAY); 270 return 0; 271 } 272 udelay(2); /* timeout = 2 * lock time */ 273 } 274 275 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 276 clk_hw_get_name(&pll->hw)); 277 278 return -1; 279 } 280 281 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 282 { 283 return clk_pll_wait_for_lock(pll); 284 } 285 286 static int clk_pll_is_enabled(struct clk_hw *hw) 287 { 288 struct tegra_clk_pll *pll = to_clk_pll(hw); 289 u32 val; 290 291 if (pll->params->flags & TEGRA_PLLM) { 292 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 293 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 294 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 295 } 296 297 val = pll_readl_base(pll); 298 299 return val & PLL_BASE_ENABLE ? 1 : 0; 300 } 301 302 static void _clk_pll_enable(struct clk_hw *hw) 303 { 304 struct tegra_clk_pll *pll = to_clk_pll(hw); 305 u32 val; 306 307 if (pll->params->iddq_reg) { 308 val = pll_readl(pll->params->iddq_reg, pll); 309 val &= ~BIT(pll->params->iddq_bit_idx); 310 pll_writel(val, pll->params->iddq_reg, pll); 311 udelay(2); 312 } 313 314 clk_pll_enable_lock(pll); 315 316 val = pll_readl_base(pll); 317 if (pll->params->flags & TEGRA_PLL_BYPASS) 318 val &= ~PLL_BASE_BYPASS; 319 val |= PLL_BASE_ENABLE; 320 pll_writel_base(val, pll); 321 322 if (pll->params->flags & TEGRA_PLLM) { 323 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 324 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 325 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 326 } 327 } 328 329 static void _clk_pll_disable(struct clk_hw *hw) 330 { 331 struct tegra_clk_pll *pll = to_clk_pll(hw); 332 u32 val; 333 334 val = pll_readl_base(pll); 335 if (pll->params->flags & TEGRA_PLL_BYPASS) 336 val &= ~PLL_BASE_BYPASS; 337 val &= ~PLL_BASE_ENABLE; 338 pll_writel_base(val, pll); 339 340 if (pll->params->flags & TEGRA_PLLM) { 341 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 342 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 343 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 344 } 345 346 if (pll->params->iddq_reg) { 347 val = pll_readl(pll->params->iddq_reg, pll); 348 val |= BIT(pll->params->iddq_bit_idx); 349 pll_writel(val, pll->params->iddq_reg, pll); 350 udelay(2); 351 } 352 } 353 354 static int clk_pll_enable(struct clk_hw *hw) 355 { 356 struct tegra_clk_pll *pll = to_clk_pll(hw); 357 unsigned long flags = 0; 358 int ret; 359 360 if (pll->lock) 361 spin_lock_irqsave(pll->lock, flags); 362 363 _clk_pll_enable(hw); 364 365 ret = clk_pll_wait_for_lock(pll); 366 367 if (pll->lock) 368 spin_unlock_irqrestore(pll->lock, flags); 369 370 return ret; 371 } 372 373 static void clk_pll_disable(struct clk_hw *hw) 374 { 375 struct tegra_clk_pll *pll = to_clk_pll(hw); 376 unsigned long flags = 0; 377 378 if (pll->lock) 379 spin_lock_irqsave(pll->lock, flags); 380 381 _clk_pll_disable(hw); 382 383 if (pll->lock) 384 spin_unlock_irqrestore(pll->lock, flags); 385 } 386 387 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 388 { 389 struct tegra_clk_pll *pll = to_clk_pll(hw); 390 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 391 392 if (p_tohw) { 393 while (p_tohw->pdiv) { 394 if (p_div <= p_tohw->pdiv) 395 return p_tohw->hw_val; 396 p_tohw++; 397 } 398 return -EINVAL; 399 } 400 return -EINVAL; 401 } 402 403 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 404 { 405 struct tegra_clk_pll *pll = to_clk_pll(hw); 406 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 407 408 if (p_tohw) { 409 while (p_tohw->pdiv) { 410 if (p_div_hw == p_tohw->hw_val) 411 return p_tohw->pdiv; 412 p_tohw++; 413 } 414 return -EINVAL; 415 } 416 417 return 1 << p_div_hw; 418 } 419 420 static int _get_table_rate(struct clk_hw *hw, 421 struct tegra_clk_pll_freq_table *cfg, 422 unsigned long rate, unsigned long parent_rate) 423 { 424 struct tegra_clk_pll *pll = to_clk_pll(hw); 425 struct tegra_clk_pll_freq_table *sel; 426 427 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 428 if (sel->input_rate == parent_rate && 429 sel->output_rate == rate) 430 break; 431 432 if (sel->input_rate == 0) 433 return -EINVAL; 434 435 cfg->input_rate = sel->input_rate; 436 cfg->output_rate = sel->output_rate; 437 cfg->m = sel->m; 438 cfg->n = sel->n; 439 cfg->p = sel->p; 440 cfg->cpcon = sel->cpcon; 441 cfg->sdm_data = sel->sdm_data; 442 443 return 0; 444 } 445 446 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 447 unsigned long rate, unsigned long parent_rate) 448 { 449 struct tegra_clk_pll *pll = to_clk_pll(hw); 450 unsigned long cfreq; 451 u32 p_div = 0; 452 int ret; 453 454 switch (parent_rate) { 455 case 12000000: 456 case 26000000: 457 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 458 break; 459 case 13000000: 460 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 461 break; 462 case 16800000: 463 case 19200000: 464 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 465 break; 466 case 9600000: 467 case 28800000: 468 /* 469 * PLL_P_OUT1 rate is not listed in PLLA table 470 */ 471 cfreq = parent_rate / (parent_rate / 1000000); 472 break; 473 default: 474 pr_err("%s Unexpected reference rate %lu\n", 475 __func__, parent_rate); 476 BUG(); 477 } 478 479 /* Raise VCO to guarantee 0.5% accuracy */ 480 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 481 cfg->output_rate <<= 1) 482 p_div++; 483 484 cfg->m = parent_rate / cfreq; 485 cfg->n = cfg->output_rate / cfreq; 486 cfg->cpcon = OUT_OF_TABLE_CPCON; 487 488 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 489 (1 << p_div) > divp_max(pll) 490 || cfg->output_rate > pll->params->vco_max) { 491 return -EINVAL; 492 } 493 494 cfg->output_rate >>= p_div; 495 496 if (pll->params->pdiv_tohw) { 497 ret = _p_div_to_hw(hw, 1 << p_div); 498 if (ret < 0) 499 return ret; 500 else 501 cfg->p = ret; 502 } else 503 cfg->p = p_div; 504 505 return 0; 506 } 507 508 /* 509 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number 510 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as 511 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used 512 * to indicate that SDM is disabled. 513 * 514 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 515 */ 516 static void clk_pll_set_sdm_data(struct clk_hw *hw, 517 struct tegra_clk_pll_freq_table *cfg) 518 { 519 struct tegra_clk_pll *pll = to_clk_pll(hw); 520 u32 val; 521 bool enabled; 522 523 if (!pll->params->sdm_din_reg) 524 return; 525 526 if (cfg->sdm_data) { 527 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); 528 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); 529 pll_writel_sdm_din(val, pll); 530 } 531 532 val = pll_readl_sdm_ctrl(pll); 533 enabled = (val & sdm_en_mask(pll)); 534 535 if (cfg->sdm_data == 0 && enabled) 536 val &= ~pll->params->sdm_ctrl_en_mask; 537 538 if (cfg->sdm_data != 0 && !enabled) 539 val |= pll->params->sdm_ctrl_en_mask; 540 541 pll_writel_sdm_ctrl(val, pll); 542 } 543 544 static void _update_pll_mnp(struct tegra_clk_pll *pll, 545 struct tegra_clk_pll_freq_table *cfg) 546 { 547 u32 val; 548 struct tegra_clk_pll_params *params = pll->params; 549 struct div_nmp *div_nmp = params->div_nmp; 550 551 if ((params->flags & TEGRA_PLLM) && 552 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 553 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 554 val = pll_override_readl(params->pmc_divp_reg, pll); 555 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 556 val |= cfg->p << div_nmp->override_divp_shift; 557 pll_override_writel(val, params->pmc_divp_reg, pll); 558 559 val = pll_override_readl(params->pmc_divnm_reg, pll); 560 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | 561 ~(divn_mask(pll) << div_nmp->override_divn_shift); 562 val |= (cfg->m << div_nmp->override_divm_shift) | 563 (cfg->n << div_nmp->override_divn_shift); 564 pll_override_writel(val, params->pmc_divnm_reg, pll); 565 } else { 566 val = pll_readl_base(pll); 567 568 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 569 divp_mask_shifted(pll)); 570 571 val |= (cfg->m << divm_shift(pll)) | 572 (cfg->n << divn_shift(pll)) | 573 (cfg->p << divp_shift(pll)); 574 575 pll_writel_base(val, pll); 576 577 clk_pll_set_sdm_data(&pll->hw, cfg); 578 } 579 } 580 581 static void _get_pll_mnp(struct tegra_clk_pll *pll, 582 struct tegra_clk_pll_freq_table *cfg) 583 { 584 u32 val; 585 struct tegra_clk_pll_params *params = pll->params; 586 struct div_nmp *div_nmp = params->div_nmp; 587 588 if ((params->flags & TEGRA_PLLM) && 589 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 590 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 591 val = pll_override_readl(params->pmc_divp_reg, pll); 592 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 593 594 val = pll_override_readl(params->pmc_divnm_reg, pll); 595 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 596 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 597 } else { 598 val = pll_readl_base(pll); 599 600 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 601 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 602 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 603 604 if (pll->params->sdm_din_reg) { 605 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { 606 val = pll_readl_sdm_din(pll); 607 val &= sdm_din_mask(pll); 608 cfg->sdm_data = sdin_din_to_data(val); 609 } 610 } 611 } 612 } 613 614 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 615 struct tegra_clk_pll_freq_table *cfg, 616 unsigned long rate) 617 { 618 u32 val; 619 620 val = pll_readl_misc(pll); 621 622 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 623 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 624 625 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 626 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 627 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 628 val |= 1 << PLL_MISC_LFCON_SHIFT; 629 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 630 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 631 if (rate >= (pll->params->vco_max >> 1)) 632 val |= 1 << PLL_MISC_DCCON_SHIFT; 633 } 634 635 pll_writel_misc(val, pll); 636 } 637 638 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 639 unsigned long rate) 640 { 641 struct tegra_clk_pll *pll = to_clk_pll(hw); 642 int state, ret = 0; 643 644 state = clk_pll_is_enabled(hw); 645 646 if (state) 647 _clk_pll_disable(hw); 648 649 _update_pll_mnp(pll, cfg); 650 651 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 652 _update_pll_cpcon(pll, cfg, rate); 653 654 if (state) { 655 _clk_pll_enable(hw); 656 ret = clk_pll_wait_for_lock(pll); 657 } 658 659 return ret; 660 } 661 662 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 663 unsigned long parent_rate) 664 { 665 struct tegra_clk_pll *pll = to_clk_pll(hw); 666 struct tegra_clk_pll_freq_table cfg, old_cfg; 667 unsigned long flags = 0; 668 int ret = 0; 669 670 if (pll->params->flags & TEGRA_PLL_FIXED) { 671 if (rate != pll->params->fixed_rate) { 672 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 673 __func__, clk_hw_get_name(hw), 674 pll->params->fixed_rate, rate); 675 return -EINVAL; 676 } 677 return 0; 678 } 679 680 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 681 _calc_rate(hw, &cfg, rate, parent_rate)) { 682 pr_err("%s: Failed to set %s rate %lu\n", __func__, 683 clk_hw_get_name(hw), rate); 684 WARN_ON(1); 685 return -EINVAL; 686 } 687 if (pll->lock) 688 spin_lock_irqsave(pll->lock, flags); 689 690 _get_pll_mnp(pll, &old_cfg); 691 692 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || 693 old_cfg.sdm_data != cfg.sdm_data) 694 ret = _program_pll(hw, &cfg, rate); 695 696 if (pll->lock) 697 spin_unlock_irqrestore(pll->lock, flags); 698 699 return ret; 700 } 701 702 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 703 unsigned long *prate) 704 { 705 struct tegra_clk_pll *pll = to_clk_pll(hw); 706 struct tegra_clk_pll_freq_table cfg; 707 708 if (pll->params->flags & TEGRA_PLL_FIXED) 709 return pll->params->fixed_rate; 710 711 /* PLLM is used for memory; we do not change rate */ 712 if (pll->params->flags & TEGRA_PLLM) 713 return clk_hw_get_rate(hw); 714 715 if (_get_table_rate(hw, &cfg, rate, *prate) && 716 _calc_rate(hw, &cfg, rate, *prate)) 717 return -EINVAL; 718 719 return cfg.output_rate; 720 } 721 722 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 723 unsigned long parent_rate) 724 { 725 struct tegra_clk_pll *pll = to_clk_pll(hw); 726 struct tegra_clk_pll_freq_table cfg; 727 u32 val; 728 u64 rate = parent_rate; 729 int pdiv; 730 731 val = pll_readl_base(pll); 732 733 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 734 return parent_rate; 735 736 if ((pll->params->flags & TEGRA_PLL_FIXED) && 737 !(val & PLL_BASE_OVERRIDE)) { 738 struct tegra_clk_pll_freq_table sel; 739 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 740 parent_rate)) { 741 pr_err("Clock %s has unknown fixed frequency\n", 742 clk_hw_get_name(hw)); 743 BUG(); 744 } 745 return pll->params->fixed_rate; 746 } 747 748 _get_pll_mnp(pll, &cfg); 749 750 pdiv = _hw_to_p_div(hw, cfg.p); 751 if (pdiv < 0) { 752 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 753 __clk_get_name(hw->clk), cfg.p); 754 pdiv = 1; 755 } 756 757 if (pll->params->set_gain) 758 pll->params->set_gain(&cfg); 759 760 cfg.m *= pdiv; 761 762 rate *= cfg.n; 763 do_div(rate, cfg.m); 764 765 return rate; 766 } 767 768 static int clk_plle_training(struct tegra_clk_pll *pll) 769 { 770 u32 val; 771 unsigned long timeout; 772 773 if (!pll->pmc) 774 return -ENOSYS; 775 776 /* 777 * PLLE is already disabled, and setup cleared; 778 * create falling edge on PLLE IDDQ input. 779 */ 780 val = readl(pll->pmc + PMC_SATA_PWRGT); 781 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 782 writel(val, pll->pmc + PMC_SATA_PWRGT); 783 784 val = readl(pll->pmc + PMC_SATA_PWRGT); 785 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 786 writel(val, pll->pmc + PMC_SATA_PWRGT); 787 788 val = readl(pll->pmc + PMC_SATA_PWRGT); 789 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 790 writel(val, pll->pmc + PMC_SATA_PWRGT); 791 792 val = pll_readl_misc(pll); 793 794 timeout = jiffies + msecs_to_jiffies(100); 795 while (1) { 796 val = pll_readl_misc(pll); 797 if (val & PLLE_MISC_READY) 798 break; 799 if (time_after(jiffies, timeout)) { 800 pr_err("%s: timeout waiting for PLLE\n", __func__); 801 return -EBUSY; 802 } 803 udelay(300); 804 } 805 806 return 0; 807 } 808 809 static int clk_plle_enable(struct clk_hw *hw) 810 { 811 struct tegra_clk_pll *pll = to_clk_pll(hw); 812 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 813 struct tegra_clk_pll_freq_table sel; 814 u32 val; 815 int err; 816 817 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 818 return -EINVAL; 819 820 clk_pll_disable(hw); 821 822 val = pll_readl_misc(pll); 823 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 824 pll_writel_misc(val, pll); 825 826 val = pll_readl_misc(pll); 827 if (!(val & PLLE_MISC_READY)) { 828 err = clk_plle_training(pll); 829 if (err) 830 return err; 831 } 832 833 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 834 /* configure dividers */ 835 val = pll_readl_base(pll); 836 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 837 divm_mask_shifted(pll)); 838 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 839 val |= sel.m << divm_shift(pll); 840 val |= sel.n << divn_shift(pll); 841 val |= sel.p << divp_shift(pll); 842 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 843 pll_writel_base(val, pll); 844 } 845 846 val = pll_readl_misc(pll); 847 val |= PLLE_MISC_SETUP_VALUE; 848 val |= PLLE_MISC_LOCK_ENABLE; 849 pll_writel_misc(val, pll); 850 851 val = readl(pll->clk_base + PLLE_SS_CTRL); 852 val &= ~PLLE_SS_COEFFICIENTS_MASK; 853 val |= PLLE_SS_DISABLE; 854 writel(val, pll->clk_base + PLLE_SS_CTRL); 855 856 val = pll_readl_base(pll); 857 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 858 pll_writel_base(val, pll); 859 860 clk_pll_wait_for_lock(pll); 861 862 return 0; 863 } 864 865 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 866 unsigned long parent_rate) 867 { 868 struct tegra_clk_pll *pll = to_clk_pll(hw); 869 u32 val = pll_readl_base(pll); 870 u32 divn = 0, divm = 0, divp = 0; 871 u64 rate = parent_rate; 872 873 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 874 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 875 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 876 divm *= divp; 877 878 rate *= divn; 879 do_div(rate, divm); 880 return rate; 881 } 882 883 const struct clk_ops tegra_clk_pll_ops = { 884 .is_enabled = clk_pll_is_enabled, 885 .enable = clk_pll_enable, 886 .disable = clk_pll_disable, 887 .recalc_rate = clk_pll_recalc_rate, 888 .round_rate = clk_pll_round_rate, 889 .set_rate = clk_pll_set_rate, 890 }; 891 892 const struct clk_ops tegra_clk_plle_ops = { 893 .recalc_rate = clk_plle_recalc_rate, 894 .is_enabled = clk_pll_is_enabled, 895 .disable = clk_pll_disable, 896 .enable = clk_plle_enable, 897 }; 898 899 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 900 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 901 defined(CONFIG_ARCH_TEGRA_132_SOC) 902 903 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 904 unsigned long parent_rate) 905 { 906 if (parent_rate > pll_params->cf_max) 907 return 2; 908 else 909 return 1; 910 } 911 912 static unsigned long _clip_vco_min(unsigned long vco_min, 913 unsigned long parent_rate) 914 { 915 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 916 } 917 918 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 919 void __iomem *clk_base, 920 unsigned long parent_rate) 921 { 922 u32 val; 923 u32 step_a, step_b; 924 925 switch (parent_rate) { 926 case 12000000: 927 case 13000000: 928 case 26000000: 929 step_a = 0x2B; 930 step_b = 0x0B; 931 break; 932 case 16800000: 933 step_a = 0x1A; 934 step_b = 0x09; 935 break; 936 case 19200000: 937 step_a = 0x12; 938 step_b = 0x08; 939 break; 940 default: 941 pr_err("%s: Unexpected reference rate %lu\n", 942 __func__, parent_rate); 943 WARN_ON(1); 944 return -EINVAL; 945 } 946 947 val = step_a << pll_params->stepa_shift; 948 val |= step_b << pll_params->stepb_shift; 949 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 950 951 return 0; 952 } 953 954 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 955 struct tegra_clk_pll_freq_table *cfg, 956 unsigned long rate, unsigned long parent_rate) 957 { 958 struct tegra_clk_pll *pll = to_clk_pll(hw); 959 unsigned int p; 960 int p_div; 961 962 if (!rate) 963 return -EINVAL; 964 965 p = DIV_ROUND_UP(pll->params->vco_min, rate); 966 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 967 cfg->output_rate = rate * p; 968 cfg->n = cfg->output_rate * cfg->m / parent_rate; 969 970 p_div = _p_div_to_hw(hw, p); 971 if (p_div < 0) 972 return p_div; 973 974 cfg->p = p_div; 975 976 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 977 return -EINVAL; 978 979 return 0; 980 } 981 982 static int _pll_ramp_calc_pll(struct clk_hw *hw, 983 struct tegra_clk_pll_freq_table *cfg, 984 unsigned long rate, unsigned long parent_rate) 985 { 986 struct tegra_clk_pll *pll = to_clk_pll(hw); 987 int err = 0, p_div; 988 989 err = _get_table_rate(hw, cfg, rate, parent_rate); 990 if (err < 0) 991 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 992 else { 993 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 994 WARN_ON(1); 995 err = -EINVAL; 996 goto out; 997 } 998 p_div = _p_div_to_hw(hw, cfg->p); 999 if (p_div < 0) 1000 return p_div; 1001 else 1002 cfg->p = p_div; 1003 } 1004 1005 if (cfg->p > pll->params->max_p) 1006 err = -EINVAL; 1007 1008 out: 1009 return err; 1010 } 1011 1012 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 1013 unsigned long parent_rate) 1014 { 1015 struct tegra_clk_pll *pll = to_clk_pll(hw); 1016 struct tegra_clk_pll_freq_table cfg, old_cfg; 1017 unsigned long flags = 0; 1018 int ret; 1019 1020 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1021 if (ret < 0) 1022 return ret; 1023 1024 if (pll->lock) 1025 spin_lock_irqsave(pll->lock, flags); 1026 1027 _get_pll_mnp(pll, &old_cfg); 1028 1029 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1030 ret = _program_pll(hw, &cfg, rate); 1031 1032 if (pll->lock) 1033 spin_unlock_irqrestore(pll->lock, flags); 1034 1035 return ret; 1036 } 1037 1038 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 1039 unsigned long *prate) 1040 { 1041 struct tegra_clk_pll *pll = to_clk_pll(hw); 1042 struct tegra_clk_pll_freq_table cfg; 1043 int ret, p_div; 1044 u64 output_rate = *prate; 1045 1046 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1047 if (ret < 0) 1048 return ret; 1049 1050 p_div = _hw_to_p_div(hw, cfg.p); 1051 if (p_div < 0) 1052 return p_div; 1053 1054 if (pll->params->set_gain) 1055 pll->params->set_gain(&cfg); 1056 1057 output_rate *= cfg.n; 1058 do_div(output_rate, cfg.m * p_div); 1059 1060 return output_rate; 1061 } 1062 1063 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, 1064 unsigned long parent_rate) 1065 { 1066 struct tegra_clk_pll_freq_table cfg; 1067 struct tegra_clk_pll *pll = to_clk_pll(hw); 1068 unsigned long flags = 0; 1069 int state, ret = 0; 1070 1071 if (pll->lock) 1072 spin_lock_irqsave(pll->lock, flags); 1073 1074 state = clk_pll_is_enabled(hw); 1075 if (state) { 1076 if (rate != clk_get_rate(hw->clk)) { 1077 pr_err("%s: Cannot change active PLLM\n", __func__); 1078 ret = -EINVAL; 1079 goto out; 1080 } 1081 goto out; 1082 } 1083 1084 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1085 if (ret < 0) 1086 goto out; 1087 1088 _update_pll_mnp(pll, &cfg); 1089 1090 out: 1091 if (pll->lock) 1092 spin_unlock_irqrestore(pll->lock, flags); 1093 1094 return ret; 1095 } 1096 1097 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1098 { 1099 u32 val; 1100 1101 val = pll_readl_misc(pll); 1102 val |= PLLCX_MISC_STROBE; 1103 pll_writel_misc(val, pll); 1104 udelay(2); 1105 1106 val &= ~PLLCX_MISC_STROBE; 1107 pll_writel_misc(val, pll); 1108 } 1109 1110 static int clk_pllc_enable(struct clk_hw *hw) 1111 { 1112 struct tegra_clk_pll *pll = to_clk_pll(hw); 1113 u32 val; 1114 int ret; 1115 unsigned long flags = 0; 1116 1117 if (pll->lock) 1118 spin_lock_irqsave(pll->lock, flags); 1119 1120 _clk_pll_enable(hw); 1121 udelay(2); 1122 1123 val = pll_readl_misc(pll); 1124 val &= ~PLLCX_MISC_RESET; 1125 pll_writel_misc(val, pll); 1126 udelay(2); 1127 1128 _pllcx_strobe(pll); 1129 1130 ret = clk_pll_wait_for_lock(pll); 1131 1132 if (pll->lock) 1133 spin_unlock_irqrestore(pll->lock, flags); 1134 1135 return ret; 1136 } 1137 1138 static void _clk_pllc_disable(struct clk_hw *hw) 1139 { 1140 struct tegra_clk_pll *pll = to_clk_pll(hw); 1141 u32 val; 1142 1143 _clk_pll_disable(hw); 1144 1145 val = pll_readl_misc(pll); 1146 val |= PLLCX_MISC_RESET; 1147 pll_writel_misc(val, pll); 1148 udelay(2); 1149 } 1150 1151 static void clk_pllc_disable(struct clk_hw *hw) 1152 { 1153 struct tegra_clk_pll *pll = to_clk_pll(hw); 1154 unsigned long flags = 0; 1155 1156 if (pll->lock) 1157 spin_lock_irqsave(pll->lock, flags); 1158 1159 _clk_pllc_disable(hw); 1160 1161 if (pll->lock) 1162 spin_unlock_irqrestore(pll->lock, flags); 1163 } 1164 1165 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1166 unsigned long input_rate, u32 n) 1167 { 1168 u32 val, n_threshold; 1169 1170 switch (input_rate) { 1171 case 12000000: 1172 n_threshold = 70; 1173 break; 1174 case 13000000: 1175 case 26000000: 1176 n_threshold = 71; 1177 break; 1178 case 16800000: 1179 n_threshold = 55; 1180 break; 1181 case 19200000: 1182 n_threshold = 48; 1183 break; 1184 default: 1185 pr_err("%s: Unexpected reference rate %lu\n", 1186 __func__, input_rate); 1187 return -EINVAL; 1188 } 1189 1190 val = pll_readl_misc(pll); 1191 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1192 val |= n <= n_threshold ? 1193 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1194 pll_writel_misc(val, pll); 1195 1196 return 0; 1197 } 1198 1199 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1200 unsigned long parent_rate) 1201 { 1202 struct tegra_clk_pll_freq_table cfg, old_cfg; 1203 struct tegra_clk_pll *pll = to_clk_pll(hw); 1204 unsigned long flags = 0; 1205 int state, ret = 0; 1206 1207 if (pll->lock) 1208 spin_lock_irqsave(pll->lock, flags); 1209 1210 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1211 if (ret < 0) 1212 goto out; 1213 1214 _get_pll_mnp(pll, &old_cfg); 1215 1216 if (cfg.m != old_cfg.m) { 1217 WARN_ON(1); 1218 goto out; 1219 } 1220 1221 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1222 goto out; 1223 1224 state = clk_pll_is_enabled(hw); 1225 if (state) 1226 _clk_pllc_disable(hw); 1227 1228 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1229 if (ret < 0) 1230 goto out; 1231 1232 _update_pll_mnp(pll, &cfg); 1233 1234 if (state) 1235 ret = clk_pllc_enable(hw); 1236 1237 out: 1238 if (pll->lock) 1239 spin_unlock_irqrestore(pll->lock, flags); 1240 1241 return ret; 1242 } 1243 1244 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1245 struct tegra_clk_pll_freq_table *cfg, 1246 unsigned long rate, unsigned long parent_rate) 1247 { 1248 u16 m, n; 1249 u64 output_rate = parent_rate; 1250 1251 m = _pll_fixed_mdiv(pll->params, parent_rate); 1252 n = rate * m / parent_rate; 1253 1254 output_rate *= n; 1255 do_div(output_rate, m); 1256 1257 if (cfg) { 1258 cfg->m = m; 1259 cfg->n = n; 1260 } 1261 1262 return output_rate; 1263 } 1264 1265 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1266 unsigned long parent_rate) 1267 { 1268 struct tegra_clk_pll_freq_table cfg, old_cfg; 1269 struct tegra_clk_pll *pll = to_clk_pll(hw); 1270 unsigned long flags = 0; 1271 int state, ret = 0; 1272 1273 if (pll->lock) 1274 spin_lock_irqsave(pll->lock, flags); 1275 1276 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1277 _get_pll_mnp(pll, &old_cfg); 1278 cfg.p = old_cfg.p; 1279 1280 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1281 state = clk_pll_is_enabled(hw); 1282 if (state) 1283 _clk_pll_disable(hw); 1284 1285 _update_pll_mnp(pll, &cfg); 1286 1287 if (state) { 1288 _clk_pll_enable(hw); 1289 ret = clk_pll_wait_for_lock(pll); 1290 } 1291 } 1292 1293 if (pll->lock) 1294 spin_unlock_irqrestore(pll->lock, flags); 1295 1296 return ret; 1297 } 1298 1299 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1300 unsigned long parent_rate) 1301 { 1302 struct tegra_clk_pll_freq_table cfg; 1303 struct tegra_clk_pll *pll = to_clk_pll(hw); 1304 u64 rate = parent_rate; 1305 1306 _get_pll_mnp(pll, &cfg); 1307 1308 rate *= cfg.n; 1309 do_div(rate, cfg.m); 1310 1311 return rate; 1312 } 1313 1314 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1315 unsigned long *prate) 1316 { 1317 struct tegra_clk_pll *pll = to_clk_pll(hw); 1318 1319 return _pllre_calc_rate(pll, NULL, rate, *prate); 1320 } 1321 1322 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1323 { 1324 struct tegra_clk_pll *pll = to_clk_pll(hw); 1325 struct tegra_clk_pll_freq_table sel; 1326 u32 val; 1327 int ret; 1328 unsigned long flags = 0; 1329 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1330 1331 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1332 return -EINVAL; 1333 1334 if (pll->lock) 1335 spin_lock_irqsave(pll->lock, flags); 1336 1337 val = pll_readl_base(pll); 1338 val &= ~BIT(29); /* Disable lock override */ 1339 pll_writel_base(val, pll); 1340 1341 val = pll_readl(pll->params->aux_reg, pll); 1342 val |= PLLE_AUX_ENABLE_SWCTL; 1343 val &= ~PLLE_AUX_SEQ_ENABLE; 1344 pll_writel(val, pll->params->aux_reg, pll); 1345 udelay(1); 1346 1347 val = pll_readl_misc(pll); 1348 val |= PLLE_MISC_LOCK_ENABLE; 1349 val |= PLLE_MISC_IDDQ_SW_CTRL; 1350 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1351 val |= PLLE_MISC_PLLE_PTS; 1352 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1353 pll_writel_misc(val, pll); 1354 udelay(5); 1355 1356 val = pll_readl(PLLE_SS_CTRL, pll); 1357 val |= PLLE_SS_DISABLE; 1358 pll_writel(val, PLLE_SS_CTRL, pll); 1359 1360 val = pll_readl_base(pll); 1361 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1362 divm_mask_shifted(pll)); 1363 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1364 val |= sel.m << divm_shift(pll); 1365 val |= sel.n << divn_shift(pll); 1366 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1367 pll_writel_base(val, pll); 1368 udelay(1); 1369 1370 _clk_pll_enable(hw); 1371 ret = clk_pll_wait_for_lock(pll); 1372 1373 if (ret < 0) 1374 goto out; 1375 1376 val = pll_readl(PLLE_SS_CTRL, pll); 1377 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1378 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1379 val |= PLLE_SS_COEFFICIENTS_VAL; 1380 pll_writel(val, PLLE_SS_CTRL, pll); 1381 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1382 pll_writel(val, PLLE_SS_CTRL, pll); 1383 udelay(1); 1384 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1385 pll_writel(val, PLLE_SS_CTRL, pll); 1386 udelay(1); 1387 1388 /* Enable hw control of xusb brick pll */ 1389 val = pll_readl_misc(pll); 1390 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1391 pll_writel_misc(val, pll); 1392 1393 val = pll_readl(pll->params->aux_reg, pll); 1394 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1395 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1396 pll_writel(val, pll->params->aux_reg, pll); 1397 udelay(1); 1398 val |= PLLE_AUX_SEQ_ENABLE; 1399 pll_writel(val, pll->params->aux_reg, pll); 1400 1401 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1402 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1403 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1404 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1405 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1406 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1407 udelay(1); 1408 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1409 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1410 1411 /* Enable hw control of SATA pll */ 1412 val = pll_readl(SATA_PLL_CFG0, pll); 1413 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1414 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1415 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1416 pll_writel(val, SATA_PLL_CFG0, pll); 1417 1418 udelay(1); 1419 1420 val = pll_readl(SATA_PLL_CFG0, pll); 1421 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1422 pll_writel(val, SATA_PLL_CFG0, pll); 1423 1424 out: 1425 if (pll->lock) 1426 spin_unlock_irqrestore(pll->lock, flags); 1427 1428 return ret; 1429 } 1430 1431 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1432 { 1433 struct tegra_clk_pll *pll = to_clk_pll(hw); 1434 unsigned long flags = 0; 1435 u32 val; 1436 1437 if (pll->lock) 1438 spin_lock_irqsave(pll->lock, flags); 1439 1440 _clk_pll_disable(hw); 1441 1442 val = pll_readl_misc(pll); 1443 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1444 pll_writel_misc(val, pll); 1445 udelay(1); 1446 1447 if (pll->lock) 1448 spin_unlock_irqrestore(pll->lock, flags); 1449 } 1450 #endif 1451 1452 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1453 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1454 spinlock_t *lock) 1455 { 1456 struct tegra_clk_pll *pll; 1457 1458 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1459 if (!pll) 1460 return ERR_PTR(-ENOMEM); 1461 1462 pll->clk_base = clk_base; 1463 pll->pmc = pmc; 1464 1465 pll->params = pll_params; 1466 pll->lock = lock; 1467 1468 if (!pll_params->div_nmp) 1469 pll_params->div_nmp = &default_nmp; 1470 1471 return pll; 1472 } 1473 1474 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1475 const char *name, const char *parent_name, unsigned long flags, 1476 const struct clk_ops *ops) 1477 { 1478 struct clk_init_data init; 1479 1480 init.name = name; 1481 init.ops = ops; 1482 init.flags = flags; 1483 init.parent_names = (parent_name ? &parent_name : NULL); 1484 init.num_parents = (parent_name ? 1 : 0); 1485 1486 /* Data in .init is copied by clk_register(), so stack variable OK */ 1487 pll->hw.init = &init; 1488 1489 return clk_register(NULL, &pll->hw); 1490 } 1491 1492 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1493 void __iomem *clk_base, void __iomem *pmc, 1494 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1495 spinlock_t *lock) 1496 { 1497 struct tegra_clk_pll *pll; 1498 struct clk *clk; 1499 1500 pll_params->flags |= TEGRA_PLL_BYPASS; 1501 1502 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1503 if (IS_ERR(pll)) 1504 return ERR_CAST(pll); 1505 1506 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1507 &tegra_clk_pll_ops); 1508 if (IS_ERR(clk)) 1509 kfree(pll); 1510 1511 return clk; 1512 } 1513 1514 static struct div_nmp pll_e_nmp = { 1515 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1516 .divn_width = PLLE_BASE_DIVN_WIDTH, 1517 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1518 .divm_width = PLLE_BASE_DIVM_WIDTH, 1519 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1520 .divp_width = PLLE_BASE_DIVP_WIDTH, 1521 }; 1522 1523 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1524 void __iomem *clk_base, void __iomem *pmc, 1525 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1526 spinlock_t *lock) 1527 { 1528 struct tegra_clk_pll *pll; 1529 struct clk *clk; 1530 1531 pll_params->flags |= TEGRA_PLL_BYPASS; 1532 1533 if (!pll_params->div_nmp) 1534 pll_params->div_nmp = &pll_e_nmp; 1535 1536 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1537 if (IS_ERR(pll)) 1538 return ERR_CAST(pll); 1539 1540 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1541 &tegra_clk_plle_ops); 1542 if (IS_ERR(clk)) 1543 kfree(pll); 1544 1545 return clk; 1546 } 1547 1548 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1549 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1550 defined(CONFIG_ARCH_TEGRA_132_SOC) 1551 static const struct clk_ops tegra_clk_pllxc_ops = { 1552 .is_enabled = clk_pll_is_enabled, 1553 .enable = clk_pll_enable, 1554 .disable = clk_pll_disable, 1555 .recalc_rate = clk_pll_recalc_rate, 1556 .round_rate = clk_pll_ramp_round_rate, 1557 .set_rate = clk_pllxc_set_rate, 1558 }; 1559 1560 static const struct clk_ops tegra_clk_pllm_ops = { 1561 .is_enabled = clk_pll_is_enabled, 1562 .enable = clk_pll_enable, 1563 .disable = clk_pll_disable, 1564 .recalc_rate = clk_pll_recalc_rate, 1565 .round_rate = clk_pll_ramp_round_rate, 1566 .set_rate = clk_pllm_set_rate, 1567 }; 1568 1569 static const struct clk_ops tegra_clk_pllc_ops = { 1570 .is_enabled = clk_pll_is_enabled, 1571 .enable = clk_pllc_enable, 1572 .disable = clk_pllc_disable, 1573 .recalc_rate = clk_pll_recalc_rate, 1574 .round_rate = clk_pll_ramp_round_rate, 1575 .set_rate = clk_pllc_set_rate, 1576 }; 1577 1578 static const struct clk_ops tegra_clk_pllre_ops = { 1579 .is_enabled = clk_pll_is_enabled, 1580 .enable = clk_pll_enable, 1581 .disable = clk_pll_disable, 1582 .recalc_rate = clk_pllre_recalc_rate, 1583 .round_rate = clk_pllre_round_rate, 1584 .set_rate = clk_pllre_set_rate, 1585 }; 1586 1587 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1588 .is_enabled = clk_pll_is_enabled, 1589 .enable = clk_plle_tegra114_enable, 1590 .disable = clk_plle_tegra114_disable, 1591 .recalc_rate = clk_pll_recalc_rate, 1592 }; 1593 1594 1595 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1596 void __iomem *clk_base, void __iomem *pmc, 1597 unsigned long flags, 1598 struct tegra_clk_pll_params *pll_params, 1599 spinlock_t *lock) 1600 { 1601 struct tegra_clk_pll *pll; 1602 struct clk *clk, *parent; 1603 unsigned long parent_rate; 1604 int err; 1605 u32 val, val_iddq; 1606 1607 parent = __clk_lookup(parent_name); 1608 if (!parent) { 1609 WARN(1, "parent clk %s of %s must be registered first\n", 1610 parent_name, name); 1611 return ERR_PTR(-EINVAL); 1612 } 1613 1614 if (!pll_params->pdiv_tohw) 1615 return ERR_PTR(-EINVAL); 1616 1617 parent_rate = clk_get_rate(parent); 1618 1619 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1620 1621 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1622 if (err) 1623 return ERR_PTR(err); 1624 1625 val = readl_relaxed(clk_base + pll_params->base_reg); 1626 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1627 1628 if (val & PLL_BASE_ENABLE) 1629 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1630 else { 1631 val_iddq |= BIT(pll_params->iddq_bit_idx); 1632 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1633 } 1634 1635 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1636 if (IS_ERR(pll)) 1637 return ERR_CAST(pll); 1638 1639 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1640 &tegra_clk_pllxc_ops); 1641 if (IS_ERR(clk)) 1642 kfree(pll); 1643 1644 return clk; 1645 } 1646 1647 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1648 void __iomem *clk_base, void __iomem *pmc, 1649 unsigned long flags, 1650 struct tegra_clk_pll_params *pll_params, 1651 spinlock_t *lock, unsigned long parent_rate) 1652 { 1653 u32 val; 1654 struct tegra_clk_pll *pll; 1655 struct clk *clk; 1656 1657 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1658 1659 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1660 if (IS_ERR(pll)) 1661 return ERR_CAST(pll); 1662 1663 /* program minimum rate by default */ 1664 1665 val = pll_readl_base(pll); 1666 if (val & PLL_BASE_ENABLE) 1667 WARN_ON(val & pll_params->iddq_bit_idx); 1668 else { 1669 int m; 1670 1671 m = _pll_fixed_mdiv(pll_params, parent_rate); 1672 val = m << divm_shift(pll); 1673 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 1674 pll_writel_base(val, pll); 1675 } 1676 1677 /* disable lock override */ 1678 1679 val = pll_readl_misc(pll); 1680 val &= ~BIT(29); 1681 pll_writel_misc(val, pll); 1682 1683 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1684 &tegra_clk_pllre_ops); 1685 if (IS_ERR(clk)) 1686 kfree(pll); 1687 1688 return clk; 1689 } 1690 1691 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1692 void __iomem *clk_base, void __iomem *pmc, 1693 unsigned long flags, 1694 struct tegra_clk_pll_params *pll_params, 1695 spinlock_t *lock) 1696 { 1697 struct tegra_clk_pll *pll; 1698 struct clk *clk, *parent; 1699 unsigned long parent_rate; 1700 1701 if (!pll_params->pdiv_tohw) 1702 return ERR_PTR(-EINVAL); 1703 1704 parent = __clk_lookup(parent_name); 1705 if (!parent) { 1706 WARN(1, "parent clk %s of %s must be registered first\n", 1707 parent_name, name); 1708 return ERR_PTR(-EINVAL); 1709 } 1710 1711 parent_rate = clk_get_rate(parent); 1712 1713 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1714 1715 pll_params->flags |= TEGRA_PLL_BYPASS; 1716 pll_params->flags |= TEGRA_PLLM; 1717 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1718 if (IS_ERR(pll)) 1719 return ERR_CAST(pll); 1720 1721 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1722 &tegra_clk_pllm_ops); 1723 if (IS_ERR(clk)) 1724 kfree(pll); 1725 1726 return clk; 1727 } 1728 1729 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1730 void __iomem *clk_base, void __iomem *pmc, 1731 unsigned long flags, 1732 struct tegra_clk_pll_params *pll_params, 1733 spinlock_t *lock) 1734 { 1735 struct clk *parent, *clk; 1736 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1737 struct tegra_clk_pll *pll; 1738 struct tegra_clk_pll_freq_table cfg; 1739 unsigned long parent_rate; 1740 1741 if (!p_tohw) 1742 return ERR_PTR(-EINVAL); 1743 1744 parent = __clk_lookup(parent_name); 1745 if (!parent) { 1746 WARN(1, "parent clk %s of %s must be registered first\n", 1747 parent_name, name); 1748 return ERR_PTR(-EINVAL); 1749 } 1750 1751 parent_rate = clk_get_rate(parent); 1752 1753 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1754 1755 pll_params->flags |= TEGRA_PLL_BYPASS; 1756 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1757 if (IS_ERR(pll)) 1758 return ERR_CAST(pll); 1759 1760 /* 1761 * Most of PLLC register fields are shadowed, and can not be read 1762 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1763 * Initialize PLL to default state: disabled, reset; shadow registers 1764 * loaded with default parameters; dividers are preset for half of 1765 * minimum VCO rate (the latter assured that shadowed divider settings 1766 * are within supported range). 1767 */ 1768 1769 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1770 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1771 1772 while (p_tohw->pdiv) { 1773 if (p_tohw->pdiv == 2) { 1774 cfg.p = p_tohw->hw_val; 1775 break; 1776 } 1777 p_tohw++; 1778 } 1779 1780 if (!p_tohw->pdiv) { 1781 WARN_ON(1); 1782 return ERR_PTR(-EINVAL); 1783 } 1784 1785 pll_writel_base(0, pll); 1786 _update_pll_mnp(pll, &cfg); 1787 1788 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1789 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1790 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1791 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1792 1793 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1794 1795 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1796 &tegra_clk_pllc_ops); 1797 if (IS_ERR(clk)) 1798 kfree(pll); 1799 1800 return clk; 1801 } 1802 1803 struct clk *tegra_clk_register_plle_tegra114(const char *name, 1804 const char *parent_name, 1805 void __iomem *clk_base, unsigned long flags, 1806 struct tegra_clk_pll_params *pll_params, 1807 spinlock_t *lock) 1808 { 1809 struct tegra_clk_pll *pll; 1810 struct clk *clk; 1811 u32 val, val_aux; 1812 1813 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1814 if (IS_ERR(pll)) 1815 return ERR_CAST(pll); 1816 1817 /* ensure parent is set to pll_re_vco */ 1818 1819 val = pll_readl_base(pll); 1820 val_aux = pll_readl(pll_params->aux_reg, pll); 1821 1822 if (val & PLL_BASE_ENABLE) { 1823 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1824 (val_aux & PLLE_AUX_PLLP_SEL)) 1825 WARN(1, "pll_e enabled with unsupported parent %s\n", 1826 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1827 "pll_re_vco"); 1828 } else { 1829 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1830 pll_writel(val_aux, pll_params->aux_reg, pll); 1831 } 1832 1833 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1834 &tegra_clk_plle_tegra114_ops); 1835 if (IS_ERR(clk)) 1836 kfree(pll); 1837 1838 return clk; 1839 } 1840 #endif 1841 1842 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 1843 static const struct clk_ops tegra_clk_pllss_ops = { 1844 .is_enabled = clk_pll_is_enabled, 1845 .enable = clk_pll_enable, 1846 .disable = clk_pll_disable, 1847 .recalc_rate = clk_pll_recalc_rate, 1848 .round_rate = clk_pll_ramp_round_rate, 1849 .set_rate = clk_pllxc_set_rate, 1850 }; 1851 1852 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 1853 void __iomem *clk_base, unsigned long flags, 1854 struct tegra_clk_pll_params *pll_params, 1855 spinlock_t *lock) 1856 { 1857 struct tegra_clk_pll *pll; 1858 struct clk *clk, *parent; 1859 struct tegra_clk_pll_freq_table cfg; 1860 unsigned long parent_rate; 1861 u32 val; 1862 int i; 1863 1864 if (!pll_params->div_nmp) 1865 return ERR_PTR(-EINVAL); 1866 1867 parent = __clk_lookup(parent_name); 1868 if (!parent) { 1869 WARN(1, "parent clk %s of %s must be registered first\n", 1870 parent_name, name); 1871 return ERR_PTR(-EINVAL); 1872 } 1873 1874 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1875 if (IS_ERR(pll)) 1876 return ERR_CAST(pll); 1877 1878 val = pll_readl_base(pll); 1879 val &= ~PLLSS_REF_SRC_SEL_MASK; 1880 pll_writel_base(val, pll); 1881 1882 parent_rate = clk_get_rate(parent); 1883 1884 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1885 1886 /* initialize PLL to minimum rate */ 1887 1888 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1889 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1890 1891 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 1892 ; 1893 if (!i) { 1894 kfree(pll); 1895 return ERR_PTR(-EINVAL); 1896 } 1897 1898 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 1899 1900 _update_pll_mnp(pll, &cfg); 1901 1902 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 1903 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 1904 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 1905 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1906 1907 val = pll_readl_base(pll); 1908 if (val & PLL_BASE_ENABLE) { 1909 if (val & BIT(pll_params->iddq_bit_idx)) { 1910 WARN(1, "%s is on but IDDQ set\n", name); 1911 kfree(pll); 1912 return ERR_PTR(-EINVAL); 1913 } 1914 } else 1915 val |= BIT(pll_params->iddq_bit_idx); 1916 1917 val &= ~PLLSS_LOCK_OVERRIDE; 1918 pll_writel_base(val, pll); 1919 1920 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1921 &tegra_clk_pllss_ops); 1922 1923 if (IS_ERR(clk)) 1924 kfree(pll); 1925 1926 return clk; 1927 } 1928 #endif 1929