1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk-provider.h> 22 #include <linux/clk.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 69 #define PLLE_MISC_SETUP_BASE_SHIFT 16 70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 71 #define PLLE_MISC_LOCK_ENABLE BIT(9) 72 #define PLLE_MISC_READY BIT(15) 73 #define PLLE_MISC_SETUP_EX_SHIFT 2 74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 76 PLLE_MISC_SETUP_EX_MASK) 77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 78 79 #define PLLE_SS_CTRL 0x68 80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 82 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 83 #define PLLE_SS_CNTL_CENTER BIT(14) 84 #define PLLE_SS_CNTL_INVERT BIT(15) 85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 86 PLLE_SS_CNTL_SSC_BYP) 87 #define PLLE_SS_MAX_MASK 0x1ff 88 #define PLLE_SS_MAX_VAL 0x25 89 #define PLLE_SS_INC_MASK (0xff << 16) 90 #define PLLE_SS_INC_VAL (0x1 << 16) 91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 93 #define PLLE_SS_COEFFICIENTS_MASK \ 94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 95 #define PLLE_SS_COEFFICIENTS_VAL \ 96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 97 98 #define PLLE_AUX_PLLP_SEL BIT(2) 99 #define PLLE_AUX_USE_LOCKDET BIT(3) 100 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 101 #define PLLE_AUX_SS_SWCTL BIT(6) 102 #define PLLE_AUX_SEQ_ENABLE BIT(24) 103 #define PLLE_AUX_SEQ_START_STATE BIT(25) 104 #define PLLE_AUX_PLLRE_SEL BIT(28) 105 106 #define XUSBIO_PLL_CFG0 0x51c 107 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 108 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 109 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 110 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 111 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 112 113 #define PLLE_MISC_PLLE_PTS BIT(8) 114 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 115 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 116 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 117 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 118 #define PLLE_MISC_VREG_CTRL_SHIFT 2 119 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 120 121 #define PLLCX_MISC_STROBE BIT(31) 122 #define PLLCX_MISC_RESET BIT(30) 123 #define PLLCX_MISC_SDM_DIV_SHIFT 28 124 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 125 #define PLLCX_MISC_FILT_DIV_SHIFT 26 126 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 127 #define PLLCX_MISC_ALPHA_SHIFT 18 128 #define PLLCX_MISC_DIV_LOW_RANGE \ 129 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 130 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 131 #define PLLCX_MISC_DIV_HIGH_RANGE \ 132 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 133 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 134 #define PLLCX_MISC_COEF_LOW_RANGE \ 135 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 136 #define PLLCX_MISC_KA_SHIFT 2 137 #define PLLCX_MISC_KB_SHIFT 9 138 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 139 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 140 PLLCX_MISC_DIV_LOW_RANGE | \ 141 PLLCX_MISC_RESET) 142 #define PLLCX_MISC1_DEFAULT 0x000d2308 143 #define PLLCX_MISC2_DEFAULT 0x30211200 144 #define PLLCX_MISC3_DEFAULT 0x200 145 146 #define PMC_SATA_PWRGT 0x1ac 147 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 148 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 149 150 #define PLLSS_MISC_KCP 0 151 #define PLLSS_MISC_KVCO 0 152 #define PLLSS_MISC_SETUP 0 153 #define PLLSS_EN_SDM 0 154 #define PLLSS_EN_SSC 0 155 #define PLLSS_EN_DITHER2 0 156 #define PLLSS_EN_DITHER 1 157 #define PLLSS_SDM_RESET 0 158 #define PLLSS_CLAMP 0 159 #define PLLSS_SDM_SSC_MAX 0 160 #define PLLSS_SDM_SSC_MIN 0 161 #define PLLSS_SDM_SSC_STEP 0 162 #define PLLSS_SDM_DIN 0 163 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 164 (PLLSS_MISC_KVCO << 24) | \ 165 PLLSS_MISC_SETUP) 166 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 167 (PLLSS_EN_SSC << 30) | \ 168 (PLLSS_EN_DITHER2 << 29) | \ 169 (PLLSS_EN_DITHER << 28) | \ 170 (PLLSS_SDM_RESET) << 27 | \ 171 (PLLSS_CLAMP << 22)) 172 #define PLLSS_CTRL1_DEFAULT \ 173 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 174 #define PLLSS_CTRL2_DEFAULT \ 175 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 176 #define PLLSS_LOCK_OVERRIDE BIT(24) 177 #define PLLSS_REF_SRC_SEL_SHIFT 25 178 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 179 180 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 181 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 182 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 183 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 184 185 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 186 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 187 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 188 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 189 190 #define mask(w) ((1 << (w)) - 1) 191 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 192 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 193 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 194 mask(p->params->div_nmp->divp_width)) 195 196 #define divm_shift(p) (p)->params->div_nmp->divm_shift 197 #define divn_shift(p) (p)->params->div_nmp->divn_shift 198 #define divp_shift(p) (p)->params->div_nmp->divp_shift 199 200 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 201 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 202 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 203 204 #define divm_max(p) (divm_mask(p)) 205 #define divn_max(p) (divn_mask(p)) 206 #define divp_max(p) (1 << (divp_mask(p))) 207 208 static struct div_nmp default_nmp = { 209 .divn_shift = PLL_BASE_DIVN_SHIFT, 210 .divn_width = PLL_BASE_DIVN_WIDTH, 211 .divm_shift = PLL_BASE_DIVM_SHIFT, 212 .divm_width = PLL_BASE_DIVM_WIDTH, 213 .divp_shift = PLL_BASE_DIVP_SHIFT, 214 .divp_width = PLL_BASE_DIVP_WIDTH, 215 }; 216 217 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 218 { 219 u32 val; 220 221 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 222 return; 223 224 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 225 return; 226 227 val = pll_readl_misc(pll); 228 val |= BIT(pll->params->lock_enable_bit_idx); 229 pll_writel_misc(val, pll); 230 } 231 232 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 233 { 234 int i; 235 u32 val, lock_mask; 236 void __iomem *lock_addr; 237 238 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 239 udelay(pll->params->lock_delay); 240 return 0; 241 } 242 243 lock_addr = pll->clk_base; 244 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 245 lock_addr += pll->params->misc_reg; 246 else 247 lock_addr += pll->params->base_reg; 248 249 lock_mask = pll->params->lock_mask; 250 251 for (i = 0; i < pll->params->lock_delay; i++) { 252 val = readl_relaxed(lock_addr); 253 if ((val & lock_mask) == lock_mask) { 254 udelay(PLL_POST_LOCK_DELAY); 255 return 0; 256 } 257 udelay(2); /* timeout = 2 * lock time */ 258 } 259 260 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 261 __clk_get_name(pll->hw.clk)); 262 263 return -1; 264 } 265 266 static int clk_pll_is_enabled(struct clk_hw *hw) 267 { 268 struct tegra_clk_pll *pll = to_clk_pll(hw); 269 u32 val; 270 271 if (pll->params->flags & TEGRA_PLLM) { 272 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 273 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 274 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 275 } 276 277 val = pll_readl_base(pll); 278 279 return val & PLL_BASE_ENABLE ? 1 : 0; 280 } 281 282 static void _clk_pll_enable(struct clk_hw *hw) 283 { 284 struct tegra_clk_pll *pll = to_clk_pll(hw); 285 u32 val; 286 287 clk_pll_enable_lock(pll); 288 289 val = pll_readl_base(pll); 290 if (pll->params->flags & TEGRA_PLL_BYPASS) 291 val &= ~PLL_BASE_BYPASS; 292 val |= PLL_BASE_ENABLE; 293 pll_writel_base(val, pll); 294 295 if (pll->params->flags & TEGRA_PLLM) { 296 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 297 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 298 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 299 } 300 } 301 302 static void _clk_pll_disable(struct clk_hw *hw) 303 { 304 struct tegra_clk_pll *pll = to_clk_pll(hw); 305 u32 val; 306 307 val = pll_readl_base(pll); 308 if (pll->params->flags & TEGRA_PLL_BYPASS) 309 val &= ~PLL_BASE_BYPASS; 310 val &= ~PLL_BASE_ENABLE; 311 pll_writel_base(val, pll); 312 313 if (pll->params->flags & TEGRA_PLLM) { 314 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 315 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 316 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 317 } 318 } 319 320 static int clk_pll_enable(struct clk_hw *hw) 321 { 322 struct tegra_clk_pll *pll = to_clk_pll(hw); 323 unsigned long flags = 0; 324 int ret; 325 326 if (pll->lock) 327 spin_lock_irqsave(pll->lock, flags); 328 329 _clk_pll_enable(hw); 330 331 ret = clk_pll_wait_for_lock(pll); 332 333 if (pll->lock) 334 spin_unlock_irqrestore(pll->lock, flags); 335 336 return ret; 337 } 338 339 static void clk_pll_disable(struct clk_hw *hw) 340 { 341 struct tegra_clk_pll *pll = to_clk_pll(hw); 342 unsigned long flags = 0; 343 344 if (pll->lock) 345 spin_lock_irqsave(pll->lock, flags); 346 347 _clk_pll_disable(hw); 348 349 if (pll->lock) 350 spin_unlock_irqrestore(pll->lock, flags); 351 } 352 353 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 354 { 355 struct tegra_clk_pll *pll = to_clk_pll(hw); 356 struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 357 358 if (p_tohw) { 359 while (p_tohw->pdiv) { 360 if (p_div <= p_tohw->pdiv) 361 return p_tohw->hw_val; 362 p_tohw++; 363 } 364 return -EINVAL; 365 } 366 return -EINVAL; 367 } 368 369 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 370 { 371 struct tegra_clk_pll *pll = to_clk_pll(hw); 372 struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 373 374 if (p_tohw) { 375 while (p_tohw->pdiv) { 376 if (p_div_hw == p_tohw->hw_val) 377 return p_tohw->pdiv; 378 p_tohw++; 379 } 380 return -EINVAL; 381 } 382 383 return 1 << p_div_hw; 384 } 385 386 static int _get_table_rate(struct clk_hw *hw, 387 struct tegra_clk_pll_freq_table *cfg, 388 unsigned long rate, unsigned long parent_rate) 389 { 390 struct tegra_clk_pll *pll = to_clk_pll(hw); 391 struct tegra_clk_pll_freq_table *sel; 392 393 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 394 if (sel->input_rate == parent_rate && 395 sel->output_rate == rate) 396 break; 397 398 if (sel->input_rate == 0) 399 return -EINVAL; 400 401 cfg->input_rate = sel->input_rate; 402 cfg->output_rate = sel->output_rate; 403 cfg->m = sel->m; 404 cfg->n = sel->n; 405 cfg->p = sel->p; 406 cfg->cpcon = sel->cpcon; 407 408 return 0; 409 } 410 411 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 412 unsigned long rate, unsigned long parent_rate) 413 { 414 struct tegra_clk_pll *pll = to_clk_pll(hw); 415 unsigned long cfreq; 416 u32 p_div = 0; 417 int ret; 418 419 switch (parent_rate) { 420 case 12000000: 421 case 26000000: 422 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 423 break; 424 case 13000000: 425 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 426 break; 427 case 16800000: 428 case 19200000: 429 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 430 break; 431 case 9600000: 432 case 28800000: 433 /* 434 * PLL_P_OUT1 rate is not listed in PLLA table 435 */ 436 cfreq = parent_rate/(parent_rate/1000000); 437 break; 438 default: 439 pr_err("%s Unexpected reference rate %lu\n", 440 __func__, parent_rate); 441 BUG(); 442 } 443 444 /* Raise VCO to guarantee 0.5% accuracy */ 445 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 446 cfg->output_rate <<= 1) 447 p_div++; 448 449 cfg->m = parent_rate / cfreq; 450 cfg->n = cfg->output_rate / cfreq; 451 cfg->cpcon = OUT_OF_TABLE_CPCON; 452 453 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 454 (1 << p_div) > divp_max(pll) 455 || cfg->output_rate > pll->params->vco_max) { 456 return -EINVAL; 457 } 458 459 cfg->output_rate >>= p_div; 460 461 if (pll->params->pdiv_tohw) { 462 ret = _p_div_to_hw(hw, 1 << p_div); 463 if (ret < 0) 464 return ret; 465 else 466 cfg->p = ret; 467 } else 468 cfg->p = p_div; 469 470 return 0; 471 } 472 473 static void _update_pll_mnp(struct tegra_clk_pll *pll, 474 struct tegra_clk_pll_freq_table *cfg) 475 { 476 u32 val; 477 struct tegra_clk_pll_params *params = pll->params; 478 struct div_nmp *div_nmp = params->div_nmp; 479 480 if ((params->flags & TEGRA_PLLM) && 481 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 482 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 483 val = pll_override_readl(params->pmc_divp_reg, pll); 484 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 485 val |= cfg->p << div_nmp->override_divp_shift; 486 pll_override_writel(val, params->pmc_divp_reg, pll); 487 488 val = pll_override_readl(params->pmc_divnm_reg, pll); 489 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | 490 ~(divn_mask(pll) << div_nmp->override_divn_shift); 491 val |= (cfg->m << div_nmp->override_divm_shift) | 492 (cfg->n << div_nmp->override_divn_shift); 493 pll_override_writel(val, params->pmc_divnm_reg, pll); 494 } else { 495 val = pll_readl_base(pll); 496 497 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 498 divp_mask_shifted(pll)); 499 500 val |= (cfg->m << divm_shift(pll)) | 501 (cfg->n << divn_shift(pll)) | 502 (cfg->p << divp_shift(pll)); 503 504 pll_writel_base(val, pll); 505 } 506 } 507 508 static void _get_pll_mnp(struct tegra_clk_pll *pll, 509 struct tegra_clk_pll_freq_table *cfg) 510 { 511 u32 val; 512 struct tegra_clk_pll_params *params = pll->params; 513 struct div_nmp *div_nmp = params->div_nmp; 514 515 if ((params->flags & TEGRA_PLLM) && 516 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 517 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 518 val = pll_override_readl(params->pmc_divp_reg, pll); 519 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 520 521 val = pll_override_readl(params->pmc_divnm_reg, pll); 522 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 523 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 524 } else { 525 val = pll_readl_base(pll); 526 527 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 528 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 529 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 530 } 531 } 532 533 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 534 struct tegra_clk_pll_freq_table *cfg, 535 unsigned long rate) 536 { 537 u32 val; 538 539 val = pll_readl_misc(pll); 540 541 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 542 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 543 544 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 545 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 546 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 547 val |= 1 << PLL_MISC_LFCON_SHIFT; 548 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 549 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 550 if (rate >= (pll->params->vco_max >> 1)) 551 val |= 1 << PLL_MISC_DCCON_SHIFT; 552 } 553 554 pll_writel_misc(val, pll); 555 } 556 557 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 558 unsigned long rate) 559 { 560 struct tegra_clk_pll *pll = to_clk_pll(hw); 561 int state, ret = 0; 562 563 state = clk_pll_is_enabled(hw); 564 565 if (state) 566 _clk_pll_disable(hw); 567 568 _update_pll_mnp(pll, cfg); 569 570 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 571 _update_pll_cpcon(pll, cfg, rate); 572 573 if (state) { 574 _clk_pll_enable(hw); 575 ret = clk_pll_wait_for_lock(pll); 576 } 577 578 return ret; 579 } 580 581 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 582 unsigned long parent_rate) 583 { 584 struct tegra_clk_pll *pll = to_clk_pll(hw); 585 struct tegra_clk_pll_freq_table cfg, old_cfg; 586 unsigned long flags = 0; 587 int ret = 0; 588 589 if (pll->params->flags & TEGRA_PLL_FIXED) { 590 if (rate != pll->params->fixed_rate) { 591 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 592 __func__, __clk_get_name(hw->clk), 593 pll->params->fixed_rate, rate); 594 return -EINVAL; 595 } 596 return 0; 597 } 598 599 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 600 _calc_rate(hw, &cfg, rate, parent_rate)) { 601 pr_err("%s: Failed to set %s rate %lu\n", __func__, 602 __clk_get_name(hw->clk), rate); 603 WARN_ON(1); 604 return -EINVAL; 605 } 606 if (pll->lock) 607 spin_lock_irqsave(pll->lock, flags); 608 609 _get_pll_mnp(pll, &old_cfg); 610 611 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 612 ret = _program_pll(hw, &cfg, rate); 613 614 if (pll->lock) 615 spin_unlock_irqrestore(pll->lock, flags); 616 617 return ret; 618 } 619 620 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 621 unsigned long *prate) 622 { 623 struct tegra_clk_pll *pll = to_clk_pll(hw); 624 struct tegra_clk_pll_freq_table cfg; 625 626 if (pll->params->flags & TEGRA_PLL_FIXED) 627 return pll->params->fixed_rate; 628 629 /* PLLM is used for memory; we do not change rate */ 630 if (pll->params->flags & TEGRA_PLLM) 631 return __clk_get_rate(hw->clk); 632 633 if (_get_table_rate(hw, &cfg, rate, *prate) && 634 _calc_rate(hw, &cfg, rate, *prate)) 635 return -EINVAL; 636 637 return cfg.output_rate; 638 } 639 640 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 641 unsigned long parent_rate) 642 { 643 struct tegra_clk_pll *pll = to_clk_pll(hw); 644 struct tegra_clk_pll_freq_table cfg; 645 u32 val; 646 u64 rate = parent_rate; 647 int pdiv; 648 649 val = pll_readl_base(pll); 650 651 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 652 return parent_rate; 653 654 if ((pll->params->flags & TEGRA_PLL_FIXED) && 655 !(val & PLL_BASE_OVERRIDE)) { 656 struct tegra_clk_pll_freq_table sel; 657 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 658 parent_rate)) { 659 pr_err("Clock %s has unknown fixed frequency\n", 660 __clk_get_name(hw->clk)); 661 BUG(); 662 } 663 return pll->params->fixed_rate; 664 } 665 666 _get_pll_mnp(pll, &cfg); 667 668 pdiv = _hw_to_p_div(hw, cfg.p); 669 if (pdiv < 0) { 670 WARN_ON(1); 671 pdiv = 1; 672 } 673 674 cfg.m *= pdiv; 675 676 rate *= cfg.n; 677 do_div(rate, cfg.m); 678 679 return rate; 680 } 681 682 static int clk_plle_training(struct tegra_clk_pll *pll) 683 { 684 u32 val; 685 unsigned long timeout; 686 687 if (!pll->pmc) 688 return -ENOSYS; 689 690 /* 691 * PLLE is already disabled, and setup cleared; 692 * create falling edge on PLLE IDDQ input. 693 */ 694 val = readl(pll->pmc + PMC_SATA_PWRGT); 695 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 696 writel(val, pll->pmc + PMC_SATA_PWRGT); 697 698 val = readl(pll->pmc + PMC_SATA_PWRGT); 699 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 700 writel(val, pll->pmc + PMC_SATA_PWRGT); 701 702 val = readl(pll->pmc + PMC_SATA_PWRGT); 703 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 704 writel(val, pll->pmc + PMC_SATA_PWRGT); 705 706 val = pll_readl_misc(pll); 707 708 timeout = jiffies + msecs_to_jiffies(100); 709 while (1) { 710 val = pll_readl_misc(pll); 711 if (val & PLLE_MISC_READY) 712 break; 713 if (time_after(jiffies, timeout)) { 714 pr_err("%s: timeout waiting for PLLE\n", __func__); 715 return -EBUSY; 716 } 717 udelay(300); 718 } 719 720 return 0; 721 } 722 723 static int clk_plle_enable(struct clk_hw *hw) 724 { 725 struct tegra_clk_pll *pll = to_clk_pll(hw); 726 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 727 struct tegra_clk_pll_freq_table sel; 728 u32 val; 729 int err; 730 731 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 732 return -EINVAL; 733 734 clk_pll_disable(hw); 735 736 val = pll_readl_misc(pll); 737 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 738 pll_writel_misc(val, pll); 739 740 val = pll_readl_misc(pll); 741 if (!(val & PLLE_MISC_READY)) { 742 err = clk_plle_training(pll); 743 if (err) 744 return err; 745 } 746 747 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 748 /* configure dividers */ 749 val = pll_readl_base(pll); 750 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 751 divm_mask_shifted(pll)); 752 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 753 val |= sel.m << divm_shift(pll); 754 val |= sel.n << divn_shift(pll); 755 val |= sel.p << divp_shift(pll); 756 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 757 pll_writel_base(val, pll); 758 } 759 760 val = pll_readl_misc(pll); 761 val |= PLLE_MISC_SETUP_VALUE; 762 val |= PLLE_MISC_LOCK_ENABLE; 763 pll_writel_misc(val, pll); 764 765 val = readl(pll->clk_base + PLLE_SS_CTRL); 766 val &= ~PLLE_SS_COEFFICIENTS_MASK; 767 val |= PLLE_SS_DISABLE; 768 writel(val, pll->clk_base + PLLE_SS_CTRL); 769 770 val = pll_readl_base(pll); 771 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 772 pll_writel_base(val, pll); 773 774 clk_pll_wait_for_lock(pll); 775 776 return 0; 777 } 778 779 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 780 unsigned long parent_rate) 781 { 782 struct tegra_clk_pll *pll = to_clk_pll(hw); 783 u32 val = pll_readl_base(pll); 784 u32 divn = 0, divm = 0, divp = 0; 785 u64 rate = parent_rate; 786 787 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 788 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 789 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 790 divm *= divp; 791 792 rate *= divn; 793 do_div(rate, divm); 794 return rate; 795 } 796 797 const struct clk_ops tegra_clk_pll_ops = { 798 .is_enabled = clk_pll_is_enabled, 799 .enable = clk_pll_enable, 800 .disable = clk_pll_disable, 801 .recalc_rate = clk_pll_recalc_rate, 802 .round_rate = clk_pll_round_rate, 803 .set_rate = clk_pll_set_rate, 804 }; 805 806 const struct clk_ops tegra_clk_plle_ops = { 807 .recalc_rate = clk_plle_recalc_rate, 808 .is_enabled = clk_pll_is_enabled, 809 .disable = clk_pll_disable, 810 .enable = clk_plle_enable, 811 }; 812 813 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) 814 815 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 816 unsigned long parent_rate) 817 { 818 if (parent_rate > pll_params->cf_max) 819 return 2; 820 else 821 return 1; 822 } 823 824 static unsigned long _clip_vco_min(unsigned long vco_min, 825 unsigned long parent_rate) 826 { 827 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 828 } 829 830 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 831 void __iomem *clk_base, 832 unsigned long parent_rate) 833 { 834 u32 val; 835 u32 step_a, step_b; 836 837 switch (parent_rate) { 838 case 12000000: 839 case 13000000: 840 case 26000000: 841 step_a = 0x2B; 842 step_b = 0x0B; 843 break; 844 case 16800000: 845 step_a = 0x1A; 846 step_b = 0x09; 847 break; 848 case 19200000: 849 step_a = 0x12; 850 step_b = 0x08; 851 break; 852 default: 853 pr_err("%s: Unexpected reference rate %lu\n", 854 __func__, parent_rate); 855 WARN_ON(1); 856 return -EINVAL; 857 } 858 859 val = step_a << pll_params->stepa_shift; 860 val |= step_b << pll_params->stepb_shift; 861 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 862 863 return 0; 864 } 865 866 static int clk_pll_iddq_enable(struct clk_hw *hw) 867 { 868 struct tegra_clk_pll *pll = to_clk_pll(hw); 869 unsigned long flags = 0; 870 871 u32 val; 872 int ret; 873 874 if (pll->lock) 875 spin_lock_irqsave(pll->lock, flags); 876 877 val = pll_readl(pll->params->iddq_reg, pll); 878 val &= ~BIT(pll->params->iddq_bit_idx); 879 pll_writel(val, pll->params->iddq_reg, pll); 880 udelay(2); 881 882 _clk_pll_enable(hw); 883 884 ret = clk_pll_wait_for_lock(pll); 885 886 if (pll->lock) 887 spin_unlock_irqrestore(pll->lock, flags); 888 889 return 0; 890 } 891 892 static void clk_pll_iddq_disable(struct clk_hw *hw) 893 { 894 struct tegra_clk_pll *pll = to_clk_pll(hw); 895 unsigned long flags = 0; 896 u32 val; 897 898 if (pll->lock) 899 spin_lock_irqsave(pll->lock, flags); 900 901 _clk_pll_disable(hw); 902 903 val = pll_readl(pll->params->iddq_reg, pll); 904 val |= BIT(pll->params->iddq_bit_idx); 905 pll_writel(val, pll->params->iddq_reg, pll); 906 udelay(2); 907 908 if (pll->lock) 909 spin_unlock_irqrestore(pll->lock, flags); 910 } 911 912 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 913 struct tegra_clk_pll_freq_table *cfg, 914 unsigned long rate, unsigned long parent_rate) 915 { 916 struct tegra_clk_pll *pll = to_clk_pll(hw); 917 unsigned int p; 918 int p_div; 919 920 if (!rate) 921 return -EINVAL; 922 923 p = DIV_ROUND_UP(pll->params->vco_min, rate); 924 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 925 cfg->output_rate = rate * p; 926 cfg->n = cfg->output_rate * cfg->m / parent_rate; 927 928 p_div = _p_div_to_hw(hw, p); 929 if (p_div < 0) 930 return p_div; 931 else 932 cfg->p = p_div; 933 934 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 935 return -EINVAL; 936 937 return 0; 938 } 939 940 static int _pll_ramp_calc_pll(struct clk_hw *hw, 941 struct tegra_clk_pll_freq_table *cfg, 942 unsigned long rate, unsigned long parent_rate) 943 { 944 struct tegra_clk_pll *pll = to_clk_pll(hw); 945 int err = 0, p_div; 946 947 err = _get_table_rate(hw, cfg, rate, parent_rate); 948 if (err < 0) 949 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 950 else { 951 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 952 WARN_ON(1); 953 err = -EINVAL; 954 goto out; 955 } 956 p_div = _p_div_to_hw(hw, cfg->p); 957 if (p_div < 0) 958 return p_div; 959 else 960 cfg->p = p_div; 961 } 962 963 if (cfg->p > pll->params->max_p) 964 err = -EINVAL; 965 966 out: 967 return err; 968 } 969 970 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 971 unsigned long parent_rate) 972 { 973 struct tegra_clk_pll *pll = to_clk_pll(hw); 974 struct tegra_clk_pll_freq_table cfg, old_cfg; 975 unsigned long flags = 0; 976 int ret = 0; 977 978 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 979 if (ret < 0) 980 return ret; 981 982 if (pll->lock) 983 spin_lock_irqsave(pll->lock, flags); 984 985 _get_pll_mnp(pll, &old_cfg); 986 987 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 988 ret = _program_pll(hw, &cfg, rate); 989 990 if (pll->lock) 991 spin_unlock_irqrestore(pll->lock, flags); 992 993 return ret; 994 } 995 996 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 997 unsigned long *prate) 998 { 999 struct tegra_clk_pll_freq_table cfg; 1000 int ret = 0, p_div; 1001 u64 output_rate = *prate; 1002 1003 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1004 if (ret < 0) 1005 return ret; 1006 1007 p_div = _hw_to_p_div(hw, cfg.p); 1008 if (p_div < 0) 1009 return p_div; 1010 1011 output_rate *= cfg.n; 1012 do_div(output_rate, cfg.m * p_div); 1013 1014 return output_rate; 1015 } 1016 1017 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, 1018 unsigned long parent_rate) 1019 { 1020 struct tegra_clk_pll_freq_table cfg; 1021 struct tegra_clk_pll *pll = to_clk_pll(hw); 1022 unsigned long flags = 0; 1023 int state, ret = 0; 1024 1025 if (pll->lock) 1026 spin_lock_irqsave(pll->lock, flags); 1027 1028 state = clk_pll_is_enabled(hw); 1029 if (state) { 1030 if (rate != clk_get_rate(hw->clk)) { 1031 pr_err("%s: Cannot change active PLLM\n", __func__); 1032 ret = -EINVAL; 1033 goto out; 1034 } 1035 goto out; 1036 } 1037 1038 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1039 if (ret < 0) 1040 goto out; 1041 1042 _update_pll_mnp(pll, &cfg); 1043 1044 out: 1045 if (pll->lock) 1046 spin_unlock_irqrestore(pll->lock, flags); 1047 1048 return ret; 1049 } 1050 1051 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1052 { 1053 u32 val; 1054 1055 val = pll_readl_misc(pll); 1056 val |= PLLCX_MISC_STROBE; 1057 pll_writel_misc(val, pll); 1058 udelay(2); 1059 1060 val &= ~PLLCX_MISC_STROBE; 1061 pll_writel_misc(val, pll); 1062 } 1063 1064 static int clk_pllc_enable(struct clk_hw *hw) 1065 { 1066 struct tegra_clk_pll *pll = to_clk_pll(hw); 1067 u32 val; 1068 int ret = 0; 1069 unsigned long flags = 0; 1070 1071 if (pll->lock) 1072 spin_lock_irqsave(pll->lock, flags); 1073 1074 _clk_pll_enable(hw); 1075 udelay(2); 1076 1077 val = pll_readl_misc(pll); 1078 val &= ~PLLCX_MISC_RESET; 1079 pll_writel_misc(val, pll); 1080 udelay(2); 1081 1082 _pllcx_strobe(pll); 1083 1084 ret = clk_pll_wait_for_lock(pll); 1085 1086 if (pll->lock) 1087 spin_unlock_irqrestore(pll->lock, flags); 1088 1089 return ret; 1090 } 1091 1092 static void _clk_pllc_disable(struct clk_hw *hw) 1093 { 1094 struct tegra_clk_pll *pll = to_clk_pll(hw); 1095 u32 val; 1096 1097 _clk_pll_disable(hw); 1098 1099 val = pll_readl_misc(pll); 1100 val |= PLLCX_MISC_RESET; 1101 pll_writel_misc(val, pll); 1102 udelay(2); 1103 } 1104 1105 static void clk_pllc_disable(struct clk_hw *hw) 1106 { 1107 struct tegra_clk_pll *pll = to_clk_pll(hw); 1108 unsigned long flags = 0; 1109 1110 if (pll->lock) 1111 spin_lock_irqsave(pll->lock, flags); 1112 1113 _clk_pllc_disable(hw); 1114 1115 if (pll->lock) 1116 spin_unlock_irqrestore(pll->lock, flags); 1117 } 1118 1119 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1120 unsigned long input_rate, u32 n) 1121 { 1122 u32 val, n_threshold; 1123 1124 switch (input_rate) { 1125 case 12000000: 1126 n_threshold = 70; 1127 break; 1128 case 13000000: 1129 case 26000000: 1130 n_threshold = 71; 1131 break; 1132 case 16800000: 1133 n_threshold = 55; 1134 break; 1135 case 19200000: 1136 n_threshold = 48; 1137 break; 1138 default: 1139 pr_err("%s: Unexpected reference rate %lu\n", 1140 __func__, input_rate); 1141 return -EINVAL; 1142 } 1143 1144 val = pll_readl_misc(pll); 1145 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1146 val |= n <= n_threshold ? 1147 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1148 pll_writel_misc(val, pll); 1149 1150 return 0; 1151 } 1152 1153 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1154 unsigned long parent_rate) 1155 { 1156 struct tegra_clk_pll_freq_table cfg, old_cfg; 1157 struct tegra_clk_pll *pll = to_clk_pll(hw); 1158 unsigned long flags = 0; 1159 int state, ret = 0; 1160 1161 if (pll->lock) 1162 spin_lock_irqsave(pll->lock, flags); 1163 1164 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1165 if (ret < 0) 1166 goto out; 1167 1168 _get_pll_mnp(pll, &old_cfg); 1169 1170 if (cfg.m != old_cfg.m) { 1171 WARN_ON(1); 1172 goto out; 1173 } 1174 1175 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1176 goto out; 1177 1178 state = clk_pll_is_enabled(hw); 1179 if (state) 1180 _clk_pllc_disable(hw); 1181 1182 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1183 if (ret < 0) 1184 goto out; 1185 1186 _update_pll_mnp(pll, &cfg); 1187 1188 if (state) 1189 ret = clk_pllc_enable(hw); 1190 1191 out: 1192 if (pll->lock) 1193 spin_unlock_irqrestore(pll->lock, flags); 1194 1195 return ret; 1196 } 1197 1198 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1199 struct tegra_clk_pll_freq_table *cfg, 1200 unsigned long rate, unsigned long parent_rate) 1201 { 1202 u16 m, n; 1203 u64 output_rate = parent_rate; 1204 1205 m = _pll_fixed_mdiv(pll->params, parent_rate); 1206 n = rate * m / parent_rate; 1207 1208 output_rate *= n; 1209 do_div(output_rate, m); 1210 1211 if (cfg) { 1212 cfg->m = m; 1213 cfg->n = n; 1214 } 1215 1216 return output_rate; 1217 } 1218 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1219 unsigned long parent_rate) 1220 { 1221 struct tegra_clk_pll_freq_table cfg, old_cfg; 1222 struct tegra_clk_pll *pll = to_clk_pll(hw); 1223 unsigned long flags = 0; 1224 int state, ret = 0; 1225 1226 if (pll->lock) 1227 spin_lock_irqsave(pll->lock, flags); 1228 1229 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1230 _get_pll_mnp(pll, &old_cfg); 1231 cfg.p = old_cfg.p; 1232 1233 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1234 state = clk_pll_is_enabled(hw); 1235 if (state) 1236 _clk_pll_disable(hw); 1237 1238 _update_pll_mnp(pll, &cfg); 1239 1240 if (state) { 1241 _clk_pll_enable(hw); 1242 ret = clk_pll_wait_for_lock(pll); 1243 } 1244 } 1245 1246 if (pll->lock) 1247 spin_unlock_irqrestore(pll->lock, flags); 1248 1249 return ret; 1250 } 1251 1252 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1253 unsigned long parent_rate) 1254 { 1255 struct tegra_clk_pll_freq_table cfg; 1256 struct tegra_clk_pll *pll = to_clk_pll(hw); 1257 u64 rate = parent_rate; 1258 1259 _get_pll_mnp(pll, &cfg); 1260 1261 rate *= cfg.n; 1262 do_div(rate, cfg.m); 1263 1264 return rate; 1265 } 1266 1267 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1268 unsigned long *prate) 1269 { 1270 struct tegra_clk_pll *pll = to_clk_pll(hw); 1271 1272 return _pllre_calc_rate(pll, NULL, rate, *prate); 1273 } 1274 1275 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1276 { 1277 struct tegra_clk_pll *pll = to_clk_pll(hw); 1278 struct tegra_clk_pll_freq_table sel; 1279 u32 val; 1280 int ret; 1281 unsigned long flags = 0; 1282 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1283 1284 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1285 return -EINVAL; 1286 1287 if (pll->lock) 1288 spin_lock_irqsave(pll->lock, flags); 1289 1290 val = pll_readl_base(pll); 1291 val &= ~BIT(29); /* Disable lock override */ 1292 pll_writel_base(val, pll); 1293 1294 val = pll_readl(pll->params->aux_reg, pll); 1295 val |= PLLE_AUX_ENABLE_SWCTL; 1296 val &= ~PLLE_AUX_SEQ_ENABLE; 1297 pll_writel(val, pll->params->aux_reg, pll); 1298 udelay(1); 1299 1300 val = pll_readl_misc(pll); 1301 val |= PLLE_MISC_LOCK_ENABLE; 1302 val |= PLLE_MISC_IDDQ_SW_CTRL; 1303 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1304 val |= PLLE_MISC_PLLE_PTS; 1305 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1306 pll_writel_misc(val, pll); 1307 udelay(5); 1308 1309 val = pll_readl(PLLE_SS_CTRL, pll); 1310 val |= PLLE_SS_DISABLE; 1311 pll_writel(val, PLLE_SS_CTRL, pll); 1312 1313 val = pll_readl_base(pll); 1314 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1315 divm_mask_shifted(pll)); 1316 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1317 val |= sel.m << divm_shift(pll); 1318 val |= sel.n << divn_shift(pll); 1319 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1320 pll_writel_base(val, pll); 1321 udelay(1); 1322 1323 _clk_pll_enable(hw); 1324 ret = clk_pll_wait_for_lock(pll); 1325 1326 if (ret < 0) 1327 goto out; 1328 1329 val = pll_readl(PLLE_SS_CTRL, pll); 1330 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1331 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1332 val |= PLLE_SS_COEFFICIENTS_VAL; 1333 pll_writel(val, PLLE_SS_CTRL, pll); 1334 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1335 pll_writel(val, PLLE_SS_CTRL, pll); 1336 udelay(1); 1337 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1338 pll_writel(val, PLLE_SS_CTRL, pll); 1339 udelay(1); 1340 1341 /* Enable hw control of xusb brick pll */ 1342 val = pll_readl_misc(pll); 1343 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1344 pll_writel_misc(val, pll); 1345 1346 val = pll_readl(pll->params->aux_reg, pll); 1347 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1348 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1349 pll_writel(val, pll->params->aux_reg, pll); 1350 udelay(1); 1351 val |= PLLE_AUX_SEQ_ENABLE; 1352 pll_writel(val, pll->params->aux_reg, pll); 1353 1354 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1355 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1356 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1357 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1358 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1359 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1360 udelay(1); 1361 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1362 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1363 1364 out: 1365 if (pll->lock) 1366 spin_unlock_irqrestore(pll->lock, flags); 1367 1368 return ret; 1369 } 1370 1371 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1372 { 1373 struct tegra_clk_pll *pll = to_clk_pll(hw); 1374 unsigned long flags = 0; 1375 u32 val; 1376 1377 if (pll->lock) 1378 spin_lock_irqsave(pll->lock, flags); 1379 1380 _clk_pll_disable(hw); 1381 1382 val = pll_readl_misc(pll); 1383 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1384 pll_writel_misc(val, pll); 1385 udelay(1); 1386 1387 if (pll->lock) 1388 spin_unlock_irqrestore(pll->lock, flags); 1389 } 1390 #endif 1391 1392 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1393 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1394 spinlock_t *lock) 1395 { 1396 struct tegra_clk_pll *pll; 1397 1398 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1399 if (!pll) 1400 return ERR_PTR(-ENOMEM); 1401 1402 pll->clk_base = clk_base; 1403 pll->pmc = pmc; 1404 1405 pll->params = pll_params; 1406 pll->lock = lock; 1407 1408 if (!pll_params->div_nmp) 1409 pll_params->div_nmp = &default_nmp; 1410 1411 return pll; 1412 } 1413 1414 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1415 const char *name, const char *parent_name, unsigned long flags, 1416 const struct clk_ops *ops) 1417 { 1418 struct clk_init_data init; 1419 1420 init.name = name; 1421 init.ops = ops; 1422 init.flags = flags; 1423 init.parent_names = (parent_name ? &parent_name : NULL); 1424 init.num_parents = (parent_name ? 1 : 0); 1425 1426 /* Data in .init is copied by clk_register(), so stack variable OK */ 1427 pll->hw.init = &init; 1428 1429 return clk_register(NULL, &pll->hw); 1430 } 1431 1432 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1433 void __iomem *clk_base, void __iomem *pmc, 1434 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1435 spinlock_t *lock) 1436 { 1437 struct tegra_clk_pll *pll; 1438 struct clk *clk; 1439 1440 pll_params->flags |= TEGRA_PLL_BYPASS; 1441 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1442 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1443 if (IS_ERR(pll)) 1444 return ERR_CAST(pll); 1445 1446 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1447 &tegra_clk_pll_ops); 1448 if (IS_ERR(clk)) 1449 kfree(pll); 1450 1451 return clk; 1452 } 1453 1454 static struct div_nmp pll_e_nmp = { 1455 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1456 .divn_width = PLLE_BASE_DIVN_WIDTH, 1457 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1458 .divm_width = PLLE_BASE_DIVM_WIDTH, 1459 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1460 .divp_width = PLLE_BASE_DIVP_WIDTH, 1461 }; 1462 1463 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1464 void __iomem *clk_base, void __iomem *pmc, 1465 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1466 spinlock_t *lock) 1467 { 1468 struct tegra_clk_pll *pll; 1469 struct clk *clk; 1470 1471 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; 1472 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1473 1474 if (!pll_params->div_nmp) 1475 pll_params->div_nmp = &pll_e_nmp; 1476 1477 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1478 if (IS_ERR(pll)) 1479 return ERR_CAST(pll); 1480 1481 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1482 &tegra_clk_plle_ops); 1483 if (IS_ERR(clk)) 1484 kfree(pll); 1485 1486 return clk; 1487 } 1488 1489 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) 1490 static const struct clk_ops tegra_clk_pllxc_ops = { 1491 .is_enabled = clk_pll_is_enabled, 1492 .enable = clk_pll_iddq_enable, 1493 .disable = clk_pll_iddq_disable, 1494 .recalc_rate = clk_pll_recalc_rate, 1495 .round_rate = clk_pll_ramp_round_rate, 1496 .set_rate = clk_pllxc_set_rate, 1497 }; 1498 1499 static const struct clk_ops tegra_clk_pllm_ops = { 1500 .is_enabled = clk_pll_is_enabled, 1501 .enable = clk_pll_iddq_enable, 1502 .disable = clk_pll_iddq_disable, 1503 .recalc_rate = clk_pll_recalc_rate, 1504 .round_rate = clk_pll_ramp_round_rate, 1505 .set_rate = clk_pllm_set_rate, 1506 }; 1507 1508 static const struct clk_ops tegra_clk_pllc_ops = { 1509 .is_enabled = clk_pll_is_enabled, 1510 .enable = clk_pllc_enable, 1511 .disable = clk_pllc_disable, 1512 .recalc_rate = clk_pll_recalc_rate, 1513 .round_rate = clk_pll_ramp_round_rate, 1514 .set_rate = clk_pllc_set_rate, 1515 }; 1516 1517 static const struct clk_ops tegra_clk_pllre_ops = { 1518 .is_enabled = clk_pll_is_enabled, 1519 .enable = clk_pll_iddq_enable, 1520 .disable = clk_pll_iddq_disable, 1521 .recalc_rate = clk_pllre_recalc_rate, 1522 .round_rate = clk_pllre_round_rate, 1523 .set_rate = clk_pllre_set_rate, 1524 }; 1525 1526 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1527 .is_enabled = clk_pll_is_enabled, 1528 .enable = clk_plle_tegra114_enable, 1529 .disable = clk_plle_tegra114_disable, 1530 .recalc_rate = clk_pll_recalc_rate, 1531 }; 1532 1533 1534 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1535 void __iomem *clk_base, void __iomem *pmc, 1536 unsigned long flags, 1537 struct tegra_clk_pll_params *pll_params, 1538 spinlock_t *lock) 1539 { 1540 struct tegra_clk_pll *pll; 1541 struct clk *clk, *parent; 1542 unsigned long parent_rate; 1543 int err; 1544 u32 val, val_iddq; 1545 1546 parent = __clk_lookup(parent_name); 1547 if (!parent) { 1548 WARN(1, "parent clk %s of %s must be registered first\n", 1549 name, parent_name); 1550 return ERR_PTR(-EINVAL); 1551 } 1552 1553 if (!pll_params->pdiv_tohw) 1554 return ERR_PTR(-EINVAL); 1555 1556 parent_rate = __clk_get_rate(parent); 1557 1558 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1559 1560 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1561 if (err) 1562 return ERR_PTR(err); 1563 1564 val = readl_relaxed(clk_base + pll_params->base_reg); 1565 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1566 1567 if (val & PLL_BASE_ENABLE) 1568 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1569 else { 1570 val_iddq |= BIT(pll_params->iddq_bit_idx); 1571 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1572 } 1573 1574 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1575 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1576 if (IS_ERR(pll)) 1577 return ERR_CAST(pll); 1578 1579 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1580 &tegra_clk_pllxc_ops); 1581 if (IS_ERR(clk)) 1582 kfree(pll); 1583 1584 return clk; 1585 } 1586 1587 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1588 void __iomem *clk_base, void __iomem *pmc, 1589 unsigned long flags, 1590 struct tegra_clk_pll_params *pll_params, 1591 spinlock_t *lock, unsigned long parent_rate) 1592 { 1593 u32 val; 1594 struct tegra_clk_pll *pll; 1595 struct clk *clk; 1596 1597 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; 1598 1599 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1600 1601 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1602 if (IS_ERR(pll)) 1603 return ERR_CAST(pll); 1604 1605 /* program minimum rate by default */ 1606 1607 val = pll_readl_base(pll); 1608 if (val & PLL_BASE_ENABLE) 1609 WARN_ON(val & pll_params->iddq_bit_idx); 1610 else { 1611 int m; 1612 1613 m = _pll_fixed_mdiv(pll_params, parent_rate); 1614 val = m << divm_shift(pll); 1615 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 1616 pll_writel_base(val, pll); 1617 } 1618 1619 /* disable lock override */ 1620 1621 val = pll_readl_misc(pll); 1622 val &= ~BIT(29); 1623 pll_writel_misc(val, pll); 1624 1625 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1626 &tegra_clk_pllre_ops); 1627 if (IS_ERR(clk)) 1628 kfree(pll); 1629 1630 return clk; 1631 } 1632 1633 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1634 void __iomem *clk_base, void __iomem *pmc, 1635 unsigned long flags, 1636 struct tegra_clk_pll_params *pll_params, 1637 spinlock_t *lock) 1638 { 1639 struct tegra_clk_pll *pll; 1640 struct clk *clk, *parent; 1641 unsigned long parent_rate; 1642 1643 if (!pll_params->pdiv_tohw) 1644 return ERR_PTR(-EINVAL); 1645 1646 parent = __clk_lookup(parent_name); 1647 if (!parent) { 1648 WARN(1, "parent clk %s of %s must be registered first\n", 1649 name, parent_name); 1650 return ERR_PTR(-EINVAL); 1651 } 1652 1653 parent_rate = __clk_get_rate(parent); 1654 1655 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1656 1657 pll_params->flags |= TEGRA_PLL_BYPASS; 1658 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1659 pll_params->flags |= TEGRA_PLLM; 1660 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1661 if (IS_ERR(pll)) 1662 return ERR_CAST(pll); 1663 1664 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1665 &tegra_clk_pllm_ops); 1666 if (IS_ERR(clk)) 1667 kfree(pll); 1668 1669 return clk; 1670 } 1671 1672 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1673 void __iomem *clk_base, void __iomem *pmc, 1674 unsigned long flags, 1675 struct tegra_clk_pll_params *pll_params, 1676 spinlock_t *lock) 1677 { 1678 struct clk *parent, *clk; 1679 struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1680 struct tegra_clk_pll *pll; 1681 struct tegra_clk_pll_freq_table cfg; 1682 unsigned long parent_rate; 1683 1684 if (!p_tohw) 1685 return ERR_PTR(-EINVAL); 1686 1687 parent = __clk_lookup(parent_name); 1688 if (!parent) { 1689 WARN(1, "parent clk %s of %s must be registered first\n", 1690 name, parent_name); 1691 return ERR_PTR(-EINVAL); 1692 } 1693 1694 parent_rate = __clk_get_rate(parent); 1695 1696 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1697 1698 pll_params->flags |= TEGRA_PLL_BYPASS; 1699 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1700 if (IS_ERR(pll)) 1701 return ERR_CAST(pll); 1702 1703 /* 1704 * Most of PLLC register fields are shadowed, and can not be read 1705 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1706 * Initialize PLL to default state: disabled, reset; shadow registers 1707 * loaded with default parameters; dividers are preset for half of 1708 * minimum VCO rate (the latter assured that shadowed divider settings 1709 * are within supported range). 1710 */ 1711 1712 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1713 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1714 1715 while (p_tohw->pdiv) { 1716 if (p_tohw->pdiv == 2) { 1717 cfg.p = p_tohw->hw_val; 1718 break; 1719 } 1720 p_tohw++; 1721 } 1722 1723 if (!p_tohw->pdiv) { 1724 WARN_ON(1); 1725 return ERR_PTR(-EINVAL); 1726 } 1727 1728 pll_writel_base(0, pll); 1729 _update_pll_mnp(pll, &cfg); 1730 1731 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1732 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1733 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1734 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1735 1736 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1737 1738 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1739 &tegra_clk_pllc_ops); 1740 if (IS_ERR(clk)) 1741 kfree(pll); 1742 1743 return clk; 1744 } 1745 1746 struct clk *tegra_clk_register_plle_tegra114(const char *name, 1747 const char *parent_name, 1748 void __iomem *clk_base, unsigned long flags, 1749 struct tegra_clk_pll_params *pll_params, 1750 spinlock_t *lock) 1751 { 1752 struct tegra_clk_pll *pll; 1753 struct clk *clk; 1754 u32 val, val_aux; 1755 1756 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1757 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1758 if (IS_ERR(pll)) 1759 return ERR_CAST(pll); 1760 1761 /* ensure parent is set to pll_re_vco */ 1762 1763 val = pll_readl_base(pll); 1764 val_aux = pll_readl(pll_params->aux_reg, pll); 1765 1766 if (val & PLL_BASE_ENABLE) { 1767 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1768 (val_aux & PLLE_AUX_PLLP_SEL)) 1769 WARN(1, "pll_e enabled with unsupported parent %s\n", 1770 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1771 "pll_re_vco"); 1772 } else { 1773 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1774 pll_writel(val_aux, pll_params->aux_reg, pll); 1775 } 1776 1777 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1778 &tegra_clk_plle_tegra114_ops); 1779 if (IS_ERR(clk)) 1780 kfree(pll); 1781 1782 return clk; 1783 } 1784 #endif 1785 1786 #ifdef CONFIG_ARCH_TEGRA_124_SOC 1787 static const struct clk_ops tegra_clk_pllss_ops = { 1788 .is_enabled = clk_pll_is_enabled, 1789 .enable = clk_pll_iddq_enable, 1790 .disable = clk_pll_iddq_disable, 1791 .recalc_rate = clk_pll_recalc_rate, 1792 .round_rate = clk_pll_ramp_round_rate, 1793 .set_rate = clk_pllxc_set_rate, 1794 }; 1795 1796 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 1797 void __iomem *clk_base, unsigned long flags, 1798 struct tegra_clk_pll_params *pll_params, 1799 spinlock_t *lock) 1800 { 1801 struct tegra_clk_pll *pll; 1802 struct clk *clk, *parent; 1803 struct tegra_clk_pll_freq_table cfg; 1804 unsigned long parent_rate; 1805 u32 val; 1806 int i; 1807 1808 if (!pll_params->div_nmp) 1809 return ERR_PTR(-EINVAL); 1810 1811 parent = __clk_lookup(parent_name); 1812 if (!parent) { 1813 WARN(1, "parent clk %s of %s must be registered first\n", 1814 name, parent_name); 1815 return ERR_PTR(-EINVAL); 1816 } 1817 1818 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK; 1819 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1820 if (IS_ERR(pll)) 1821 return ERR_CAST(pll); 1822 1823 val = pll_readl_base(pll); 1824 val &= ~PLLSS_REF_SRC_SEL_MASK; 1825 pll_writel_base(val, pll); 1826 1827 parent_rate = __clk_get_rate(parent); 1828 1829 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1830 1831 /* initialize PLL to minimum rate */ 1832 1833 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1834 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1835 1836 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 1837 ; 1838 if (!i) { 1839 kfree(pll); 1840 return ERR_PTR(-EINVAL); 1841 } 1842 1843 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 1844 1845 _update_pll_mnp(pll, &cfg); 1846 1847 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 1848 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 1849 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 1850 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1851 1852 val = pll_readl_base(pll); 1853 if (val & PLL_BASE_ENABLE) { 1854 if (val & BIT(pll_params->iddq_bit_idx)) { 1855 WARN(1, "%s is on but IDDQ set\n", name); 1856 kfree(pll); 1857 return ERR_PTR(-EINVAL); 1858 } 1859 } else 1860 val |= BIT(pll_params->iddq_bit_idx); 1861 1862 val &= ~PLLSS_LOCK_OVERRIDE; 1863 pll_writel_base(val, pll); 1864 1865 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1866 &tegra_clk_pllss_ops); 1867 1868 if (IS_ERR(clk)) 1869 kfree(pll); 1870 1871 return clk; 1872 } 1873 #endif 1874