1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 69 #define PLLE_MISC_SETUP_BASE_SHIFT 16 70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 71 #define PLLE_MISC_LOCK_ENABLE BIT(9) 72 #define PLLE_MISC_READY BIT(15) 73 #define PLLE_MISC_SETUP_EX_SHIFT 2 74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 76 PLLE_MISC_SETUP_EX_MASK) 77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 78 79 #define PLLE_SS_CTRL 0x68 80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 82 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 83 #define PLLE_SS_CNTL_CENTER BIT(14) 84 #define PLLE_SS_CNTL_INVERT BIT(15) 85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 86 PLLE_SS_CNTL_SSC_BYP) 87 #define PLLE_SS_MAX_MASK 0x1ff 88 #define PLLE_SS_MAX_VAL 0x25 89 #define PLLE_SS_INC_MASK (0xff << 16) 90 #define PLLE_SS_INC_VAL (0x1 << 16) 91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 93 #define PLLE_SS_COEFFICIENTS_MASK \ 94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 95 #define PLLE_SS_COEFFICIENTS_VAL \ 96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 97 98 #define PLLE_AUX_PLLP_SEL BIT(2) 99 #define PLLE_AUX_USE_LOCKDET BIT(3) 100 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 101 #define PLLE_AUX_SS_SWCTL BIT(6) 102 #define PLLE_AUX_SEQ_ENABLE BIT(24) 103 #define PLLE_AUX_SEQ_START_STATE BIT(25) 104 #define PLLE_AUX_PLLRE_SEL BIT(28) 105 106 #define XUSBIO_PLL_CFG0 0x51c 107 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 108 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 109 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 110 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 111 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 112 113 #define SATA_PLL_CFG0 0x490 114 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 115 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 116 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 117 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 118 119 #define PLLE_MISC_PLLE_PTS BIT(8) 120 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 121 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 122 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 123 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 124 #define PLLE_MISC_VREG_CTRL_SHIFT 2 125 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 126 127 #define PLLCX_MISC_STROBE BIT(31) 128 #define PLLCX_MISC_RESET BIT(30) 129 #define PLLCX_MISC_SDM_DIV_SHIFT 28 130 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 131 #define PLLCX_MISC_FILT_DIV_SHIFT 26 132 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 133 #define PLLCX_MISC_ALPHA_SHIFT 18 134 #define PLLCX_MISC_DIV_LOW_RANGE \ 135 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 136 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 137 #define PLLCX_MISC_DIV_HIGH_RANGE \ 138 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 139 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 140 #define PLLCX_MISC_COEF_LOW_RANGE \ 141 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 142 #define PLLCX_MISC_KA_SHIFT 2 143 #define PLLCX_MISC_KB_SHIFT 9 144 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 145 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 146 PLLCX_MISC_DIV_LOW_RANGE | \ 147 PLLCX_MISC_RESET) 148 #define PLLCX_MISC1_DEFAULT 0x000d2308 149 #define PLLCX_MISC2_DEFAULT 0x30211200 150 #define PLLCX_MISC3_DEFAULT 0x200 151 152 #define PMC_SATA_PWRGT 0x1ac 153 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 154 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 155 156 #define PLLSS_MISC_KCP 0 157 #define PLLSS_MISC_KVCO 0 158 #define PLLSS_MISC_SETUP 0 159 #define PLLSS_EN_SDM 0 160 #define PLLSS_EN_SSC 0 161 #define PLLSS_EN_DITHER2 0 162 #define PLLSS_EN_DITHER 1 163 #define PLLSS_SDM_RESET 0 164 #define PLLSS_CLAMP 0 165 #define PLLSS_SDM_SSC_MAX 0 166 #define PLLSS_SDM_SSC_MIN 0 167 #define PLLSS_SDM_SSC_STEP 0 168 #define PLLSS_SDM_DIN 0 169 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 170 (PLLSS_MISC_KVCO << 24) | \ 171 PLLSS_MISC_SETUP) 172 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 173 (PLLSS_EN_SSC << 30) | \ 174 (PLLSS_EN_DITHER2 << 29) | \ 175 (PLLSS_EN_DITHER << 28) | \ 176 (PLLSS_SDM_RESET) << 27 | \ 177 (PLLSS_CLAMP << 22)) 178 #define PLLSS_CTRL1_DEFAULT \ 179 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 180 #define PLLSS_CTRL2_DEFAULT \ 181 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 182 #define PLLSS_LOCK_OVERRIDE BIT(24) 183 #define PLLSS_REF_SRC_SEL_SHIFT 25 184 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 185 186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 187 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 188 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 189 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 190 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p) 191 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p) 192 193 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 194 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 195 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 196 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 197 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) 198 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) 199 200 #define mask(w) ((1 << (w)) - 1) 201 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 202 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 203 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 204 mask(p->params->div_nmp->divp_width)) 205 #define sdm_din_mask(p) p->params->sdm_din_mask 206 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask 207 208 #define divm_shift(p) (p)->params->div_nmp->divm_shift 209 #define divn_shift(p) (p)->params->div_nmp->divn_shift 210 #define divp_shift(p) (p)->params->div_nmp->divp_shift 211 212 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 213 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 214 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 215 216 #define divm_max(p) (divm_mask(p)) 217 #define divn_max(p) (divn_mask(p)) 218 #define divp_max(p) (1 << (divp_mask(p))) 219 220 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 221 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 222 223 static struct div_nmp default_nmp = { 224 .divn_shift = PLL_BASE_DIVN_SHIFT, 225 .divn_width = PLL_BASE_DIVN_WIDTH, 226 .divm_shift = PLL_BASE_DIVM_SHIFT, 227 .divm_width = PLL_BASE_DIVM_WIDTH, 228 .divp_shift = PLL_BASE_DIVP_SHIFT, 229 .divp_width = PLL_BASE_DIVP_WIDTH, 230 }; 231 232 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 233 { 234 u32 val; 235 236 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 237 return; 238 239 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 240 return; 241 242 val = pll_readl_misc(pll); 243 val |= BIT(pll->params->lock_enable_bit_idx); 244 pll_writel_misc(val, pll); 245 } 246 247 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 248 { 249 int i; 250 u32 val, lock_mask; 251 void __iomem *lock_addr; 252 253 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 254 udelay(pll->params->lock_delay); 255 return 0; 256 } 257 258 lock_addr = pll->clk_base; 259 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 260 lock_addr += pll->params->misc_reg; 261 else 262 lock_addr += pll->params->base_reg; 263 264 lock_mask = pll->params->lock_mask; 265 266 for (i = 0; i < pll->params->lock_delay; i++) { 267 val = readl_relaxed(lock_addr); 268 if ((val & lock_mask) == lock_mask) { 269 udelay(PLL_POST_LOCK_DELAY); 270 return 0; 271 } 272 udelay(2); /* timeout = 2 * lock time */ 273 } 274 275 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 276 clk_hw_get_name(&pll->hw)); 277 278 return -1; 279 } 280 281 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 282 { 283 return clk_pll_wait_for_lock(pll); 284 } 285 286 static int clk_pll_is_enabled(struct clk_hw *hw) 287 { 288 struct tegra_clk_pll *pll = to_clk_pll(hw); 289 u32 val; 290 291 if (pll->params->flags & TEGRA_PLLM) { 292 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 293 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 294 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 295 } 296 297 val = pll_readl_base(pll); 298 299 return val & PLL_BASE_ENABLE ? 1 : 0; 300 } 301 302 static void _clk_pll_enable(struct clk_hw *hw) 303 { 304 struct tegra_clk_pll *pll = to_clk_pll(hw); 305 u32 val; 306 307 if (pll->params->iddq_reg) { 308 val = pll_readl(pll->params->iddq_reg, pll); 309 val &= ~BIT(pll->params->iddq_bit_idx); 310 pll_writel(val, pll->params->iddq_reg, pll); 311 udelay(2); 312 } 313 314 if (pll->params->reset_reg) { 315 val = pll_readl(pll->params->reset_reg, pll); 316 val &= ~BIT(pll->params->reset_bit_idx); 317 pll_writel(val, pll->params->reset_reg, pll); 318 } 319 320 clk_pll_enable_lock(pll); 321 322 val = pll_readl_base(pll); 323 if (pll->params->flags & TEGRA_PLL_BYPASS) 324 val &= ~PLL_BASE_BYPASS; 325 val |= PLL_BASE_ENABLE; 326 pll_writel_base(val, pll); 327 328 if (pll->params->flags & TEGRA_PLLM) { 329 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 330 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 331 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 332 } 333 } 334 335 static void _clk_pll_disable(struct clk_hw *hw) 336 { 337 struct tegra_clk_pll *pll = to_clk_pll(hw); 338 u32 val; 339 340 val = pll_readl_base(pll); 341 if (pll->params->flags & TEGRA_PLL_BYPASS) 342 val &= ~PLL_BASE_BYPASS; 343 val &= ~PLL_BASE_ENABLE; 344 pll_writel_base(val, pll); 345 346 if (pll->params->flags & TEGRA_PLLM) { 347 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 348 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 349 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 350 } 351 352 if (pll->params->reset_reg) { 353 val = pll_readl(pll->params->reset_reg, pll); 354 val |= BIT(pll->params->reset_bit_idx); 355 pll_writel(val, pll->params->reset_reg, pll); 356 } 357 358 if (pll->params->iddq_reg) { 359 val = pll_readl(pll->params->iddq_reg, pll); 360 val |= BIT(pll->params->iddq_bit_idx); 361 pll_writel(val, pll->params->iddq_reg, pll); 362 udelay(2); 363 } 364 } 365 366 static int clk_pll_enable(struct clk_hw *hw) 367 { 368 struct tegra_clk_pll *pll = to_clk_pll(hw); 369 unsigned long flags = 0; 370 int ret; 371 372 if (pll->lock) 373 spin_lock_irqsave(pll->lock, flags); 374 375 _clk_pll_enable(hw); 376 377 ret = clk_pll_wait_for_lock(pll); 378 379 if (pll->lock) 380 spin_unlock_irqrestore(pll->lock, flags); 381 382 return ret; 383 } 384 385 static void clk_pll_disable(struct clk_hw *hw) 386 { 387 struct tegra_clk_pll *pll = to_clk_pll(hw); 388 unsigned long flags = 0; 389 390 if (pll->lock) 391 spin_lock_irqsave(pll->lock, flags); 392 393 _clk_pll_disable(hw); 394 395 if (pll->lock) 396 spin_unlock_irqrestore(pll->lock, flags); 397 } 398 399 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 400 { 401 struct tegra_clk_pll *pll = to_clk_pll(hw); 402 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 403 404 if (p_tohw) { 405 while (p_tohw->pdiv) { 406 if (p_div <= p_tohw->pdiv) 407 return p_tohw->hw_val; 408 p_tohw++; 409 } 410 return -EINVAL; 411 } 412 return -EINVAL; 413 } 414 415 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 416 { 417 struct tegra_clk_pll *pll = to_clk_pll(hw); 418 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 419 420 if (p_tohw) { 421 while (p_tohw->pdiv) { 422 if (p_div_hw == p_tohw->hw_val) 423 return p_tohw->pdiv; 424 p_tohw++; 425 } 426 return -EINVAL; 427 } 428 429 return 1 << p_div_hw; 430 } 431 432 static int _get_table_rate(struct clk_hw *hw, 433 struct tegra_clk_pll_freq_table *cfg, 434 unsigned long rate, unsigned long parent_rate) 435 { 436 struct tegra_clk_pll *pll = to_clk_pll(hw); 437 struct tegra_clk_pll_freq_table *sel; 438 int p; 439 440 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 441 if (sel->input_rate == parent_rate && 442 sel->output_rate == rate) 443 break; 444 445 if (sel->input_rate == 0) 446 return -EINVAL; 447 448 if (pll->params->pdiv_tohw) { 449 p = _p_div_to_hw(hw, sel->p); 450 if (p < 0) 451 return p; 452 } else { 453 p = ilog2(sel->p); 454 } 455 456 cfg->input_rate = sel->input_rate; 457 cfg->output_rate = sel->output_rate; 458 cfg->m = sel->m; 459 cfg->n = sel->n; 460 cfg->p = p; 461 cfg->cpcon = sel->cpcon; 462 cfg->sdm_data = sel->sdm_data; 463 464 return 0; 465 } 466 467 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 468 unsigned long rate, unsigned long parent_rate) 469 { 470 struct tegra_clk_pll *pll = to_clk_pll(hw); 471 unsigned long cfreq; 472 u32 p_div = 0; 473 int ret; 474 475 switch (parent_rate) { 476 case 12000000: 477 case 26000000: 478 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 479 break; 480 case 13000000: 481 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 482 break; 483 case 16800000: 484 case 19200000: 485 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 486 break; 487 case 9600000: 488 case 28800000: 489 /* 490 * PLL_P_OUT1 rate is not listed in PLLA table 491 */ 492 cfreq = parent_rate / (parent_rate / 1000000); 493 break; 494 default: 495 pr_err("%s Unexpected reference rate %lu\n", 496 __func__, parent_rate); 497 BUG(); 498 } 499 500 /* Raise VCO to guarantee 0.5% accuracy */ 501 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 502 cfg->output_rate <<= 1) 503 p_div++; 504 505 cfg->m = parent_rate / cfreq; 506 cfg->n = cfg->output_rate / cfreq; 507 cfg->cpcon = OUT_OF_TABLE_CPCON; 508 509 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 510 (1 << p_div) > divp_max(pll) 511 || cfg->output_rate > pll->params->vco_max) { 512 return -EINVAL; 513 } 514 515 cfg->output_rate >>= p_div; 516 517 if (pll->params->pdiv_tohw) { 518 ret = _p_div_to_hw(hw, 1 << p_div); 519 if (ret < 0) 520 return ret; 521 else 522 cfg->p = ret; 523 } else 524 cfg->p = p_div; 525 526 return 0; 527 } 528 529 /* 530 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number 531 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as 532 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used 533 * to indicate that SDM is disabled. 534 * 535 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 536 */ 537 static void clk_pll_set_sdm_data(struct clk_hw *hw, 538 struct tegra_clk_pll_freq_table *cfg) 539 { 540 struct tegra_clk_pll *pll = to_clk_pll(hw); 541 u32 val; 542 bool enabled; 543 544 if (!pll->params->sdm_din_reg) 545 return; 546 547 if (cfg->sdm_data) { 548 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); 549 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); 550 pll_writel_sdm_din(val, pll); 551 } 552 553 val = pll_readl_sdm_ctrl(pll); 554 enabled = (val & sdm_en_mask(pll)); 555 556 if (cfg->sdm_data == 0 && enabled) 557 val &= ~pll->params->sdm_ctrl_en_mask; 558 559 if (cfg->sdm_data != 0 && !enabled) 560 val |= pll->params->sdm_ctrl_en_mask; 561 562 pll_writel_sdm_ctrl(val, pll); 563 } 564 565 static void _update_pll_mnp(struct tegra_clk_pll *pll, 566 struct tegra_clk_pll_freq_table *cfg) 567 { 568 u32 val; 569 struct tegra_clk_pll_params *params = pll->params; 570 struct div_nmp *div_nmp = params->div_nmp; 571 572 if ((params->flags & TEGRA_PLLM) && 573 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 574 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 575 val = pll_override_readl(params->pmc_divp_reg, pll); 576 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 577 val |= cfg->p << div_nmp->override_divp_shift; 578 pll_override_writel(val, params->pmc_divp_reg, pll); 579 580 val = pll_override_readl(params->pmc_divnm_reg, pll); 581 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | 582 ~(divn_mask(pll) << div_nmp->override_divn_shift); 583 val |= (cfg->m << div_nmp->override_divm_shift) | 584 (cfg->n << div_nmp->override_divn_shift); 585 pll_override_writel(val, params->pmc_divnm_reg, pll); 586 } else { 587 val = pll_readl_base(pll); 588 589 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 590 divp_mask_shifted(pll)); 591 592 val |= (cfg->m << divm_shift(pll)) | 593 (cfg->n << divn_shift(pll)) | 594 (cfg->p << divp_shift(pll)); 595 596 pll_writel_base(val, pll); 597 598 clk_pll_set_sdm_data(&pll->hw, cfg); 599 } 600 } 601 602 static void _get_pll_mnp(struct tegra_clk_pll *pll, 603 struct tegra_clk_pll_freq_table *cfg) 604 { 605 u32 val; 606 struct tegra_clk_pll_params *params = pll->params; 607 struct div_nmp *div_nmp = params->div_nmp; 608 609 if ((params->flags & TEGRA_PLLM) && 610 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 611 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 612 val = pll_override_readl(params->pmc_divp_reg, pll); 613 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 614 615 val = pll_override_readl(params->pmc_divnm_reg, pll); 616 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 617 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 618 } else { 619 val = pll_readl_base(pll); 620 621 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 622 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 623 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 624 625 if (pll->params->sdm_din_reg) { 626 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { 627 val = pll_readl_sdm_din(pll); 628 val &= sdm_din_mask(pll); 629 cfg->sdm_data = sdin_din_to_data(val); 630 } 631 } 632 } 633 } 634 635 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 636 struct tegra_clk_pll_freq_table *cfg, 637 unsigned long rate) 638 { 639 u32 val; 640 641 val = pll_readl_misc(pll); 642 643 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 644 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 645 646 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 647 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 648 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 649 val |= 1 << PLL_MISC_LFCON_SHIFT; 650 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 651 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 652 if (rate >= (pll->params->vco_max >> 1)) 653 val |= 1 << PLL_MISC_DCCON_SHIFT; 654 } 655 656 pll_writel_misc(val, pll); 657 } 658 659 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 660 unsigned long rate) 661 { 662 struct tegra_clk_pll *pll = to_clk_pll(hw); 663 int state, ret = 0; 664 665 state = clk_pll_is_enabled(hw); 666 667 if (state) 668 _clk_pll_disable(hw); 669 670 _update_pll_mnp(pll, cfg); 671 672 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 673 _update_pll_cpcon(pll, cfg, rate); 674 675 if (state) { 676 _clk_pll_enable(hw); 677 ret = clk_pll_wait_for_lock(pll); 678 } 679 680 return ret; 681 } 682 683 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 684 unsigned long parent_rate) 685 { 686 struct tegra_clk_pll *pll = to_clk_pll(hw); 687 struct tegra_clk_pll_freq_table cfg, old_cfg; 688 unsigned long flags = 0; 689 int ret = 0; 690 691 if (pll->params->flags & TEGRA_PLL_FIXED) { 692 if (rate != pll->params->fixed_rate) { 693 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 694 __func__, clk_hw_get_name(hw), 695 pll->params->fixed_rate, rate); 696 return -EINVAL; 697 } 698 return 0; 699 } 700 701 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 702 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { 703 pr_err("%s: Failed to set %s rate %lu\n", __func__, 704 clk_hw_get_name(hw), rate); 705 WARN_ON(1); 706 return -EINVAL; 707 } 708 if (pll->lock) 709 spin_lock_irqsave(pll->lock, flags); 710 711 _get_pll_mnp(pll, &old_cfg); 712 713 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || 714 old_cfg.sdm_data != cfg.sdm_data) 715 ret = _program_pll(hw, &cfg, rate); 716 717 if (pll->lock) 718 spin_unlock_irqrestore(pll->lock, flags); 719 720 return ret; 721 } 722 723 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 724 unsigned long *prate) 725 { 726 struct tegra_clk_pll *pll = to_clk_pll(hw); 727 struct tegra_clk_pll_freq_table cfg; 728 729 if (pll->params->flags & TEGRA_PLL_FIXED) 730 return pll->params->fixed_rate; 731 732 /* PLLM is used for memory; we do not change rate */ 733 if (pll->params->flags & TEGRA_PLLM) 734 return clk_hw_get_rate(hw); 735 736 if (_get_table_rate(hw, &cfg, rate, *prate) && 737 pll->params->calc_rate(hw, &cfg, rate, *prate)) 738 return -EINVAL; 739 740 return cfg.output_rate; 741 } 742 743 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 744 unsigned long parent_rate) 745 { 746 struct tegra_clk_pll *pll = to_clk_pll(hw); 747 struct tegra_clk_pll_freq_table cfg; 748 u32 val; 749 u64 rate = parent_rate; 750 int pdiv; 751 752 val = pll_readl_base(pll); 753 754 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 755 return parent_rate; 756 757 if ((pll->params->flags & TEGRA_PLL_FIXED) && 758 !(val & PLL_BASE_OVERRIDE)) { 759 struct tegra_clk_pll_freq_table sel; 760 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 761 parent_rate)) { 762 pr_err("Clock %s has unknown fixed frequency\n", 763 clk_hw_get_name(hw)); 764 BUG(); 765 } 766 return pll->params->fixed_rate; 767 } 768 769 _get_pll_mnp(pll, &cfg); 770 771 pdiv = _hw_to_p_div(hw, cfg.p); 772 if (pdiv < 0) { 773 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 774 __clk_get_name(hw->clk), cfg.p); 775 pdiv = 1; 776 } 777 778 if (pll->params->set_gain) 779 pll->params->set_gain(&cfg); 780 781 cfg.m *= pdiv; 782 783 rate *= cfg.n; 784 do_div(rate, cfg.m); 785 786 return rate; 787 } 788 789 static int clk_plle_training(struct tegra_clk_pll *pll) 790 { 791 u32 val; 792 unsigned long timeout; 793 794 if (!pll->pmc) 795 return -ENOSYS; 796 797 /* 798 * PLLE is already disabled, and setup cleared; 799 * create falling edge on PLLE IDDQ input. 800 */ 801 val = readl(pll->pmc + PMC_SATA_PWRGT); 802 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 803 writel(val, pll->pmc + PMC_SATA_PWRGT); 804 805 val = readl(pll->pmc + PMC_SATA_PWRGT); 806 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 807 writel(val, pll->pmc + PMC_SATA_PWRGT); 808 809 val = readl(pll->pmc + PMC_SATA_PWRGT); 810 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 811 writel(val, pll->pmc + PMC_SATA_PWRGT); 812 813 val = pll_readl_misc(pll); 814 815 timeout = jiffies + msecs_to_jiffies(100); 816 while (1) { 817 val = pll_readl_misc(pll); 818 if (val & PLLE_MISC_READY) 819 break; 820 if (time_after(jiffies, timeout)) { 821 pr_err("%s: timeout waiting for PLLE\n", __func__); 822 return -EBUSY; 823 } 824 udelay(300); 825 } 826 827 return 0; 828 } 829 830 static int clk_plle_enable(struct clk_hw *hw) 831 { 832 struct tegra_clk_pll *pll = to_clk_pll(hw); 833 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 834 struct tegra_clk_pll_freq_table sel; 835 u32 val; 836 int err; 837 838 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 839 return -EINVAL; 840 841 clk_pll_disable(hw); 842 843 val = pll_readl_misc(pll); 844 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 845 pll_writel_misc(val, pll); 846 847 val = pll_readl_misc(pll); 848 if (!(val & PLLE_MISC_READY)) { 849 err = clk_plle_training(pll); 850 if (err) 851 return err; 852 } 853 854 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 855 /* configure dividers */ 856 val = pll_readl_base(pll); 857 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 858 divm_mask_shifted(pll)); 859 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 860 val |= sel.m << divm_shift(pll); 861 val |= sel.n << divn_shift(pll); 862 val |= sel.p << divp_shift(pll); 863 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 864 pll_writel_base(val, pll); 865 } 866 867 val = pll_readl_misc(pll); 868 val |= PLLE_MISC_SETUP_VALUE; 869 val |= PLLE_MISC_LOCK_ENABLE; 870 pll_writel_misc(val, pll); 871 872 val = readl(pll->clk_base + PLLE_SS_CTRL); 873 val &= ~PLLE_SS_COEFFICIENTS_MASK; 874 val |= PLLE_SS_DISABLE; 875 writel(val, pll->clk_base + PLLE_SS_CTRL); 876 877 val = pll_readl_base(pll); 878 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 879 pll_writel_base(val, pll); 880 881 clk_pll_wait_for_lock(pll); 882 883 return 0; 884 } 885 886 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 887 unsigned long parent_rate) 888 { 889 struct tegra_clk_pll *pll = to_clk_pll(hw); 890 u32 val = pll_readl_base(pll); 891 u32 divn = 0, divm = 0, divp = 0; 892 u64 rate = parent_rate; 893 894 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 895 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 896 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 897 divm *= divp; 898 899 rate *= divn; 900 do_div(rate, divm); 901 return rate; 902 } 903 904 const struct clk_ops tegra_clk_pll_ops = { 905 .is_enabled = clk_pll_is_enabled, 906 .enable = clk_pll_enable, 907 .disable = clk_pll_disable, 908 .recalc_rate = clk_pll_recalc_rate, 909 .round_rate = clk_pll_round_rate, 910 .set_rate = clk_pll_set_rate, 911 }; 912 913 const struct clk_ops tegra_clk_plle_ops = { 914 .recalc_rate = clk_plle_recalc_rate, 915 .is_enabled = clk_pll_is_enabled, 916 .disable = clk_pll_disable, 917 .enable = clk_plle_enable, 918 }; 919 920 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 921 unsigned long parent_rate) 922 { 923 u16 mdiv = parent_rate / pll_params->cf_min; 924 925 if (pll_params->flags & TEGRA_MDIV_NEW) 926 return (!pll_params->mdiv_default ? mdiv : 927 min(mdiv, pll_params->mdiv_default)); 928 929 if (pll_params->mdiv_default) 930 return pll_params->mdiv_default; 931 932 if (parent_rate > pll_params->cf_max) 933 return 2; 934 else 935 return 1; 936 } 937 938 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 939 struct tegra_clk_pll_freq_table *cfg, 940 unsigned long rate, unsigned long parent_rate) 941 { 942 struct tegra_clk_pll *pll = to_clk_pll(hw); 943 unsigned int p; 944 int p_div; 945 946 if (!rate) 947 return -EINVAL; 948 949 p = DIV_ROUND_UP(pll->params->vco_min, rate); 950 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 951 cfg->output_rate = rate * p; 952 cfg->n = cfg->output_rate * cfg->m / parent_rate; 953 cfg->input_rate = parent_rate; 954 955 p_div = _p_div_to_hw(hw, p); 956 if (p_div < 0) 957 return p_div; 958 959 cfg->p = p_div; 960 961 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 962 return -EINVAL; 963 964 return 0; 965 } 966 967 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 968 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 969 defined(CONFIG_ARCH_TEGRA_132_SOC) 970 971 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) 972 { 973 struct tegra_clk_pll *pll = to_clk_pll(hw); 974 975 return (u16)_pll_fixed_mdiv(pll->params, input_rate); 976 } 977 978 static unsigned long _clip_vco_min(unsigned long vco_min, 979 unsigned long parent_rate) 980 { 981 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 982 } 983 984 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 985 void __iomem *clk_base, 986 unsigned long parent_rate) 987 { 988 u32 val; 989 u32 step_a, step_b; 990 991 switch (parent_rate) { 992 case 12000000: 993 case 13000000: 994 case 26000000: 995 step_a = 0x2B; 996 step_b = 0x0B; 997 break; 998 case 16800000: 999 step_a = 0x1A; 1000 step_b = 0x09; 1001 break; 1002 case 19200000: 1003 step_a = 0x12; 1004 step_b = 0x08; 1005 break; 1006 default: 1007 pr_err("%s: Unexpected reference rate %lu\n", 1008 __func__, parent_rate); 1009 WARN_ON(1); 1010 return -EINVAL; 1011 } 1012 1013 val = step_a << pll_params->stepa_shift; 1014 val |= step_b << pll_params->stepb_shift; 1015 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1016 1017 return 0; 1018 } 1019 1020 static int _pll_ramp_calc_pll(struct clk_hw *hw, 1021 struct tegra_clk_pll_freq_table *cfg, 1022 unsigned long rate, unsigned long parent_rate) 1023 { 1024 struct tegra_clk_pll *pll = to_clk_pll(hw); 1025 int err = 0; 1026 1027 err = _get_table_rate(hw, cfg, rate, parent_rate); 1028 if (err < 0) 1029 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 1030 else { 1031 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 1032 WARN_ON(1); 1033 err = -EINVAL; 1034 goto out; 1035 } 1036 } 1037 1038 if (cfg->p > pll->params->max_p) 1039 err = -EINVAL; 1040 1041 out: 1042 return err; 1043 } 1044 1045 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 1046 unsigned long parent_rate) 1047 { 1048 struct tegra_clk_pll *pll = to_clk_pll(hw); 1049 struct tegra_clk_pll_freq_table cfg, old_cfg; 1050 unsigned long flags = 0; 1051 int ret; 1052 1053 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1054 if (ret < 0) 1055 return ret; 1056 1057 if (pll->lock) 1058 spin_lock_irqsave(pll->lock, flags); 1059 1060 _get_pll_mnp(pll, &old_cfg); 1061 1062 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1063 ret = _program_pll(hw, &cfg, rate); 1064 1065 if (pll->lock) 1066 spin_unlock_irqrestore(pll->lock, flags); 1067 1068 return ret; 1069 } 1070 1071 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 1072 unsigned long *prate) 1073 { 1074 struct tegra_clk_pll *pll = to_clk_pll(hw); 1075 struct tegra_clk_pll_freq_table cfg; 1076 int ret, p_div; 1077 u64 output_rate = *prate; 1078 1079 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1080 if (ret < 0) 1081 return ret; 1082 1083 p_div = _hw_to_p_div(hw, cfg.p); 1084 if (p_div < 0) 1085 return p_div; 1086 1087 if (pll->params->set_gain) 1088 pll->params->set_gain(&cfg); 1089 1090 output_rate *= cfg.n; 1091 do_div(output_rate, cfg.m * p_div); 1092 1093 return output_rate; 1094 } 1095 1096 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, 1097 unsigned long parent_rate) 1098 { 1099 struct tegra_clk_pll_freq_table cfg; 1100 struct tegra_clk_pll *pll = to_clk_pll(hw); 1101 unsigned long flags = 0; 1102 int state, ret = 0; 1103 1104 if (pll->lock) 1105 spin_lock_irqsave(pll->lock, flags); 1106 1107 state = clk_pll_is_enabled(hw); 1108 if (state) { 1109 if (rate != clk_get_rate(hw->clk)) { 1110 pr_err("%s: Cannot change active PLLM\n", __func__); 1111 ret = -EINVAL; 1112 goto out; 1113 } 1114 goto out; 1115 } 1116 1117 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1118 if (ret < 0) 1119 goto out; 1120 1121 _update_pll_mnp(pll, &cfg); 1122 1123 out: 1124 if (pll->lock) 1125 spin_unlock_irqrestore(pll->lock, flags); 1126 1127 return ret; 1128 } 1129 1130 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1131 { 1132 u32 val; 1133 1134 val = pll_readl_misc(pll); 1135 val |= PLLCX_MISC_STROBE; 1136 pll_writel_misc(val, pll); 1137 udelay(2); 1138 1139 val &= ~PLLCX_MISC_STROBE; 1140 pll_writel_misc(val, pll); 1141 } 1142 1143 static int clk_pllc_enable(struct clk_hw *hw) 1144 { 1145 struct tegra_clk_pll *pll = to_clk_pll(hw); 1146 u32 val; 1147 int ret; 1148 unsigned long flags = 0; 1149 1150 if (pll->lock) 1151 spin_lock_irqsave(pll->lock, flags); 1152 1153 _clk_pll_enable(hw); 1154 udelay(2); 1155 1156 val = pll_readl_misc(pll); 1157 val &= ~PLLCX_MISC_RESET; 1158 pll_writel_misc(val, pll); 1159 udelay(2); 1160 1161 _pllcx_strobe(pll); 1162 1163 ret = clk_pll_wait_for_lock(pll); 1164 1165 if (pll->lock) 1166 spin_unlock_irqrestore(pll->lock, flags); 1167 1168 return ret; 1169 } 1170 1171 static void _clk_pllc_disable(struct clk_hw *hw) 1172 { 1173 struct tegra_clk_pll *pll = to_clk_pll(hw); 1174 u32 val; 1175 1176 _clk_pll_disable(hw); 1177 1178 val = pll_readl_misc(pll); 1179 val |= PLLCX_MISC_RESET; 1180 pll_writel_misc(val, pll); 1181 udelay(2); 1182 } 1183 1184 static void clk_pllc_disable(struct clk_hw *hw) 1185 { 1186 struct tegra_clk_pll *pll = to_clk_pll(hw); 1187 unsigned long flags = 0; 1188 1189 if (pll->lock) 1190 spin_lock_irqsave(pll->lock, flags); 1191 1192 _clk_pllc_disable(hw); 1193 1194 if (pll->lock) 1195 spin_unlock_irqrestore(pll->lock, flags); 1196 } 1197 1198 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1199 unsigned long input_rate, u32 n) 1200 { 1201 u32 val, n_threshold; 1202 1203 switch (input_rate) { 1204 case 12000000: 1205 n_threshold = 70; 1206 break; 1207 case 13000000: 1208 case 26000000: 1209 n_threshold = 71; 1210 break; 1211 case 16800000: 1212 n_threshold = 55; 1213 break; 1214 case 19200000: 1215 n_threshold = 48; 1216 break; 1217 default: 1218 pr_err("%s: Unexpected reference rate %lu\n", 1219 __func__, input_rate); 1220 return -EINVAL; 1221 } 1222 1223 val = pll_readl_misc(pll); 1224 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1225 val |= n <= n_threshold ? 1226 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1227 pll_writel_misc(val, pll); 1228 1229 return 0; 1230 } 1231 1232 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1233 unsigned long parent_rate) 1234 { 1235 struct tegra_clk_pll_freq_table cfg, old_cfg; 1236 struct tegra_clk_pll *pll = to_clk_pll(hw); 1237 unsigned long flags = 0; 1238 int state, ret = 0; 1239 1240 if (pll->lock) 1241 spin_lock_irqsave(pll->lock, flags); 1242 1243 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1244 if (ret < 0) 1245 goto out; 1246 1247 _get_pll_mnp(pll, &old_cfg); 1248 1249 if (cfg.m != old_cfg.m) { 1250 WARN_ON(1); 1251 goto out; 1252 } 1253 1254 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1255 goto out; 1256 1257 state = clk_pll_is_enabled(hw); 1258 if (state) 1259 _clk_pllc_disable(hw); 1260 1261 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1262 if (ret < 0) 1263 goto out; 1264 1265 _update_pll_mnp(pll, &cfg); 1266 1267 if (state) 1268 ret = clk_pllc_enable(hw); 1269 1270 out: 1271 if (pll->lock) 1272 spin_unlock_irqrestore(pll->lock, flags); 1273 1274 return ret; 1275 } 1276 1277 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1278 struct tegra_clk_pll_freq_table *cfg, 1279 unsigned long rate, unsigned long parent_rate) 1280 { 1281 u16 m, n; 1282 u64 output_rate = parent_rate; 1283 1284 m = _pll_fixed_mdiv(pll->params, parent_rate); 1285 n = rate * m / parent_rate; 1286 1287 output_rate *= n; 1288 do_div(output_rate, m); 1289 1290 if (cfg) { 1291 cfg->m = m; 1292 cfg->n = n; 1293 } 1294 1295 return output_rate; 1296 } 1297 1298 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1299 unsigned long parent_rate) 1300 { 1301 struct tegra_clk_pll_freq_table cfg, old_cfg; 1302 struct tegra_clk_pll *pll = to_clk_pll(hw); 1303 unsigned long flags = 0; 1304 int state, ret = 0; 1305 1306 if (pll->lock) 1307 spin_lock_irqsave(pll->lock, flags); 1308 1309 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1310 _get_pll_mnp(pll, &old_cfg); 1311 cfg.p = old_cfg.p; 1312 1313 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1314 state = clk_pll_is_enabled(hw); 1315 if (state) 1316 _clk_pll_disable(hw); 1317 1318 _update_pll_mnp(pll, &cfg); 1319 1320 if (state) { 1321 _clk_pll_enable(hw); 1322 ret = clk_pll_wait_for_lock(pll); 1323 } 1324 } 1325 1326 if (pll->lock) 1327 spin_unlock_irqrestore(pll->lock, flags); 1328 1329 return ret; 1330 } 1331 1332 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1333 unsigned long parent_rate) 1334 { 1335 struct tegra_clk_pll_freq_table cfg; 1336 struct tegra_clk_pll *pll = to_clk_pll(hw); 1337 u64 rate = parent_rate; 1338 1339 _get_pll_mnp(pll, &cfg); 1340 1341 rate *= cfg.n; 1342 do_div(rate, cfg.m); 1343 1344 return rate; 1345 } 1346 1347 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1348 unsigned long *prate) 1349 { 1350 struct tegra_clk_pll *pll = to_clk_pll(hw); 1351 1352 return _pllre_calc_rate(pll, NULL, rate, *prate); 1353 } 1354 1355 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1356 { 1357 struct tegra_clk_pll *pll = to_clk_pll(hw); 1358 struct tegra_clk_pll_freq_table sel; 1359 u32 val; 1360 int ret; 1361 unsigned long flags = 0; 1362 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1363 1364 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1365 return -EINVAL; 1366 1367 if (pll->lock) 1368 spin_lock_irqsave(pll->lock, flags); 1369 1370 val = pll_readl_base(pll); 1371 val &= ~BIT(29); /* Disable lock override */ 1372 pll_writel_base(val, pll); 1373 1374 val = pll_readl(pll->params->aux_reg, pll); 1375 val |= PLLE_AUX_ENABLE_SWCTL; 1376 val &= ~PLLE_AUX_SEQ_ENABLE; 1377 pll_writel(val, pll->params->aux_reg, pll); 1378 udelay(1); 1379 1380 val = pll_readl_misc(pll); 1381 val |= PLLE_MISC_LOCK_ENABLE; 1382 val |= PLLE_MISC_IDDQ_SW_CTRL; 1383 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1384 val |= PLLE_MISC_PLLE_PTS; 1385 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1386 pll_writel_misc(val, pll); 1387 udelay(5); 1388 1389 val = pll_readl(PLLE_SS_CTRL, pll); 1390 val |= PLLE_SS_DISABLE; 1391 pll_writel(val, PLLE_SS_CTRL, pll); 1392 1393 val = pll_readl_base(pll); 1394 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1395 divm_mask_shifted(pll)); 1396 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1397 val |= sel.m << divm_shift(pll); 1398 val |= sel.n << divn_shift(pll); 1399 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1400 pll_writel_base(val, pll); 1401 udelay(1); 1402 1403 _clk_pll_enable(hw); 1404 ret = clk_pll_wait_for_lock(pll); 1405 1406 if (ret < 0) 1407 goto out; 1408 1409 val = pll_readl(PLLE_SS_CTRL, pll); 1410 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1411 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1412 val |= PLLE_SS_COEFFICIENTS_VAL; 1413 pll_writel(val, PLLE_SS_CTRL, pll); 1414 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1415 pll_writel(val, PLLE_SS_CTRL, pll); 1416 udelay(1); 1417 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1418 pll_writel(val, PLLE_SS_CTRL, pll); 1419 udelay(1); 1420 1421 /* Enable hw control of xusb brick pll */ 1422 val = pll_readl_misc(pll); 1423 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1424 pll_writel_misc(val, pll); 1425 1426 val = pll_readl(pll->params->aux_reg, pll); 1427 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1428 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1429 pll_writel(val, pll->params->aux_reg, pll); 1430 udelay(1); 1431 val |= PLLE_AUX_SEQ_ENABLE; 1432 pll_writel(val, pll->params->aux_reg, pll); 1433 1434 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1435 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1436 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1437 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1438 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1439 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1440 udelay(1); 1441 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1442 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1443 1444 /* Enable hw control of SATA pll */ 1445 val = pll_readl(SATA_PLL_CFG0, pll); 1446 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1447 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1448 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1449 pll_writel(val, SATA_PLL_CFG0, pll); 1450 1451 udelay(1); 1452 1453 val = pll_readl(SATA_PLL_CFG0, pll); 1454 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1455 pll_writel(val, SATA_PLL_CFG0, pll); 1456 1457 out: 1458 if (pll->lock) 1459 spin_unlock_irqrestore(pll->lock, flags); 1460 1461 return ret; 1462 } 1463 1464 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1465 { 1466 struct tegra_clk_pll *pll = to_clk_pll(hw); 1467 unsigned long flags = 0; 1468 u32 val; 1469 1470 if (pll->lock) 1471 spin_lock_irqsave(pll->lock, flags); 1472 1473 _clk_pll_disable(hw); 1474 1475 val = pll_readl_misc(pll); 1476 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1477 pll_writel_misc(val, pll); 1478 udelay(1); 1479 1480 if (pll->lock) 1481 spin_unlock_irqrestore(pll->lock, flags); 1482 } 1483 #endif 1484 1485 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1486 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1487 spinlock_t *lock) 1488 { 1489 struct tegra_clk_pll *pll; 1490 1491 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1492 if (!pll) 1493 return ERR_PTR(-ENOMEM); 1494 1495 pll->clk_base = clk_base; 1496 pll->pmc = pmc; 1497 1498 pll->params = pll_params; 1499 pll->lock = lock; 1500 1501 if (!pll_params->div_nmp) 1502 pll_params->div_nmp = &default_nmp; 1503 1504 return pll; 1505 } 1506 1507 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1508 const char *name, const char *parent_name, unsigned long flags, 1509 const struct clk_ops *ops) 1510 { 1511 struct clk_init_data init; 1512 1513 init.name = name; 1514 init.ops = ops; 1515 init.flags = flags; 1516 init.parent_names = (parent_name ? &parent_name : NULL); 1517 init.num_parents = (parent_name ? 1 : 0); 1518 1519 /* Default to _calc_rate if unspecified */ 1520 if (!pll->params->calc_rate) { 1521 if (pll->params->flags & TEGRA_PLLM) 1522 pll->params->calc_rate = _calc_dynamic_ramp_rate; 1523 else 1524 pll->params->calc_rate = _calc_rate; 1525 } 1526 1527 /* Data in .init is copied by clk_register(), so stack variable OK */ 1528 pll->hw.init = &init; 1529 1530 return clk_register(NULL, &pll->hw); 1531 } 1532 1533 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1534 void __iomem *clk_base, void __iomem *pmc, 1535 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1536 spinlock_t *lock) 1537 { 1538 struct tegra_clk_pll *pll; 1539 struct clk *clk; 1540 1541 pll_params->flags |= TEGRA_PLL_BYPASS; 1542 1543 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1544 if (IS_ERR(pll)) 1545 return ERR_CAST(pll); 1546 1547 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1548 &tegra_clk_pll_ops); 1549 if (IS_ERR(clk)) 1550 kfree(pll); 1551 1552 return clk; 1553 } 1554 1555 static struct div_nmp pll_e_nmp = { 1556 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1557 .divn_width = PLLE_BASE_DIVN_WIDTH, 1558 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1559 .divm_width = PLLE_BASE_DIVM_WIDTH, 1560 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1561 .divp_width = PLLE_BASE_DIVP_WIDTH, 1562 }; 1563 1564 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1565 void __iomem *clk_base, void __iomem *pmc, 1566 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1567 spinlock_t *lock) 1568 { 1569 struct tegra_clk_pll *pll; 1570 struct clk *clk; 1571 1572 pll_params->flags |= TEGRA_PLL_BYPASS; 1573 1574 if (!pll_params->div_nmp) 1575 pll_params->div_nmp = &pll_e_nmp; 1576 1577 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1578 if (IS_ERR(pll)) 1579 return ERR_CAST(pll); 1580 1581 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1582 &tegra_clk_plle_ops); 1583 if (IS_ERR(clk)) 1584 kfree(pll); 1585 1586 return clk; 1587 } 1588 1589 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1590 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1591 defined(CONFIG_ARCH_TEGRA_132_SOC) 1592 static const struct clk_ops tegra_clk_pllxc_ops = { 1593 .is_enabled = clk_pll_is_enabled, 1594 .enable = clk_pll_enable, 1595 .disable = clk_pll_disable, 1596 .recalc_rate = clk_pll_recalc_rate, 1597 .round_rate = clk_pll_ramp_round_rate, 1598 .set_rate = clk_pllxc_set_rate, 1599 }; 1600 1601 static const struct clk_ops tegra_clk_pllm_ops = { 1602 .is_enabled = clk_pll_is_enabled, 1603 .enable = clk_pll_enable, 1604 .disable = clk_pll_disable, 1605 .recalc_rate = clk_pll_recalc_rate, 1606 .round_rate = clk_pll_ramp_round_rate, 1607 .set_rate = clk_pllm_set_rate, 1608 }; 1609 1610 static const struct clk_ops tegra_clk_pllc_ops = { 1611 .is_enabled = clk_pll_is_enabled, 1612 .enable = clk_pllc_enable, 1613 .disable = clk_pllc_disable, 1614 .recalc_rate = clk_pll_recalc_rate, 1615 .round_rate = clk_pll_ramp_round_rate, 1616 .set_rate = clk_pllc_set_rate, 1617 }; 1618 1619 static const struct clk_ops tegra_clk_pllre_ops = { 1620 .is_enabled = clk_pll_is_enabled, 1621 .enable = clk_pll_enable, 1622 .disable = clk_pll_disable, 1623 .recalc_rate = clk_pllre_recalc_rate, 1624 .round_rate = clk_pllre_round_rate, 1625 .set_rate = clk_pllre_set_rate, 1626 }; 1627 1628 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1629 .is_enabled = clk_pll_is_enabled, 1630 .enable = clk_plle_tegra114_enable, 1631 .disable = clk_plle_tegra114_disable, 1632 .recalc_rate = clk_pll_recalc_rate, 1633 }; 1634 1635 1636 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1637 void __iomem *clk_base, void __iomem *pmc, 1638 unsigned long flags, 1639 struct tegra_clk_pll_params *pll_params, 1640 spinlock_t *lock) 1641 { 1642 struct tegra_clk_pll *pll; 1643 struct clk *clk, *parent; 1644 unsigned long parent_rate; 1645 int err; 1646 u32 val, val_iddq; 1647 1648 parent = __clk_lookup(parent_name); 1649 if (!parent) { 1650 WARN(1, "parent clk %s of %s must be registered first\n", 1651 parent_name, name); 1652 return ERR_PTR(-EINVAL); 1653 } 1654 1655 if (!pll_params->pdiv_tohw) 1656 return ERR_PTR(-EINVAL); 1657 1658 parent_rate = clk_get_rate(parent); 1659 1660 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1661 1662 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1663 if (err) 1664 return ERR_PTR(err); 1665 1666 val = readl_relaxed(clk_base + pll_params->base_reg); 1667 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1668 1669 if (val & PLL_BASE_ENABLE) 1670 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1671 else { 1672 val_iddq |= BIT(pll_params->iddq_bit_idx); 1673 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1674 } 1675 1676 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1677 if (IS_ERR(pll)) 1678 return ERR_CAST(pll); 1679 1680 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1681 &tegra_clk_pllxc_ops); 1682 if (IS_ERR(clk)) 1683 kfree(pll); 1684 1685 return clk; 1686 } 1687 1688 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1689 void __iomem *clk_base, void __iomem *pmc, 1690 unsigned long flags, 1691 struct tegra_clk_pll_params *pll_params, 1692 spinlock_t *lock, unsigned long parent_rate) 1693 { 1694 u32 val; 1695 struct tegra_clk_pll *pll; 1696 struct clk *clk; 1697 1698 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1699 1700 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1701 if (IS_ERR(pll)) 1702 return ERR_CAST(pll); 1703 1704 /* program minimum rate by default */ 1705 1706 val = pll_readl_base(pll); 1707 if (val & PLL_BASE_ENABLE) 1708 WARN_ON(val & pll_params->iddq_bit_idx); 1709 else { 1710 int m; 1711 1712 m = _pll_fixed_mdiv(pll_params, parent_rate); 1713 val = m << divm_shift(pll); 1714 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 1715 pll_writel_base(val, pll); 1716 } 1717 1718 /* disable lock override */ 1719 1720 val = pll_readl_misc(pll); 1721 val &= ~BIT(29); 1722 pll_writel_misc(val, pll); 1723 1724 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1725 &tegra_clk_pllre_ops); 1726 if (IS_ERR(clk)) 1727 kfree(pll); 1728 1729 return clk; 1730 } 1731 1732 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1733 void __iomem *clk_base, void __iomem *pmc, 1734 unsigned long flags, 1735 struct tegra_clk_pll_params *pll_params, 1736 spinlock_t *lock) 1737 { 1738 struct tegra_clk_pll *pll; 1739 struct clk *clk, *parent; 1740 unsigned long parent_rate; 1741 1742 if (!pll_params->pdiv_tohw) 1743 return ERR_PTR(-EINVAL); 1744 1745 parent = __clk_lookup(parent_name); 1746 if (!parent) { 1747 WARN(1, "parent clk %s of %s must be registered first\n", 1748 parent_name, name); 1749 return ERR_PTR(-EINVAL); 1750 } 1751 1752 parent_rate = clk_get_rate(parent); 1753 1754 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1755 1756 pll_params->flags |= TEGRA_PLL_BYPASS; 1757 pll_params->flags |= TEGRA_PLLM; 1758 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1759 if (IS_ERR(pll)) 1760 return ERR_CAST(pll); 1761 1762 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1763 &tegra_clk_pllm_ops); 1764 if (IS_ERR(clk)) 1765 kfree(pll); 1766 1767 return clk; 1768 } 1769 1770 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1771 void __iomem *clk_base, void __iomem *pmc, 1772 unsigned long flags, 1773 struct tegra_clk_pll_params *pll_params, 1774 spinlock_t *lock) 1775 { 1776 struct clk *parent, *clk; 1777 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1778 struct tegra_clk_pll *pll; 1779 struct tegra_clk_pll_freq_table cfg; 1780 unsigned long parent_rate; 1781 1782 if (!p_tohw) 1783 return ERR_PTR(-EINVAL); 1784 1785 parent = __clk_lookup(parent_name); 1786 if (!parent) { 1787 WARN(1, "parent clk %s of %s must be registered first\n", 1788 parent_name, name); 1789 return ERR_PTR(-EINVAL); 1790 } 1791 1792 parent_rate = clk_get_rate(parent); 1793 1794 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1795 1796 pll_params->flags |= TEGRA_PLL_BYPASS; 1797 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1798 if (IS_ERR(pll)) 1799 return ERR_CAST(pll); 1800 1801 /* 1802 * Most of PLLC register fields are shadowed, and can not be read 1803 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1804 * Initialize PLL to default state: disabled, reset; shadow registers 1805 * loaded with default parameters; dividers are preset for half of 1806 * minimum VCO rate (the latter assured that shadowed divider settings 1807 * are within supported range). 1808 */ 1809 1810 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1811 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1812 1813 while (p_tohw->pdiv) { 1814 if (p_tohw->pdiv == 2) { 1815 cfg.p = p_tohw->hw_val; 1816 break; 1817 } 1818 p_tohw++; 1819 } 1820 1821 if (!p_tohw->pdiv) { 1822 WARN_ON(1); 1823 return ERR_PTR(-EINVAL); 1824 } 1825 1826 pll_writel_base(0, pll); 1827 _update_pll_mnp(pll, &cfg); 1828 1829 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1830 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1831 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1832 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1833 1834 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1835 1836 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1837 &tegra_clk_pllc_ops); 1838 if (IS_ERR(clk)) 1839 kfree(pll); 1840 1841 return clk; 1842 } 1843 1844 struct clk *tegra_clk_register_plle_tegra114(const char *name, 1845 const char *parent_name, 1846 void __iomem *clk_base, unsigned long flags, 1847 struct tegra_clk_pll_params *pll_params, 1848 spinlock_t *lock) 1849 { 1850 struct tegra_clk_pll *pll; 1851 struct clk *clk; 1852 u32 val, val_aux; 1853 1854 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1855 if (IS_ERR(pll)) 1856 return ERR_CAST(pll); 1857 1858 /* ensure parent is set to pll_re_vco */ 1859 1860 val = pll_readl_base(pll); 1861 val_aux = pll_readl(pll_params->aux_reg, pll); 1862 1863 if (val & PLL_BASE_ENABLE) { 1864 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1865 (val_aux & PLLE_AUX_PLLP_SEL)) 1866 WARN(1, "pll_e enabled with unsupported parent %s\n", 1867 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1868 "pll_re_vco"); 1869 } else { 1870 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1871 pll_writel(val_aux, pll_params->aux_reg, pll); 1872 } 1873 1874 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1875 &tegra_clk_plle_tegra114_ops); 1876 if (IS_ERR(clk)) 1877 kfree(pll); 1878 1879 return clk; 1880 } 1881 #endif 1882 1883 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 1884 static const struct clk_ops tegra_clk_pllss_ops = { 1885 .is_enabled = clk_pll_is_enabled, 1886 .enable = clk_pll_enable, 1887 .disable = clk_pll_disable, 1888 .recalc_rate = clk_pll_recalc_rate, 1889 .round_rate = clk_pll_ramp_round_rate, 1890 .set_rate = clk_pllxc_set_rate, 1891 }; 1892 1893 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 1894 void __iomem *clk_base, unsigned long flags, 1895 struct tegra_clk_pll_params *pll_params, 1896 spinlock_t *lock) 1897 { 1898 struct tegra_clk_pll *pll; 1899 struct clk *clk, *parent; 1900 struct tegra_clk_pll_freq_table cfg; 1901 unsigned long parent_rate; 1902 u32 val; 1903 int i; 1904 1905 if (!pll_params->div_nmp) 1906 return ERR_PTR(-EINVAL); 1907 1908 parent = __clk_lookup(parent_name); 1909 if (!parent) { 1910 WARN(1, "parent clk %s of %s must be registered first\n", 1911 parent_name, name); 1912 return ERR_PTR(-EINVAL); 1913 } 1914 1915 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1916 if (IS_ERR(pll)) 1917 return ERR_CAST(pll); 1918 1919 val = pll_readl_base(pll); 1920 val &= ~PLLSS_REF_SRC_SEL_MASK; 1921 pll_writel_base(val, pll); 1922 1923 parent_rate = clk_get_rate(parent); 1924 1925 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1926 1927 /* initialize PLL to minimum rate */ 1928 1929 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1930 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1931 1932 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 1933 ; 1934 if (!i) { 1935 kfree(pll); 1936 return ERR_PTR(-EINVAL); 1937 } 1938 1939 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 1940 1941 _update_pll_mnp(pll, &cfg); 1942 1943 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 1944 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 1945 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 1946 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1947 1948 val = pll_readl_base(pll); 1949 if (val & PLL_BASE_ENABLE) { 1950 if (val & BIT(pll_params->iddq_bit_idx)) { 1951 WARN(1, "%s is on but IDDQ set\n", name); 1952 kfree(pll); 1953 return ERR_PTR(-EINVAL); 1954 } 1955 } else 1956 val |= BIT(pll_params->iddq_bit_idx); 1957 1958 val &= ~PLLSS_LOCK_OVERRIDE; 1959 pll_writel_base(val, pll); 1960 1961 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1962 &tegra_clk_pllss_ops); 1963 1964 if (IS_ERR(clk)) 1965 kfree(pll); 1966 1967 return clk; 1968 } 1969 #endif 1970