1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 #define PLLE_BASE_ENABLE BIT(31) 69 70 #define PLLE_MISC_SETUP_BASE_SHIFT 16 71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 72 #define PLLE_MISC_LOCK_ENABLE BIT(9) 73 #define PLLE_MISC_READY BIT(15) 74 #define PLLE_MISC_SETUP_EX_SHIFT 2 75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 77 PLLE_MISC_SETUP_EX_MASK) 78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 79 80 #define PLLE_SS_CTRL 0x68 81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 83 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 84 #define PLLE_SS_CNTL_CENTER BIT(14) 85 #define PLLE_SS_CNTL_INVERT BIT(15) 86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 87 PLLE_SS_CNTL_SSC_BYP) 88 #define PLLE_SS_MAX_MASK 0x1ff 89 #define PLLE_SS_MAX_VAL 0x25 90 #define PLLE_SS_INC_MASK (0xff << 16) 91 #define PLLE_SS_INC_VAL (0x1 << 16) 92 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 93 #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 94 #define PLLE_SS_COEFFICIENTS_MASK \ 95 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 96 #define PLLE_SS_COEFFICIENTS_VAL \ 97 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 98 99 #define PLLE_AUX_PLLP_SEL BIT(2) 100 #define PLLE_AUX_USE_LOCKDET BIT(3) 101 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 102 #define PLLE_AUX_SS_SWCTL BIT(6) 103 #define PLLE_AUX_SEQ_ENABLE BIT(24) 104 #define PLLE_AUX_SEQ_START_STATE BIT(25) 105 #define PLLE_AUX_PLLRE_SEL BIT(28) 106 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31) 107 108 #define XUSBIO_PLL_CFG0 0x51c 109 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 110 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 111 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 112 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 113 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 114 115 #define SATA_PLL_CFG0 0x490 116 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 117 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 118 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 119 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 120 121 #define PLLE_MISC_PLLE_PTS BIT(8) 122 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 123 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 124 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 125 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 126 #define PLLE_MISC_VREG_CTRL_SHIFT 2 127 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 128 129 #define PLLCX_MISC_STROBE BIT(31) 130 #define PLLCX_MISC_RESET BIT(30) 131 #define PLLCX_MISC_SDM_DIV_SHIFT 28 132 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 133 #define PLLCX_MISC_FILT_DIV_SHIFT 26 134 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 135 #define PLLCX_MISC_ALPHA_SHIFT 18 136 #define PLLCX_MISC_DIV_LOW_RANGE \ 137 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 138 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 139 #define PLLCX_MISC_DIV_HIGH_RANGE \ 140 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 141 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 142 #define PLLCX_MISC_COEF_LOW_RANGE \ 143 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 144 #define PLLCX_MISC_KA_SHIFT 2 145 #define PLLCX_MISC_KB_SHIFT 9 146 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 147 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 148 PLLCX_MISC_DIV_LOW_RANGE | \ 149 PLLCX_MISC_RESET) 150 #define PLLCX_MISC1_DEFAULT 0x000d2308 151 #define PLLCX_MISC2_DEFAULT 0x30211200 152 #define PLLCX_MISC3_DEFAULT 0x200 153 154 #define PMC_SATA_PWRGT 0x1ac 155 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 156 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 157 158 #define PLLSS_MISC_KCP 0 159 #define PLLSS_MISC_KVCO 0 160 #define PLLSS_MISC_SETUP 0 161 #define PLLSS_EN_SDM 0 162 #define PLLSS_EN_SSC 0 163 #define PLLSS_EN_DITHER2 0 164 #define PLLSS_EN_DITHER 1 165 #define PLLSS_SDM_RESET 0 166 #define PLLSS_CLAMP 0 167 #define PLLSS_SDM_SSC_MAX 0 168 #define PLLSS_SDM_SSC_MIN 0 169 #define PLLSS_SDM_SSC_STEP 0 170 #define PLLSS_SDM_DIN 0 171 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 172 (PLLSS_MISC_KVCO << 24) | \ 173 PLLSS_MISC_SETUP) 174 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 175 (PLLSS_EN_SSC << 30) | \ 176 (PLLSS_EN_DITHER2 << 29) | \ 177 (PLLSS_EN_DITHER << 28) | \ 178 (PLLSS_SDM_RESET) << 27 | \ 179 (PLLSS_CLAMP << 22)) 180 #define PLLSS_CTRL1_DEFAULT \ 181 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 182 #define PLLSS_CTRL2_DEFAULT \ 183 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 184 #define PLLSS_LOCK_OVERRIDE BIT(24) 185 #define PLLSS_REF_SRC_SEL_SHIFT 25 186 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 187 188 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 189 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 190 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 191 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 192 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p) 193 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p) 194 195 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 196 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 197 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 198 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 199 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) 200 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) 201 202 #define mask(w) ((1 << (w)) - 1) 203 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 204 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 205 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 206 mask(p->params->div_nmp->divp_width)) 207 #define sdm_din_mask(p) p->params->sdm_din_mask 208 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask 209 210 #define divm_shift(p) (p)->params->div_nmp->divm_shift 211 #define divn_shift(p) (p)->params->div_nmp->divn_shift 212 #define divp_shift(p) (p)->params->div_nmp->divp_shift 213 214 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 215 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 216 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 217 218 #define divm_max(p) (divm_mask(p)) 219 #define divn_max(p) (divn_mask(p)) 220 #define divp_max(p) (1 << (divp_mask(p))) 221 222 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 223 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 224 225 static struct div_nmp default_nmp = { 226 .divn_shift = PLL_BASE_DIVN_SHIFT, 227 .divn_width = PLL_BASE_DIVN_WIDTH, 228 .divm_shift = PLL_BASE_DIVM_SHIFT, 229 .divm_width = PLL_BASE_DIVM_WIDTH, 230 .divp_shift = PLL_BASE_DIVP_SHIFT, 231 .divp_width = PLL_BASE_DIVP_WIDTH, 232 }; 233 234 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 235 { 236 u32 val; 237 238 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 239 return; 240 241 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 242 return; 243 244 val = pll_readl_misc(pll); 245 val |= BIT(pll->params->lock_enable_bit_idx); 246 pll_writel_misc(val, pll); 247 } 248 249 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 250 { 251 int i; 252 u32 val, lock_mask; 253 void __iomem *lock_addr; 254 255 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 256 udelay(pll->params->lock_delay); 257 return 0; 258 } 259 260 lock_addr = pll->clk_base; 261 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 262 lock_addr += pll->params->misc_reg; 263 else 264 lock_addr += pll->params->base_reg; 265 266 lock_mask = pll->params->lock_mask; 267 268 for (i = 0; i < pll->params->lock_delay; i++) { 269 val = readl_relaxed(lock_addr); 270 if ((val & lock_mask) == lock_mask) { 271 udelay(PLL_POST_LOCK_DELAY); 272 return 0; 273 } 274 udelay(2); /* timeout = 2 * lock time */ 275 } 276 277 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 278 clk_hw_get_name(&pll->hw)); 279 280 return -1; 281 } 282 283 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 284 { 285 return clk_pll_wait_for_lock(pll); 286 } 287 288 static int clk_pll_is_enabled(struct clk_hw *hw) 289 { 290 struct tegra_clk_pll *pll = to_clk_pll(hw); 291 u32 val; 292 293 if (pll->params->flags & TEGRA_PLLM) { 294 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 295 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 296 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 297 } 298 299 val = pll_readl_base(pll); 300 301 return val & PLL_BASE_ENABLE ? 1 : 0; 302 } 303 304 static void _clk_pll_enable(struct clk_hw *hw) 305 { 306 struct tegra_clk_pll *pll = to_clk_pll(hw); 307 u32 val; 308 309 if (pll->params->iddq_reg) { 310 val = pll_readl(pll->params->iddq_reg, pll); 311 val &= ~BIT(pll->params->iddq_bit_idx); 312 pll_writel(val, pll->params->iddq_reg, pll); 313 udelay(2); 314 } 315 316 if (pll->params->reset_reg) { 317 val = pll_readl(pll->params->reset_reg, pll); 318 val &= ~BIT(pll->params->reset_bit_idx); 319 pll_writel(val, pll->params->reset_reg, pll); 320 } 321 322 clk_pll_enable_lock(pll); 323 324 val = pll_readl_base(pll); 325 if (pll->params->flags & TEGRA_PLL_BYPASS) 326 val &= ~PLL_BASE_BYPASS; 327 val |= PLL_BASE_ENABLE; 328 pll_writel_base(val, pll); 329 330 if (pll->params->flags & TEGRA_PLLM) { 331 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 332 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 333 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 334 } 335 } 336 337 static void _clk_pll_disable(struct clk_hw *hw) 338 { 339 struct tegra_clk_pll *pll = to_clk_pll(hw); 340 u32 val; 341 342 val = pll_readl_base(pll); 343 if (pll->params->flags & TEGRA_PLL_BYPASS) 344 val &= ~PLL_BASE_BYPASS; 345 val &= ~PLL_BASE_ENABLE; 346 pll_writel_base(val, pll); 347 348 if (pll->params->flags & TEGRA_PLLM) { 349 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 350 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 351 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 352 } 353 354 if (pll->params->reset_reg) { 355 val = pll_readl(pll->params->reset_reg, pll); 356 val |= BIT(pll->params->reset_bit_idx); 357 pll_writel(val, pll->params->reset_reg, pll); 358 } 359 360 if (pll->params->iddq_reg) { 361 val = pll_readl(pll->params->iddq_reg, pll); 362 val |= BIT(pll->params->iddq_bit_idx); 363 pll_writel(val, pll->params->iddq_reg, pll); 364 udelay(2); 365 } 366 } 367 368 static int clk_pll_enable(struct clk_hw *hw) 369 { 370 struct tegra_clk_pll *pll = to_clk_pll(hw); 371 unsigned long flags = 0; 372 int ret; 373 374 if (pll->lock) 375 spin_lock_irqsave(pll->lock, flags); 376 377 _clk_pll_enable(hw); 378 379 ret = clk_pll_wait_for_lock(pll); 380 381 if (pll->lock) 382 spin_unlock_irqrestore(pll->lock, flags); 383 384 return ret; 385 } 386 387 static void clk_pll_disable(struct clk_hw *hw) 388 { 389 struct tegra_clk_pll *pll = to_clk_pll(hw); 390 unsigned long flags = 0; 391 392 if (pll->lock) 393 spin_lock_irqsave(pll->lock, flags); 394 395 _clk_pll_disable(hw); 396 397 if (pll->lock) 398 spin_unlock_irqrestore(pll->lock, flags); 399 } 400 401 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 402 { 403 struct tegra_clk_pll *pll = to_clk_pll(hw); 404 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 405 406 if (p_tohw) { 407 while (p_tohw->pdiv) { 408 if (p_div <= p_tohw->pdiv) 409 return p_tohw->hw_val; 410 p_tohw++; 411 } 412 return -EINVAL; 413 } 414 return -EINVAL; 415 } 416 417 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div) 418 { 419 return _p_div_to_hw(&pll->hw, p_div); 420 } 421 422 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 423 { 424 struct tegra_clk_pll *pll = to_clk_pll(hw); 425 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 426 427 if (p_tohw) { 428 while (p_tohw->pdiv) { 429 if (p_div_hw == p_tohw->hw_val) 430 return p_tohw->pdiv; 431 p_tohw++; 432 } 433 return -EINVAL; 434 } 435 436 return 1 << p_div_hw; 437 } 438 439 static int _get_table_rate(struct clk_hw *hw, 440 struct tegra_clk_pll_freq_table *cfg, 441 unsigned long rate, unsigned long parent_rate) 442 { 443 struct tegra_clk_pll *pll = to_clk_pll(hw); 444 struct tegra_clk_pll_freq_table *sel; 445 int p; 446 447 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 448 if (sel->input_rate == parent_rate && 449 sel->output_rate == rate) 450 break; 451 452 if (sel->input_rate == 0) 453 return -EINVAL; 454 455 if (pll->params->pdiv_tohw) { 456 p = _p_div_to_hw(hw, sel->p); 457 if (p < 0) 458 return p; 459 } else { 460 p = ilog2(sel->p); 461 } 462 463 cfg->input_rate = sel->input_rate; 464 cfg->output_rate = sel->output_rate; 465 cfg->m = sel->m; 466 cfg->n = sel->n; 467 cfg->p = p; 468 cfg->cpcon = sel->cpcon; 469 cfg->sdm_data = sel->sdm_data; 470 471 return 0; 472 } 473 474 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 475 unsigned long rate, unsigned long parent_rate) 476 { 477 struct tegra_clk_pll *pll = to_clk_pll(hw); 478 unsigned long cfreq; 479 u32 p_div = 0; 480 int ret; 481 482 switch (parent_rate) { 483 case 12000000: 484 case 26000000: 485 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 486 break; 487 case 13000000: 488 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 489 break; 490 case 16800000: 491 case 19200000: 492 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 493 break; 494 case 9600000: 495 case 28800000: 496 /* 497 * PLL_P_OUT1 rate is not listed in PLLA table 498 */ 499 cfreq = parent_rate / (parent_rate / 1000000); 500 break; 501 default: 502 pr_err("%s Unexpected reference rate %lu\n", 503 __func__, parent_rate); 504 BUG(); 505 } 506 507 /* Raise VCO to guarantee 0.5% accuracy */ 508 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 509 cfg->output_rate <<= 1) 510 p_div++; 511 512 cfg->m = parent_rate / cfreq; 513 cfg->n = cfg->output_rate / cfreq; 514 cfg->cpcon = OUT_OF_TABLE_CPCON; 515 516 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 517 (1 << p_div) > divp_max(pll) 518 || cfg->output_rate > pll->params->vco_max) { 519 return -EINVAL; 520 } 521 522 cfg->output_rate >>= p_div; 523 524 if (pll->params->pdiv_tohw) { 525 ret = _p_div_to_hw(hw, 1 << p_div); 526 if (ret < 0) 527 return ret; 528 else 529 cfg->p = ret; 530 } else 531 cfg->p = p_div; 532 533 return 0; 534 } 535 536 /* 537 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number 538 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as 539 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used 540 * to indicate that SDM is disabled. 541 * 542 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 543 */ 544 static void clk_pll_set_sdm_data(struct clk_hw *hw, 545 struct tegra_clk_pll_freq_table *cfg) 546 { 547 struct tegra_clk_pll *pll = to_clk_pll(hw); 548 u32 val; 549 bool enabled; 550 551 if (!pll->params->sdm_din_reg) 552 return; 553 554 if (cfg->sdm_data) { 555 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); 556 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); 557 pll_writel_sdm_din(val, pll); 558 } 559 560 val = pll_readl_sdm_ctrl(pll); 561 enabled = (val & sdm_en_mask(pll)); 562 563 if (cfg->sdm_data == 0 && enabled) 564 val &= ~pll->params->sdm_ctrl_en_mask; 565 566 if (cfg->sdm_data != 0 && !enabled) 567 val |= pll->params->sdm_ctrl_en_mask; 568 569 pll_writel_sdm_ctrl(val, pll); 570 } 571 572 static void _update_pll_mnp(struct tegra_clk_pll *pll, 573 struct tegra_clk_pll_freq_table *cfg) 574 { 575 u32 val; 576 struct tegra_clk_pll_params *params = pll->params; 577 struct div_nmp *div_nmp = params->div_nmp; 578 579 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 580 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 581 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 582 val = pll_override_readl(params->pmc_divp_reg, pll); 583 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 584 val |= cfg->p << div_nmp->override_divp_shift; 585 pll_override_writel(val, params->pmc_divp_reg, pll); 586 587 val = pll_override_readl(params->pmc_divnm_reg, pll); 588 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | 589 ~(divn_mask(pll) << div_nmp->override_divn_shift); 590 val |= (cfg->m << div_nmp->override_divm_shift) | 591 (cfg->n << div_nmp->override_divn_shift); 592 pll_override_writel(val, params->pmc_divnm_reg, pll); 593 } else { 594 val = pll_readl_base(pll); 595 596 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 597 divp_mask_shifted(pll)); 598 599 val |= (cfg->m << divm_shift(pll)) | 600 (cfg->n << divn_shift(pll)) | 601 (cfg->p << divp_shift(pll)); 602 603 pll_writel_base(val, pll); 604 605 clk_pll_set_sdm_data(&pll->hw, cfg); 606 } 607 } 608 609 static void _get_pll_mnp(struct tegra_clk_pll *pll, 610 struct tegra_clk_pll_freq_table *cfg) 611 { 612 u32 val; 613 struct tegra_clk_pll_params *params = pll->params; 614 struct div_nmp *div_nmp = params->div_nmp; 615 616 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 617 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 618 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 619 val = pll_override_readl(params->pmc_divp_reg, pll); 620 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 621 622 val = pll_override_readl(params->pmc_divnm_reg, pll); 623 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 624 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 625 } else { 626 val = pll_readl_base(pll); 627 628 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 629 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 630 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 631 632 if (pll->params->sdm_din_reg) { 633 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { 634 val = pll_readl_sdm_din(pll); 635 val &= sdm_din_mask(pll); 636 cfg->sdm_data = sdin_din_to_data(val); 637 } 638 } 639 } 640 } 641 642 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 643 struct tegra_clk_pll_freq_table *cfg, 644 unsigned long rate) 645 { 646 u32 val; 647 648 val = pll_readl_misc(pll); 649 650 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 651 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 652 653 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 654 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 655 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 656 val |= 1 << PLL_MISC_LFCON_SHIFT; 657 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 658 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 659 if (rate >= (pll->params->vco_max >> 1)) 660 val |= 1 << PLL_MISC_DCCON_SHIFT; 661 } 662 663 pll_writel_misc(val, pll); 664 } 665 666 static void pll_clk_start_ss(struct tegra_clk_pll *pll) 667 { 668 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { 669 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); 670 671 val |= pll->params->ssc_ctrl_en_mask; 672 pll_writel(val, pll->params->ssc_ctrl_reg, pll); 673 } 674 } 675 676 static void pll_clk_stop_ss(struct tegra_clk_pll *pll) 677 { 678 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { 679 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); 680 681 val &= ~pll->params->ssc_ctrl_en_mask; 682 pll_writel(val, pll->params->ssc_ctrl_reg, pll); 683 } 684 } 685 686 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 687 unsigned long rate) 688 { 689 struct tegra_clk_pll *pll = to_clk_pll(hw); 690 struct tegra_clk_pll_freq_table old_cfg; 691 int state, ret = 0; 692 693 state = clk_pll_is_enabled(hw); 694 695 _get_pll_mnp(pll, &old_cfg); 696 697 if (state && pll->params->defaults_set && pll->params->dyn_ramp && 698 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { 699 ret = pll->params->dyn_ramp(pll, cfg); 700 if (!ret) 701 return 0; 702 } 703 704 if (state) { 705 pll_clk_stop_ss(pll); 706 _clk_pll_disable(hw); 707 } 708 709 if (!pll->params->defaults_set && pll->params->set_defaults) 710 pll->params->set_defaults(pll); 711 712 _update_pll_mnp(pll, cfg); 713 714 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 715 _update_pll_cpcon(pll, cfg, rate); 716 717 if (state) { 718 _clk_pll_enable(hw); 719 ret = clk_pll_wait_for_lock(pll); 720 pll_clk_start_ss(pll); 721 } 722 723 return ret; 724 } 725 726 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 727 unsigned long parent_rate) 728 { 729 struct tegra_clk_pll *pll = to_clk_pll(hw); 730 struct tegra_clk_pll_freq_table cfg, old_cfg; 731 unsigned long flags = 0; 732 int ret = 0; 733 734 if (pll->params->flags & TEGRA_PLL_FIXED) { 735 if (rate != pll->params->fixed_rate) { 736 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 737 __func__, clk_hw_get_name(hw), 738 pll->params->fixed_rate, rate); 739 return -EINVAL; 740 } 741 return 0; 742 } 743 744 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 745 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { 746 pr_err("%s: Failed to set %s rate %lu\n", __func__, 747 clk_hw_get_name(hw), rate); 748 WARN_ON(1); 749 return -EINVAL; 750 } 751 if (pll->lock) 752 spin_lock_irqsave(pll->lock, flags); 753 754 _get_pll_mnp(pll, &old_cfg); 755 756 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || 757 old_cfg.sdm_data != cfg.sdm_data) 758 ret = _program_pll(hw, &cfg, rate); 759 760 if (pll->lock) 761 spin_unlock_irqrestore(pll->lock, flags); 762 763 return ret; 764 } 765 766 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 767 unsigned long *prate) 768 { 769 struct tegra_clk_pll *pll = to_clk_pll(hw); 770 struct tegra_clk_pll_freq_table cfg; 771 772 if (pll->params->flags & TEGRA_PLL_FIXED) { 773 /* PLLM/MB are used for memory; we do not change rate */ 774 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) 775 return clk_hw_get_rate(hw); 776 return pll->params->fixed_rate; 777 } 778 779 if (_get_table_rate(hw, &cfg, rate, *prate) && 780 pll->params->calc_rate(hw, &cfg, rate, *prate)) 781 return -EINVAL; 782 783 return cfg.output_rate; 784 } 785 786 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 787 unsigned long parent_rate) 788 { 789 struct tegra_clk_pll *pll = to_clk_pll(hw); 790 struct tegra_clk_pll_freq_table cfg; 791 u32 val; 792 u64 rate = parent_rate; 793 int pdiv; 794 795 val = pll_readl_base(pll); 796 797 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 798 return parent_rate; 799 800 if ((pll->params->flags & TEGRA_PLL_FIXED) && 801 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 802 !(val & PLL_BASE_OVERRIDE)) { 803 struct tegra_clk_pll_freq_table sel; 804 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 805 parent_rate)) { 806 pr_err("Clock %s has unknown fixed frequency\n", 807 clk_hw_get_name(hw)); 808 BUG(); 809 } 810 return pll->params->fixed_rate; 811 } 812 813 _get_pll_mnp(pll, &cfg); 814 815 pdiv = _hw_to_p_div(hw, cfg.p); 816 if (pdiv < 0) { 817 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 818 __clk_get_name(hw->clk), cfg.p); 819 pdiv = 1; 820 } 821 822 if (pll->params->set_gain) 823 pll->params->set_gain(&cfg); 824 825 cfg.m *= pdiv; 826 827 rate *= cfg.n; 828 do_div(rate, cfg.m); 829 830 return rate; 831 } 832 833 static int clk_plle_training(struct tegra_clk_pll *pll) 834 { 835 u32 val; 836 unsigned long timeout; 837 838 if (!pll->pmc) 839 return -ENOSYS; 840 841 /* 842 * PLLE is already disabled, and setup cleared; 843 * create falling edge on PLLE IDDQ input. 844 */ 845 val = readl(pll->pmc + PMC_SATA_PWRGT); 846 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 847 writel(val, pll->pmc + PMC_SATA_PWRGT); 848 849 val = readl(pll->pmc + PMC_SATA_PWRGT); 850 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 851 writel(val, pll->pmc + PMC_SATA_PWRGT); 852 853 val = readl(pll->pmc + PMC_SATA_PWRGT); 854 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 855 writel(val, pll->pmc + PMC_SATA_PWRGT); 856 857 val = pll_readl_misc(pll); 858 859 timeout = jiffies + msecs_to_jiffies(100); 860 while (1) { 861 val = pll_readl_misc(pll); 862 if (val & PLLE_MISC_READY) 863 break; 864 if (time_after(jiffies, timeout)) { 865 pr_err("%s: timeout waiting for PLLE\n", __func__); 866 return -EBUSY; 867 } 868 udelay(300); 869 } 870 871 return 0; 872 } 873 874 static int clk_plle_enable(struct clk_hw *hw) 875 { 876 struct tegra_clk_pll *pll = to_clk_pll(hw); 877 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 878 struct tegra_clk_pll_freq_table sel; 879 u32 val; 880 int err; 881 882 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 883 return -EINVAL; 884 885 clk_pll_disable(hw); 886 887 val = pll_readl_misc(pll); 888 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 889 pll_writel_misc(val, pll); 890 891 val = pll_readl_misc(pll); 892 if (!(val & PLLE_MISC_READY)) { 893 err = clk_plle_training(pll); 894 if (err) 895 return err; 896 } 897 898 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 899 /* configure dividers */ 900 val = pll_readl_base(pll); 901 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 902 divm_mask_shifted(pll)); 903 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 904 val |= sel.m << divm_shift(pll); 905 val |= sel.n << divn_shift(pll); 906 val |= sel.p << divp_shift(pll); 907 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 908 pll_writel_base(val, pll); 909 } 910 911 val = pll_readl_misc(pll); 912 val |= PLLE_MISC_SETUP_VALUE; 913 val |= PLLE_MISC_LOCK_ENABLE; 914 pll_writel_misc(val, pll); 915 916 val = readl(pll->clk_base + PLLE_SS_CTRL); 917 val &= ~PLLE_SS_COEFFICIENTS_MASK; 918 val |= PLLE_SS_DISABLE; 919 writel(val, pll->clk_base + PLLE_SS_CTRL); 920 921 val = pll_readl_base(pll); 922 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 923 pll_writel_base(val, pll); 924 925 clk_pll_wait_for_lock(pll); 926 927 return 0; 928 } 929 930 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 931 unsigned long parent_rate) 932 { 933 struct tegra_clk_pll *pll = to_clk_pll(hw); 934 u32 val = pll_readl_base(pll); 935 u32 divn = 0, divm = 0, divp = 0; 936 u64 rate = parent_rate; 937 938 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 939 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 940 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 941 divm *= divp; 942 943 rate *= divn; 944 do_div(rate, divm); 945 return rate; 946 } 947 948 const struct clk_ops tegra_clk_pll_ops = { 949 .is_enabled = clk_pll_is_enabled, 950 .enable = clk_pll_enable, 951 .disable = clk_pll_disable, 952 .recalc_rate = clk_pll_recalc_rate, 953 .round_rate = clk_pll_round_rate, 954 .set_rate = clk_pll_set_rate, 955 }; 956 957 const struct clk_ops tegra_clk_plle_ops = { 958 .recalc_rate = clk_plle_recalc_rate, 959 .is_enabled = clk_pll_is_enabled, 960 .disable = clk_pll_disable, 961 .enable = clk_plle_enable, 962 }; 963 964 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 965 unsigned long parent_rate) 966 { 967 u16 mdiv = parent_rate / pll_params->cf_min; 968 969 if (pll_params->flags & TEGRA_MDIV_NEW) 970 return (!pll_params->mdiv_default ? mdiv : 971 min(mdiv, pll_params->mdiv_default)); 972 973 if (pll_params->mdiv_default) 974 return pll_params->mdiv_default; 975 976 if (parent_rate > pll_params->cf_max) 977 return 2; 978 else 979 return 1; 980 } 981 982 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 983 struct tegra_clk_pll_freq_table *cfg, 984 unsigned long rate, unsigned long parent_rate) 985 { 986 struct tegra_clk_pll *pll = to_clk_pll(hw); 987 unsigned int p; 988 int p_div; 989 990 if (!rate) 991 return -EINVAL; 992 993 p = DIV_ROUND_UP(pll->params->vco_min, rate); 994 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 995 cfg->output_rate = rate * p; 996 cfg->n = cfg->output_rate * cfg->m / parent_rate; 997 cfg->input_rate = parent_rate; 998 999 p_div = _p_div_to_hw(hw, p); 1000 if (p_div < 0) 1001 return p_div; 1002 1003 cfg->p = p_div; 1004 1005 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 1006 return -EINVAL; 1007 1008 return 0; 1009 } 1010 1011 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1012 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1013 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1014 defined(CONFIG_ARCH_TEGRA_210_SOC) 1015 1016 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) 1017 { 1018 struct tegra_clk_pll *pll = to_clk_pll(hw); 1019 1020 return (u16)_pll_fixed_mdiv(pll->params, input_rate); 1021 } 1022 1023 static unsigned long _clip_vco_min(unsigned long vco_min, 1024 unsigned long parent_rate) 1025 { 1026 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 1027 } 1028 1029 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1030 void __iomem *clk_base, 1031 unsigned long parent_rate) 1032 { 1033 u32 val; 1034 u32 step_a, step_b; 1035 1036 switch (parent_rate) { 1037 case 12000000: 1038 case 13000000: 1039 case 26000000: 1040 step_a = 0x2B; 1041 step_b = 0x0B; 1042 break; 1043 case 16800000: 1044 step_a = 0x1A; 1045 step_b = 0x09; 1046 break; 1047 case 19200000: 1048 step_a = 0x12; 1049 step_b = 0x08; 1050 break; 1051 default: 1052 pr_err("%s: Unexpected reference rate %lu\n", 1053 __func__, parent_rate); 1054 WARN_ON(1); 1055 return -EINVAL; 1056 } 1057 1058 val = step_a << pll_params->stepa_shift; 1059 val |= step_b << pll_params->stepb_shift; 1060 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1061 1062 return 0; 1063 } 1064 1065 static int _pll_ramp_calc_pll(struct clk_hw *hw, 1066 struct tegra_clk_pll_freq_table *cfg, 1067 unsigned long rate, unsigned long parent_rate) 1068 { 1069 struct tegra_clk_pll *pll = to_clk_pll(hw); 1070 int err = 0; 1071 1072 err = _get_table_rate(hw, cfg, rate, parent_rate); 1073 if (err < 0) 1074 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 1075 else { 1076 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 1077 WARN_ON(1); 1078 err = -EINVAL; 1079 goto out; 1080 } 1081 } 1082 1083 if (cfg->p > pll->params->max_p) 1084 err = -EINVAL; 1085 1086 out: 1087 return err; 1088 } 1089 1090 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 1091 unsigned long parent_rate) 1092 { 1093 struct tegra_clk_pll *pll = to_clk_pll(hw); 1094 struct tegra_clk_pll_freq_table cfg, old_cfg; 1095 unsigned long flags = 0; 1096 int ret; 1097 1098 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1099 if (ret < 0) 1100 return ret; 1101 1102 if (pll->lock) 1103 spin_lock_irqsave(pll->lock, flags); 1104 1105 _get_pll_mnp(pll, &old_cfg); 1106 1107 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1108 ret = _program_pll(hw, &cfg, rate); 1109 1110 if (pll->lock) 1111 spin_unlock_irqrestore(pll->lock, flags); 1112 1113 return ret; 1114 } 1115 1116 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 1117 unsigned long *prate) 1118 { 1119 struct tegra_clk_pll *pll = to_clk_pll(hw); 1120 struct tegra_clk_pll_freq_table cfg; 1121 int ret, p_div; 1122 u64 output_rate = *prate; 1123 1124 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1125 if (ret < 0) 1126 return ret; 1127 1128 p_div = _hw_to_p_div(hw, cfg.p); 1129 if (p_div < 0) 1130 return p_div; 1131 1132 if (pll->params->set_gain) 1133 pll->params->set_gain(&cfg); 1134 1135 output_rate *= cfg.n; 1136 do_div(output_rate, cfg.m * p_div); 1137 1138 return output_rate; 1139 } 1140 1141 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1142 { 1143 u32 val; 1144 1145 val = pll_readl_misc(pll); 1146 val |= PLLCX_MISC_STROBE; 1147 pll_writel_misc(val, pll); 1148 udelay(2); 1149 1150 val &= ~PLLCX_MISC_STROBE; 1151 pll_writel_misc(val, pll); 1152 } 1153 1154 static int clk_pllc_enable(struct clk_hw *hw) 1155 { 1156 struct tegra_clk_pll *pll = to_clk_pll(hw); 1157 u32 val; 1158 int ret; 1159 unsigned long flags = 0; 1160 1161 if (pll->lock) 1162 spin_lock_irqsave(pll->lock, flags); 1163 1164 _clk_pll_enable(hw); 1165 udelay(2); 1166 1167 val = pll_readl_misc(pll); 1168 val &= ~PLLCX_MISC_RESET; 1169 pll_writel_misc(val, pll); 1170 udelay(2); 1171 1172 _pllcx_strobe(pll); 1173 1174 ret = clk_pll_wait_for_lock(pll); 1175 1176 if (pll->lock) 1177 spin_unlock_irqrestore(pll->lock, flags); 1178 1179 return ret; 1180 } 1181 1182 static void _clk_pllc_disable(struct clk_hw *hw) 1183 { 1184 struct tegra_clk_pll *pll = to_clk_pll(hw); 1185 u32 val; 1186 1187 _clk_pll_disable(hw); 1188 1189 val = pll_readl_misc(pll); 1190 val |= PLLCX_MISC_RESET; 1191 pll_writel_misc(val, pll); 1192 udelay(2); 1193 } 1194 1195 static void clk_pllc_disable(struct clk_hw *hw) 1196 { 1197 struct tegra_clk_pll *pll = to_clk_pll(hw); 1198 unsigned long flags = 0; 1199 1200 if (pll->lock) 1201 spin_lock_irqsave(pll->lock, flags); 1202 1203 _clk_pllc_disable(hw); 1204 1205 if (pll->lock) 1206 spin_unlock_irqrestore(pll->lock, flags); 1207 } 1208 1209 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1210 unsigned long input_rate, u32 n) 1211 { 1212 u32 val, n_threshold; 1213 1214 switch (input_rate) { 1215 case 12000000: 1216 n_threshold = 70; 1217 break; 1218 case 13000000: 1219 case 26000000: 1220 n_threshold = 71; 1221 break; 1222 case 16800000: 1223 n_threshold = 55; 1224 break; 1225 case 19200000: 1226 n_threshold = 48; 1227 break; 1228 default: 1229 pr_err("%s: Unexpected reference rate %lu\n", 1230 __func__, input_rate); 1231 return -EINVAL; 1232 } 1233 1234 val = pll_readl_misc(pll); 1235 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1236 val |= n <= n_threshold ? 1237 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1238 pll_writel_misc(val, pll); 1239 1240 return 0; 1241 } 1242 1243 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1244 unsigned long parent_rate) 1245 { 1246 struct tegra_clk_pll_freq_table cfg, old_cfg; 1247 struct tegra_clk_pll *pll = to_clk_pll(hw); 1248 unsigned long flags = 0; 1249 int state, ret = 0; 1250 1251 if (pll->lock) 1252 spin_lock_irqsave(pll->lock, flags); 1253 1254 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1255 if (ret < 0) 1256 goto out; 1257 1258 _get_pll_mnp(pll, &old_cfg); 1259 1260 if (cfg.m != old_cfg.m) { 1261 WARN_ON(1); 1262 goto out; 1263 } 1264 1265 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1266 goto out; 1267 1268 state = clk_pll_is_enabled(hw); 1269 if (state) 1270 _clk_pllc_disable(hw); 1271 1272 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1273 if (ret < 0) 1274 goto out; 1275 1276 _update_pll_mnp(pll, &cfg); 1277 1278 if (state) 1279 ret = clk_pllc_enable(hw); 1280 1281 out: 1282 if (pll->lock) 1283 spin_unlock_irqrestore(pll->lock, flags); 1284 1285 return ret; 1286 } 1287 1288 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1289 struct tegra_clk_pll_freq_table *cfg, 1290 unsigned long rate, unsigned long parent_rate) 1291 { 1292 u16 m, n; 1293 u64 output_rate = parent_rate; 1294 1295 m = _pll_fixed_mdiv(pll->params, parent_rate); 1296 n = rate * m / parent_rate; 1297 1298 output_rate *= n; 1299 do_div(output_rate, m); 1300 1301 if (cfg) { 1302 cfg->m = m; 1303 cfg->n = n; 1304 } 1305 1306 return output_rate; 1307 } 1308 1309 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1310 unsigned long parent_rate) 1311 { 1312 struct tegra_clk_pll_freq_table cfg, old_cfg; 1313 struct tegra_clk_pll *pll = to_clk_pll(hw); 1314 unsigned long flags = 0; 1315 int state, ret = 0; 1316 1317 if (pll->lock) 1318 spin_lock_irqsave(pll->lock, flags); 1319 1320 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1321 _get_pll_mnp(pll, &old_cfg); 1322 cfg.p = old_cfg.p; 1323 1324 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1325 state = clk_pll_is_enabled(hw); 1326 if (state) 1327 _clk_pll_disable(hw); 1328 1329 _update_pll_mnp(pll, &cfg); 1330 1331 if (state) { 1332 _clk_pll_enable(hw); 1333 ret = clk_pll_wait_for_lock(pll); 1334 } 1335 } 1336 1337 if (pll->lock) 1338 spin_unlock_irqrestore(pll->lock, flags); 1339 1340 return ret; 1341 } 1342 1343 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1344 unsigned long parent_rate) 1345 { 1346 struct tegra_clk_pll_freq_table cfg; 1347 struct tegra_clk_pll *pll = to_clk_pll(hw); 1348 u64 rate = parent_rate; 1349 1350 _get_pll_mnp(pll, &cfg); 1351 1352 rate *= cfg.n; 1353 do_div(rate, cfg.m); 1354 1355 return rate; 1356 } 1357 1358 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1359 unsigned long *prate) 1360 { 1361 struct tegra_clk_pll *pll = to_clk_pll(hw); 1362 1363 return _pllre_calc_rate(pll, NULL, rate, *prate); 1364 } 1365 1366 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1367 { 1368 struct tegra_clk_pll *pll = to_clk_pll(hw); 1369 struct tegra_clk_pll_freq_table sel; 1370 u32 val; 1371 int ret; 1372 unsigned long flags = 0; 1373 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1374 1375 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1376 return -EINVAL; 1377 1378 if (pll->lock) 1379 spin_lock_irqsave(pll->lock, flags); 1380 1381 val = pll_readl_base(pll); 1382 val &= ~BIT(29); /* Disable lock override */ 1383 pll_writel_base(val, pll); 1384 1385 val = pll_readl(pll->params->aux_reg, pll); 1386 val |= PLLE_AUX_ENABLE_SWCTL; 1387 val &= ~PLLE_AUX_SEQ_ENABLE; 1388 pll_writel(val, pll->params->aux_reg, pll); 1389 udelay(1); 1390 1391 val = pll_readl_misc(pll); 1392 val |= PLLE_MISC_LOCK_ENABLE; 1393 val |= PLLE_MISC_IDDQ_SW_CTRL; 1394 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1395 val |= PLLE_MISC_PLLE_PTS; 1396 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1397 pll_writel_misc(val, pll); 1398 udelay(5); 1399 1400 val = pll_readl(PLLE_SS_CTRL, pll); 1401 val |= PLLE_SS_DISABLE; 1402 pll_writel(val, PLLE_SS_CTRL, pll); 1403 1404 val = pll_readl_base(pll); 1405 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1406 divm_mask_shifted(pll)); 1407 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1408 val |= sel.m << divm_shift(pll); 1409 val |= sel.n << divn_shift(pll); 1410 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1411 pll_writel_base(val, pll); 1412 udelay(1); 1413 1414 _clk_pll_enable(hw); 1415 ret = clk_pll_wait_for_lock(pll); 1416 1417 if (ret < 0) 1418 goto out; 1419 1420 val = pll_readl(PLLE_SS_CTRL, pll); 1421 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1422 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1423 val |= PLLE_SS_COEFFICIENTS_VAL; 1424 pll_writel(val, PLLE_SS_CTRL, pll); 1425 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1426 pll_writel(val, PLLE_SS_CTRL, pll); 1427 udelay(1); 1428 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1429 pll_writel(val, PLLE_SS_CTRL, pll); 1430 udelay(1); 1431 1432 /* Enable hw control of xusb brick pll */ 1433 val = pll_readl_misc(pll); 1434 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1435 pll_writel_misc(val, pll); 1436 1437 val = pll_readl(pll->params->aux_reg, pll); 1438 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1439 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1440 pll_writel(val, pll->params->aux_reg, pll); 1441 udelay(1); 1442 val |= PLLE_AUX_SEQ_ENABLE; 1443 pll_writel(val, pll->params->aux_reg, pll); 1444 1445 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1446 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1447 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1448 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1449 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1450 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1451 udelay(1); 1452 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1453 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1454 1455 /* Enable hw control of SATA pll */ 1456 val = pll_readl(SATA_PLL_CFG0, pll); 1457 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1458 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1459 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1460 pll_writel(val, SATA_PLL_CFG0, pll); 1461 1462 udelay(1); 1463 1464 val = pll_readl(SATA_PLL_CFG0, pll); 1465 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1466 pll_writel(val, SATA_PLL_CFG0, pll); 1467 1468 out: 1469 if (pll->lock) 1470 spin_unlock_irqrestore(pll->lock, flags); 1471 1472 return ret; 1473 } 1474 1475 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1476 { 1477 struct tegra_clk_pll *pll = to_clk_pll(hw); 1478 unsigned long flags = 0; 1479 u32 val; 1480 1481 if (pll->lock) 1482 spin_lock_irqsave(pll->lock, flags); 1483 1484 _clk_pll_disable(hw); 1485 1486 val = pll_readl_misc(pll); 1487 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1488 pll_writel_misc(val, pll); 1489 udelay(1); 1490 1491 if (pll->lock) 1492 spin_unlock_irqrestore(pll->lock, flags); 1493 } 1494 #endif 1495 1496 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1497 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1498 spinlock_t *lock) 1499 { 1500 struct tegra_clk_pll *pll; 1501 1502 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1503 if (!pll) 1504 return ERR_PTR(-ENOMEM); 1505 1506 pll->clk_base = clk_base; 1507 pll->pmc = pmc; 1508 1509 pll->params = pll_params; 1510 pll->lock = lock; 1511 1512 if (!pll_params->div_nmp) 1513 pll_params->div_nmp = &default_nmp; 1514 1515 return pll; 1516 } 1517 1518 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1519 const char *name, const char *parent_name, unsigned long flags, 1520 const struct clk_ops *ops) 1521 { 1522 struct clk_init_data init; 1523 1524 init.name = name; 1525 init.ops = ops; 1526 init.flags = flags; 1527 init.parent_names = (parent_name ? &parent_name : NULL); 1528 init.num_parents = (parent_name ? 1 : 0); 1529 1530 /* Default to _calc_rate if unspecified */ 1531 if (!pll->params->calc_rate) { 1532 if (pll->params->flags & TEGRA_PLLM) 1533 pll->params->calc_rate = _calc_dynamic_ramp_rate; 1534 else 1535 pll->params->calc_rate = _calc_rate; 1536 } 1537 1538 if (pll->params->set_defaults) 1539 pll->params->set_defaults(pll); 1540 1541 /* Data in .init is copied by clk_register(), so stack variable OK */ 1542 pll->hw.init = &init; 1543 1544 return clk_register(NULL, &pll->hw); 1545 } 1546 1547 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1548 void __iomem *clk_base, void __iomem *pmc, 1549 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1550 spinlock_t *lock) 1551 { 1552 struct tegra_clk_pll *pll; 1553 struct clk *clk; 1554 1555 pll_params->flags |= TEGRA_PLL_BYPASS; 1556 1557 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1558 if (IS_ERR(pll)) 1559 return ERR_CAST(pll); 1560 1561 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1562 &tegra_clk_pll_ops); 1563 if (IS_ERR(clk)) 1564 kfree(pll); 1565 1566 return clk; 1567 } 1568 1569 static struct div_nmp pll_e_nmp = { 1570 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1571 .divn_width = PLLE_BASE_DIVN_WIDTH, 1572 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1573 .divm_width = PLLE_BASE_DIVM_WIDTH, 1574 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1575 .divp_width = PLLE_BASE_DIVP_WIDTH, 1576 }; 1577 1578 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1579 void __iomem *clk_base, void __iomem *pmc, 1580 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1581 spinlock_t *lock) 1582 { 1583 struct tegra_clk_pll *pll; 1584 struct clk *clk; 1585 1586 pll_params->flags |= TEGRA_PLL_BYPASS; 1587 1588 if (!pll_params->div_nmp) 1589 pll_params->div_nmp = &pll_e_nmp; 1590 1591 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1592 if (IS_ERR(pll)) 1593 return ERR_CAST(pll); 1594 1595 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1596 &tegra_clk_plle_ops); 1597 if (IS_ERR(clk)) 1598 kfree(pll); 1599 1600 return clk; 1601 } 1602 1603 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1604 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1605 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1606 defined(CONFIG_ARCH_TEGRA_210_SOC) 1607 static const struct clk_ops tegra_clk_pllxc_ops = { 1608 .is_enabled = clk_pll_is_enabled, 1609 .enable = clk_pll_enable, 1610 .disable = clk_pll_disable, 1611 .recalc_rate = clk_pll_recalc_rate, 1612 .round_rate = clk_pll_ramp_round_rate, 1613 .set_rate = clk_pllxc_set_rate, 1614 }; 1615 1616 static const struct clk_ops tegra_clk_pllc_ops = { 1617 .is_enabled = clk_pll_is_enabled, 1618 .enable = clk_pllc_enable, 1619 .disable = clk_pllc_disable, 1620 .recalc_rate = clk_pll_recalc_rate, 1621 .round_rate = clk_pll_ramp_round_rate, 1622 .set_rate = clk_pllc_set_rate, 1623 }; 1624 1625 static const struct clk_ops tegra_clk_pllre_ops = { 1626 .is_enabled = clk_pll_is_enabled, 1627 .enable = clk_pll_enable, 1628 .disable = clk_pll_disable, 1629 .recalc_rate = clk_pllre_recalc_rate, 1630 .round_rate = clk_pllre_round_rate, 1631 .set_rate = clk_pllre_set_rate, 1632 }; 1633 1634 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1635 .is_enabled = clk_pll_is_enabled, 1636 .enable = clk_plle_tegra114_enable, 1637 .disable = clk_plle_tegra114_disable, 1638 .recalc_rate = clk_pll_recalc_rate, 1639 }; 1640 1641 1642 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1643 void __iomem *clk_base, void __iomem *pmc, 1644 unsigned long flags, 1645 struct tegra_clk_pll_params *pll_params, 1646 spinlock_t *lock) 1647 { 1648 struct tegra_clk_pll *pll; 1649 struct clk *clk, *parent; 1650 unsigned long parent_rate; 1651 u32 val, val_iddq; 1652 1653 parent = __clk_lookup(parent_name); 1654 if (!parent) { 1655 WARN(1, "parent clk %s of %s must be registered first\n", 1656 parent_name, name); 1657 return ERR_PTR(-EINVAL); 1658 } 1659 1660 if (!pll_params->pdiv_tohw) 1661 return ERR_PTR(-EINVAL); 1662 1663 parent_rate = clk_get_rate(parent); 1664 1665 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1666 1667 if (pll_params->adjust_vco) 1668 pll_params->vco_min = pll_params->adjust_vco(pll_params, 1669 parent_rate); 1670 1671 /* 1672 * If the pll has a set_defaults callback, it will take care of 1673 * configuring dynamic ramping and setting IDDQ in that path. 1674 */ 1675 if (!pll_params->set_defaults) { 1676 int err; 1677 1678 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1679 if (err) 1680 return ERR_PTR(err); 1681 1682 val = readl_relaxed(clk_base + pll_params->base_reg); 1683 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1684 1685 if (val & PLL_BASE_ENABLE) 1686 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1687 else { 1688 val_iddq |= BIT(pll_params->iddq_bit_idx); 1689 writel_relaxed(val_iddq, 1690 clk_base + pll_params->iddq_reg); 1691 } 1692 } 1693 1694 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1695 if (IS_ERR(pll)) 1696 return ERR_CAST(pll); 1697 1698 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1699 &tegra_clk_pllxc_ops); 1700 if (IS_ERR(clk)) 1701 kfree(pll); 1702 1703 return clk; 1704 } 1705 1706 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1707 void __iomem *clk_base, void __iomem *pmc, 1708 unsigned long flags, 1709 struct tegra_clk_pll_params *pll_params, 1710 spinlock_t *lock, unsigned long parent_rate) 1711 { 1712 u32 val; 1713 struct tegra_clk_pll *pll; 1714 struct clk *clk; 1715 1716 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1717 1718 if (pll_params->adjust_vco) 1719 pll_params->vco_min = pll_params->adjust_vco(pll_params, 1720 parent_rate); 1721 1722 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1723 if (IS_ERR(pll)) 1724 return ERR_CAST(pll); 1725 1726 /* program minimum rate by default */ 1727 1728 val = pll_readl_base(pll); 1729 if (val & PLL_BASE_ENABLE) 1730 WARN_ON(val & pll_params->iddq_bit_idx); 1731 else { 1732 int m; 1733 1734 m = _pll_fixed_mdiv(pll_params, parent_rate); 1735 val = m << divm_shift(pll); 1736 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 1737 pll_writel_base(val, pll); 1738 } 1739 1740 /* disable lock override */ 1741 1742 val = pll_readl_misc(pll); 1743 val &= ~BIT(29); 1744 pll_writel_misc(val, pll); 1745 1746 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1747 &tegra_clk_pllre_ops); 1748 if (IS_ERR(clk)) 1749 kfree(pll); 1750 1751 return clk; 1752 } 1753 1754 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1755 void __iomem *clk_base, void __iomem *pmc, 1756 unsigned long flags, 1757 struct tegra_clk_pll_params *pll_params, 1758 spinlock_t *lock) 1759 { 1760 struct tegra_clk_pll *pll; 1761 struct clk *clk, *parent; 1762 unsigned long parent_rate; 1763 1764 if (!pll_params->pdiv_tohw) 1765 return ERR_PTR(-EINVAL); 1766 1767 parent = __clk_lookup(parent_name); 1768 if (!parent) { 1769 WARN(1, "parent clk %s of %s must be registered first\n", 1770 parent_name, name); 1771 return ERR_PTR(-EINVAL); 1772 } 1773 1774 parent_rate = clk_get_rate(parent); 1775 1776 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1777 1778 if (pll_params->adjust_vco) 1779 pll_params->vco_min = pll_params->adjust_vco(pll_params, 1780 parent_rate); 1781 1782 pll_params->flags |= TEGRA_PLL_BYPASS; 1783 pll_params->flags |= TEGRA_PLLM; 1784 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1785 if (IS_ERR(pll)) 1786 return ERR_CAST(pll); 1787 1788 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1789 &tegra_clk_pll_ops); 1790 if (IS_ERR(clk)) 1791 kfree(pll); 1792 1793 return clk; 1794 } 1795 1796 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1797 void __iomem *clk_base, void __iomem *pmc, 1798 unsigned long flags, 1799 struct tegra_clk_pll_params *pll_params, 1800 spinlock_t *lock) 1801 { 1802 struct clk *parent, *clk; 1803 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1804 struct tegra_clk_pll *pll; 1805 struct tegra_clk_pll_freq_table cfg; 1806 unsigned long parent_rate; 1807 1808 if (!p_tohw) 1809 return ERR_PTR(-EINVAL); 1810 1811 parent = __clk_lookup(parent_name); 1812 if (!parent) { 1813 WARN(1, "parent clk %s of %s must be registered first\n", 1814 parent_name, name); 1815 return ERR_PTR(-EINVAL); 1816 } 1817 1818 parent_rate = clk_get_rate(parent); 1819 1820 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1821 1822 pll_params->flags |= TEGRA_PLL_BYPASS; 1823 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1824 if (IS_ERR(pll)) 1825 return ERR_CAST(pll); 1826 1827 /* 1828 * Most of PLLC register fields are shadowed, and can not be read 1829 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1830 * Initialize PLL to default state: disabled, reset; shadow registers 1831 * loaded with default parameters; dividers are preset for half of 1832 * minimum VCO rate (the latter assured that shadowed divider settings 1833 * are within supported range). 1834 */ 1835 1836 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1837 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1838 1839 while (p_tohw->pdiv) { 1840 if (p_tohw->pdiv == 2) { 1841 cfg.p = p_tohw->hw_val; 1842 break; 1843 } 1844 p_tohw++; 1845 } 1846 1847 if (!p_tohw->pdiv) { 1848 WARN_ON(1); 1849 return ERR_PTR(-EINVAL); 1850 } 1851 1852 pll_writel_base(0, pll); 1853 _update_pll_mnp(pll, &cfg); 1854 1855 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1856 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1857 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1858 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1859 1860 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1861 1862 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1863 &tegra_clk_pllc_ops); 1864 if (IS_ERR(clk)) 1865 kfree(pll); 1866 1867 return clk; 1868 } 1869 1870 struct clk *tegra_clk_register_plle_tegra114(const char *name, 1871 const char *parent_name, 1872 void __iomem *clk_base, unsigned long flags, 1873 struct tegra_clk_pll_params *pll_params, 1874 spinlock_t *lock) 1875 { 1876 struct tegra_clk_pll *pll; 1877 struct clk *clk; 1878 u32 val, val_aux; 1879 1880 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1881 if (IS_ERR(pll)) 1882 return ERR_CAST(pll); 1883 1884 /* ensure parent is set to pll_re_vco */ 1885 1886 val = pll_readl_base(pll); 1887 val_aux = pll_readl(pll_params->aux_reg, pll); 1888 1889 if (val & PLL_BASE_ENABLE) { 1890 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1891 (val_aux & PLLE_AUX_PLLP_SEL)) 1892 WARN(1, "pll_e enabled with unsupported parent %s\n", 1893 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1894 "pll_re_vco"); 1895 } else { 1896 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1897 pll_writel(val_aux, pll_params->aux_reg, pll); 1898 } 1899 1900 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1901 &tegra_clk_plle_tegra114_ops); 1902 if (IS_ERR(clk)) 1903 kfree(pll); 1904 1905 return clk; 1906 } 1907 #endif 1908 1909 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 1910 static const struct clk_ops tegra_clk_pllss_ops = { 1911 .is_enabled = clk_pll_is_enabled, 1912 .enable = clk_pll_enable, 1913 .disable = clk_pll_disable, 1914 .recalc_rate = clk_pll_recalc_rate, 1915 .round_rate = clk_pll_ramp_round_rate, 1916 .set_rate = clk_pllxc_set_rate, 1917 }; 1918 1919 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 1920 void __iomem *clk_base, unsigned long flags, 1921 struct tegra_clk_pll_params *pll_params, 1922 spinlock_t *lock) 1923 { 1924 struct tegra_clk_pll *pll; 1925 struct clk *clk, *parent; 1926 struct tegra_clk_pll_freq_table cfg; 1927 unsigned long parent_rate; 1928 u32 val; 1929 int i; 1930 1931 if (!pll_params->div_nmp) 1932 return ERR_PTR(-EINVAL); 1933 1934 parent = __clk_lookup(parent_name); 1935 if (!parent) { 1936 WARN(1, "parent clk %s of %s must be registered first\n", 1937 parent_name, name); 1938 return ERR_PTR(-EINVAL); 1939 } 1940 1941 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1942 if (IS_ERR(pll)) 1943 return ERR_CAST(pll); 1944 1945 val = pll_readl_base(pll); 1946 val &= ~PLLSS_REF_SRC_SEL_MASK; 1947 pll_writel_base(val, pll); 1948 1949 parent_rate = clk_get_rate(parent); 1950 1951 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1952 1953 /* initialize PLL to minimum rate */ 1954 1955 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1956 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1957 1958 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 1959 ; 1960 if (!i) { 1961 kfree(pll); 1962 return ERR_PTR(-EINVAL); 1963 } 1964 1965 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 1966 1967 _update_pll_mnp(pll, &cfg); 1968 1969 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 1970 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 1971 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 1972 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1973 1974 val = pll_readl_base(pll); 1975 if (val & PLL_BASE_ENABLE) { 1976 if (val & BIT(pll_params->iddq_bit_idx)) { 1977 WARN(1, "%s is on but IDDQ set\n", name); 1978 kfree(pll); 1979 return ERR_PTR(-EINVAL); 1980 } 1981 } else 1982 val |= BIT(pll_params->iddq_bit_idx); 1983 1984 val &= ~PLLSS_LOCK_OVERRIDE; 1985 pll_writel_base(val, pll); 1986 1987 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1988 &tegra_clk_pllss_ops); 1989 1990 if (IS_ERR(clk)) 1991 kfree(pll); 1992 1993 return clk; 1994 } 1995 #endif 1996 1997 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 1998 static int clk_plle_tegra210_enable(struct clk_hw *hw) 1999 { 2000 struct tegra_clk_pll *pll = to_clk_pll(hw); 2001 struct tegra_clk_pll_freq_table sel; 2002 u32 val; 2003 int ret; 2004 unsigned long flags = 0; 2005 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 2006 2007 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 2008 return -EINVAL; 2009 2010 if (pll->lock) 2011 spin_lock_irqsave(pll->lock, flags); 2012 2013 val = pll_readl_base(pll); 2014 val &= ~BIT(30); /* Disable lock override */ 2015 pll_writel_base(val, pll); 2016 2017 val = pll_readl(pll->params->aux_reg, pll); 2018 val |= PLLE_AUX_ENABLE_SWCTL; 2019 val &= ~PLLE_AUX_SEQ_ENABLE; 2020 pll_writel(val, pll->params->aux_reg, pll); 2021 udelay(1); 2022 2023 val = pll_readl_misc(pll); 2024 val |= PLLE_MISC_LOCK_ENABLE; 2025 val |= PLLE_MISC_IDDQ_SW_CTRL; 2026 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 2027 val |= PLLE_MISC_PLLE_PTS; 2028 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 2029 pll_writel_misc(val, pll); 2030 udelay(5); 2031 2032 val = pll_readl(PLLE_SS_CTRL, pll); 2033 val |= PLLE_SS_DISABLE; 2034 pll_writel(val, PLLE_SS_CTRL, pll); 2035 2036 val = pll_readl_base(pll); 2037 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 2038 divm_mask_shifted(pll)); 2039 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 2040 val |= sel.m << divm_shift(pll); 2041 val |= sel.n << divn_shift(pll); 2042 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 2043 pll_writel_base(val, pll); 2044 udelay(1); 2045 2046 val = pll_readl_base(pll); 2047 val |= PLLE_BASE_ENABLE; 2048 pll_writel_base(val, pll); 2049 2050 ret = clk_pll_wait_for_lock(pll); 2051 2052 if (ret < 0) 2053 goto out; 2054 2055 val = pll_readl(PLLE_SS_CTRL, pll); 2056 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 2057 val &= ~PLLE_SS_COEFFICIENTS_MASK; 2058 val |= PLLE_SS_COEFFICIENTS_VAL; 2059 pll_writel(val, PLLE_SS_CTRL, pll); 2060 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 2061 pll_writel(val, PLLE_SS_CTRL, pll); 2062 udelay(1); 2063 val &= ~PLLE_SS_CNTL_INTERP_RESET; 2064 pll_writel(val, PLLE_SS_CTRL, pll); 2065 udelay(1); 2066 2067 val = pll_readl_misc(pll); 2068 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 2069 pll_writel_misc(val, pll); 2070 2071 val = pll_readl(pll->params->aux_reg, pll); 2072 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); 2073 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 2074 pll_writel(val, pll->params->aux_reg, pll); 2075 udelay(1); 2076 val |= PLLE_AUX_SEQ_ENABLE; 2077 pll_writel(val, pll->params->aux_reg, pll); 2078 2079 out: 2080 if (pll->lock) 2081 spin_unlock_irqrestore(pll->lock, flags); 2082 2083 return ret; 2084 } 2085 2086 static void clk_plle_tegra210_disable(struct clk_hw *hw) 2087 { 2088 struct tegra_clk_pll *pll = to_clk_pll(hw); 2089 unsigned long flags = 0; 2090 u32 val; 2091 2092 if (pll->lock) 2093 spin_lock_irqsave(pll->lock, flags); 2094 2095 val = pll_readl_base(pll); 2096 val &= ~PLLE_BASE_ENABLE; 2097 pll_writel_base(val, pll); 2098 2099 val = pll_readl_misc(pll); 2100 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 2101 pll_writel_misc(val, pll); 2102 udelay(1); 2103 2104 if (pll->lock) 2105 spin_unlock_irqrestore(pll->lock, flags); 2106 } 2107 2108 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw) 2109 { 2110 struct tegra_clk_pll *pll = to_clk_pll(hw); 2111 u32 val; 2112 2113 val = pll_readl_base(pll); 2114 2115 return val & PLLE_BASE_ENABLE ? 1 : 0; 2116 } 2117 2118 static const struct clk_ops tegra_clk_plle_tegra210_ops = { 2119 .is_enabled = clk_plle_tegra210_is_enabled, 2120 .enable = clk_plle_tegra210_enable, 2121 .disable = clk_plle_tegra210_disable, 2122 .recalc_rate = clk_pll_recalc_rate, 2123 }; 2124 2125 struct clk *tegra_clk_register_plle_tegra210(const char *name, 2126 const char *parent_name, 2127 void __iomem *clk_base, unsigned long flags, 2128 struct tegra_clk_pll_params *pll_params, 2129 spinlock_t *lock) 2130 { 2131 struct tegra_clk_pll *pll; 2132 struct clk *clk; 2133 u32 val, val_aux; 2134 2135 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2136 if (IS_ERR(pll)) 2137 return ERR_CAST(pll); 2138 2139 /* ensure parent is set to pll_re_vco */ 2140 2141 val = pll_readl_base(pll); 2142 val_aux = pll_readl(pll_params->aux_reg, pll); 2143 2144 if (val & PLLE_BASE_ENABLE) { 2145 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 2146 (val_aux & PLLE_AUX_PLLP_SEL)) 2147 WARN(1, "pll_e enabled with unsupported parent %s\n", 2148 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 2149 "pll_re_vco"); 2150 } else { 2151 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 2152 pll_writel(val_aux, pll_params->aux_reg, pll); 2153 } 2154 2155 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2156 &tegra_clk_plle_tegra210_ops); 2157 if (IS_ERR(clk)) 2158 kfree(pll); 2159 2160 return clk; 2161 } 2162 2163 struct clk *tegra_clk_register_pllc_tegra210(const char *name, 2164 const char *parent_name, void __iomem *clk_base, 2165 void __iomem *pmc, unsigned long flags, 2166 struct tegra_clk_pll_params *pll_params, 2167 spinlock_t *lock) 2168 { 2169 struct clk *parent, *clk; 2170 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 2171 struct tegra_clk_pll *pll; 2172 unsigned long parent_rate; 2173 2174 if (!p_tohw) 2175 return ERR_PTR(-EINVAL); 2176 2177 parent = __clk_lookup(parent_name); 2178 if (!parent) { 2179 WARN(1, "parent clk %s of %s must be registered first\n", 2180 name, parent_name); 2181 return ERR_PTR(-EINVAL); 2182 } 2183 2184 parent_rate = clk_get_rate(parent); 2185 2186 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2187 2188 if (pll_params->adjust_vco) 2189 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2190 parent_rate); 2191 2192 pll_params->flags |= TEGRA_PLL_BYPASS; 2193 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2194 if (IS_ERR(pll)) 2195 return ERR_CAST(pll); 2196 2197 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2198 &tegra_clk_pll_ops); 2199 if (IS_ERR(clk)) 2200 kfree(pll); 2201 2202 return clk; 2203 } 2204 2205 struct clk *tegra_clk_register_pllxc_tegra210(const char *name, 2206 const char *parent_name, void __iomem *clk_base, 2207 void __iomem *pmc, unsigned long flags, 2208 struct tegra_clk_pll_params *pll_params, 2209 spinlock_t *lock) 2210 { 2211 struct tegra_clk_pll *pll; 2212 struct clk *clk, *parent; 2213 unsigned long parent_rate; 2214 2215 parent = __clk_lookup(parent_name); 2216 if (!parent) { 2217 WARN(1, "parent clk %s of %s must be registered first\n", 2218 name, parent_name); 2219 return ERR_PTR(-EINVAL); 2220 } 2221 2222 if (!pll_params->pdiv_tohw) 2223 return ERR_PTR(-EINVAL); 2224 2225 parent_rate = clk_get_rate(parent); 2226 2227 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2228 2229 if (pll_params->adjust_vco) 2230 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2231 parent_rate); 2232 2233 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2234 if (IS_ERR(pll)) 2235 return ERR_CAST(pll); 2236 2237 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2238 &tegra_clk_pll_ops); 2239 if (IS_ERR(clk)) 2240 kfree(pll); 2241 2242 return clk; 2243 } 2244 2245 struct clk *tegra_clk_register_pllss_tegra210(const char *name, 2246 const char *parent_name, void __iomem *clk_base, 2247 unsigned long flags, 2248 struct tegra_clk_pll_params *pll_params, 2249 spinlock_t *lock) 2250 { 2251 struct tegra_clk_pll *pll; 2252 struct clk *clk, *parent; 2253 struct tegra_clk_pll_freq_table cfg; 2254 unsigned long parent_rate; 2255 u32 val; 2256 int i; 2257 2258 if (!pll_params->div_nmp) 2259 return ERR_PTR(-EINVAL); 2260 2261 parent = __clk_lookup(parent_name); 2262 if (!parent) { 2263 WARN(1, "parent clk %s of %s must be registered first\n", 2264 name, parent_name); 2265 return ERR_PTR(-EINVAL); 2266 } 2267 2268 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2269 if (IS_ERR(pll)) 2270 return ERR_CAST(pll); 2271 2272 val = pll_readl_base(pll); 2273 val &= ~PLLSS_REF_SRC_SEL_MASK; 2274 pll_writel_base(val, pll); 2275 2276 parent_rate = clk_get_rate(parent); 2277 2278 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2279 2280 if (pll_params->adjust_vco) 2281 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2282 parent_rate); 2283 2284 /* initialize PLL to minimum rate */ 2285 2286 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 2287 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 2288 2289 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 2290 ; 2291 if (!i) { 2292 kfree(pll); 2293 return ERR_PTR(-EINVAL); 2294 } 2295 2296 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 2297 2298 _update_pll_mnp(pll, &cfg); 2299 2300 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 2301 2302 val = pll_readl_base(pll); 2303 if (val & PLL_BASE_ENABLE) { 2304 if (val & BIT(pll_params->iddq_bit_idx)) { 2305 WARN(1, "%s is on but IDDQ set\n", name); 2306 kfree(pll); 2307 return ERR_PTR(-EINVAL); 2308 } 2309 } else 2310 val |= BIT(pll_params->iddq_bit_idx); 2311 2312 val &= ~PLLSS_LOCK_OVERRIDE; 2313 pll_writel_base(val, pll); 2314 2315 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2316 &tegra_clk_pll_ops); 2317 2318 if (IS_ERR(clk)) 2319 kfree(pll); 2320 2321 return clk; 2322 } 2323 2324 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 2325 void __iomem *clk_base, void __iomem *pmc, 2326 unsigned long flags, 2327 struct tegra_clk_pll_params *pll_params, 2328 spinlock_t *lock) 2329 { 2330 struct tegra_clk_pll *pll; 2331 struct clk *clk, *parent; 2332 unsigned long parent_rate; 2333 2334 if (!pll_params->pdiv_tohw) 2335 return ERR_PTR(-EINVAL); 2336 2337 parent = __clk_lookup(parent_name); 2338 if (!parent) { 2339 WARN(1, "parent clk %s of %s must be registered first\n", 2340 parent_name, name); 2341 return ERR_PTR(-EINVAL); 2342 } 2343 2344 parent_rate = clk_get_rate(parent); 2345 2346 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2347 2348 if (pll_params->adjust_vco) 2349 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2350 parent_rate); 2351 2352 pll_params->flags |= TEGRA_PLL_BYPASS; 2353 pll_params->flags |= TEGRA_PLLMB; 2354 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2355 if (IS_ERR(pll)) 2356 return ERR_CAST(pll); 2357 2358 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2359 &tegra_clk_pll_ops); 2360 if (IS_ERR(clk)) 2361 kfree(pll); 2362 2363 return clk; 2364 } 2365 #endif 2366