1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 #define PLLE_BASE_ENABLE BIT(31) 69 70 #define PLLE_MISC_SETUP_BASE_SHIFT 16 71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 72 #define PLLE_MISC_LOCK_ENABLE BIT(9) 73 #define PLLE_MISC_READY BIT(15) 74 #define PLLE_MISC_SETUP_EX_SHIFT 2 75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 77 PLLE_MISC_SETUP_EX_MASK) 78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 79 80 #define PLLE_SS_CTRL 0x68 81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 83 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 84 #define PLLE_SS_CNTL_CENTER BIT(14) 85 #define PLLE_SS_CNTL_INVERT BIT(15) 86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 87 PLLE_SS_CNTL_SSC_BYP) 88 #define PLLE_SS_MAX_MASK 0x1ff 89 #define PLLE_SS_MAX_VAL 0x25 90 #define PLLE_SS_INC_MASK (0xff << 16) 91 #define PLLE_SS_INC_VAL (0x1 << 16) 92 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 93 #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 94 #define PLLE_SS_COEFFICIENTS_MASK \ 95 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 96 #define PLLE_SS_COEFFICIENTS_VAL \ 97 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 98 99 #define PLLE_AUX_PLLP_SEL BIT(2) 100 #define PLLE_AUX_USE_LOCKDET BIT(3) 101 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 102 #define PLLE_AUX_SS_SWCTL BIT(6) 103 #define PLLE_AUX_SEQ_ENABLE BIT(24) 104 #define PLLE_AUX_SEQ_START_STATE BIT(25) 105 #define PLLE_AUX_PLLRE_SEL BIT(28) 106 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31) 107 108 #define XUSBIO_PLL_CFG0 0x51c 109 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 110 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 111 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 112 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 113 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 114 115 #define SATA_PLL_CFG0 0x490 116 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 117 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 118 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 119 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 120 121 #define PLLE_MISC_PLLE_PTS BIT(8) 122 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 123 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 124 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 125 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 126 #define PLLE_MISC_VREG_CTRL_SHIFT 2 127 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 128 129 #define PLLCX_MISC_STROBE BIT(31) 130 #define PLLCX_MISC_RESET BIT(30) 131 #define PLLCX_MISC_SDM_DIV_SHIFT 28 132 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 133 #define PLLCX_MISC_FILT_DIV_SHIFT 26 134 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 135 #define PLLCX_MISC_ALPHA_SHIFT 18 136 #define PLLCX_MISC_DIV_LOW_RANGE \ 137 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 138 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 139 #define PLLCX_MISC_DIV_HIGH_RANGE \ 140 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 141 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 142 #define PLLCX_MISC_COEF_LOW_RANGE \ 143 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 144 #define PLLCX_MISC_KA_SHIFT 2 145 #define PLLCX_MISC_KB_SHIFT 9 146 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 147 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 148 PLLCX_MISC_DIV_LOW_RANGE | \ 149 PLLCX_MISC_RESET) 150 #define PLLCX_MISC1_DEFAULT 0x000d2308 151 #define PLLCX_MISC2_DEFAULT 0x30211200 152 #define PLLCX_MISC3_DEFAULT 0x200 153 154 #define PMC_SATA_PWRGT 0x1ac 155 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 156 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 157 158 #define PLLSS_MISC_KCP 0 159 #define PLLSS_MISC_KVCO 0 160 #define PLLSS_MISC_SETUP 0 161 #define PLLSS_EN_SDM 0 162 #define PLLSS_EN_SSC 0 163 #define PLLSS_EN_DITHER2 0 164 #define PLLSS_EN_DITHER 1 165 #define PLLSS_SDM_RESET 0 166 #define PLLSS_CLAMP 0 167 #define PLLSS_SDM_SSC_MAX 0 168 #define PLLSS_SDM_SSC_MIN 0 169 #define PLLSS_SDM_SSC_STEP 0 170 #define PLLSS_SDM_DIN 0 171 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 172 (PLLSS_MISC_KVCO << 24) | \ 173 PLLSS_MISC_SETUP) 174 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 175 (PLLSS_EN_SSC << 30) | \ 176 (PLLSS_EN_DITHER2 << 29) | \ 177 (PLLSS_EN_DITHER << 28) | \ 178 (PLLSS_SDM_RESET) << 27 | \ 179 (PLLSS_CLAMP << 22)) 180 #define PLLSS_CTRL1_DEFAULT \ 181 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 182 #define PLLSS_CTRL2_DEFAULT \ 183 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 184 #define PLLSS_LOCK_OVERRIDE BIT(24) 185 #define PLLSS_REF_SRC_SEL_SHIFT 25 186 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 187 188 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 189 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 190 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 191 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 192 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p) 193 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p) 194 195 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 196 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 197 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 198 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 199 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) 200 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) 201 202 #define mask(w) ((1 << (w)) - 1) 203 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 204 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 205 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 206 mask(p->params->div_nmp->divp_width)) 207 #define sdm_din_mask(p) p->params->sdm_din_mask 208 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask 209 210 #define divm_shift(p) (p)->params->div_nmp->divm_shift 211 #define divn_shift(p) (p)->params->div_nmp->divn_shift 212 #define divp_shift(p) (p)->params->div_nmp->divp_shift 213 214 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 215 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 216 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 217 218 #define divm_max(p) (divm_mask(p)) 219 #define divn_max(p) (divn_mask(p)) 220 #define divp_max(p) (1 << (divp_mask(p))) 221 222 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 223 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 224 225 static struct div_nmp default_nmp = { 226 .divn_shift = PLL_BASE_DIVN_SHIFT, 227 .divn_width = PLL_BASE_DIVN_WIDTH, 228 .divm_shift = PLL_BASE_DIVM_SHIFT, 229 .divm_width = PLL_BASE_DIVM_WIDTH, 230 .divp_shift = PLL_BASE_DIVP_SHIFT, 231 .divp_width = PLL_BASE_DIVP_WIDTH, 232 }; 233 234 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 235 { 236 u32 val; 237 238 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 239 return; 240 241 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 242 return; 243 244 val = pll_readl_misc(pll); 245 val |= BIT(pll->params->lock_enable_bit_idx); 246 pll_writel_misc(val, pll); 247 } 248 249 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 250 { 251 int i; 252 u32 val, lock_mask; 253 void __iomem *lock_addr; 254 255 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 256 udelay(pll->params->lock_delay); 257 return 0; 258 } 259 260 lock_addr = pll->clk_base; 261 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 262 lock_addr += pll->params->misc_reg; 263 else 264 lock_addr += pll->params->base_reg; 265 266 lock_mask = pll->params->lock_mask; 267 268 for (i = 0; i < pll->params->lock_delay; i++) { 269 val = readl_relaxed(lock_addr); 270 if ((val & lock_mask) == lock_mask) { 271 udelay(PLL_POST_LOCK_DELAY); 272 return 0; 273 } 274 udelay(2); /* timeout = 2 * lock time */ 275 } 276 277 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 278 clk_hw_get_name(&pll->hw)); 279 280 return -1; 281 } 282 283 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 284 { 285 return clk_pll_wait_for_lock(pll); 286 } 287 288 static int clk_pll_is_enabled(struct clk_hw *hw) 289 { 290 struct tegra_clk_pll *pll = to_clk_pll(hw); 291 u32 val; 292 293 if (pll->params->flags & TEGRA_PLLM) { 294 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 295 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 296 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 297 } 298 299 val = pll_readl_base(pll); 300 301 return val & PLL_BASE_ENABLE ? 1 : 0; 302 } 303 304 static void _clk_pll_enable(struct clk_hw *hw) 305 { 306 struct tegra_clk_pll *pll = to_clk_pll(hw); 307 u32 val; 308 309 if (pll->params->iddq_reg) { 310 val = pll_readl(pll->params->iddq_reg, pll); 311 val &= ~BIT(pll->params->iddq_bit_idx); 312 pll_writel(val, pll->params->iddq_reg, pll); 313 udelay(2); 314 } 315 316 if (pll->params->reset_reg) { 317 val = pll_readl(pll->params->reset_reg, pll); 318 val &= ~BIT(pll->params->reset_bit_idx); 319 pll_writel(val, pll->params->reset_reg, pll); 320 } 321 322 clk_pll_enable_lock(pll); 323 324 val = pll_readl_base(pll); 325 if (pll->params->flags & TEGRA_PLL_BYPASS) 326 val &= ~PLL_BASE_BYPASS; 327 val |= PLL_BASE_ENABLE; 328 pll_writel_base(val, pll); 329 330 if (pll->params->flags & TEGRA_PLLM) { 331 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 332 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 333 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 334 } 335 } 336 337 static void _clk_pll_disable(struct clk_hw *hw) 338 { 339 struct tegra_clk_pll *pll = to_clk_pll(hw); 340 u32 val; 341 342 val = pll_readl_base(pll); 343 if (pll->params->flags & TEGRA_PLL_BYPASS) 344 val &= ~PLL_BASE_BYPASS; 345 val &= ~PLL_BASE_ENABLE; 346 pll_writel_base(val, pll); 347 348 if (pll->params->flags & TEGRA_PLLM) { 349 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 350 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 351 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 352 } 353 354 if (pll->params->reset_reg) { 355 val = pll_readl(pll->params->reset_reg, pll); 356 val |= BIT(pll->params->reset_bit_idx); 357 pll_writel(val, pll->params->reset_reg, pll); 358 } 359 360 if (pll->params->iddq_reg) { 361 val = pll_readl(pll->params->iddq_reg, pll); 362 val |= BIT(pll->params->iddq_bit_idx); 363 pll_writel(val, pll->params->iddq_reg, pll); 364 udelay(2); 365 } 366 } 367 368 static int clk_pll_enable(struct clk_hw *hw) 369 { 370 struct tegra_clk_pll *pll = to_clk_pll(hw); 371 unsigned long flags = 0; 372 int ret; 373 374 if (pll->lock) 375 spin_lock_irqsave(pll->lock, flags); 376 377 _clk_pll_enable(hw); 378 379 ret = clk_pll_wait_for_lock(pll); 380 381 if (pll->lock) 382 spin_unlock_irqrestore(pll->lock, flags); 383 384 return ret; 385 } 386 387 static void clk_pll_disable(struct clk_hw *hw) 388 { 389 struct tegra_clk_pll *pll = to_clk_pll(hw); 390 unsigned long flags = 0; 391 392 if (pll->lock) 393 spin_lock_irqsave(pll->lock, flags); 394 395 _clk_pll_disable(hw); 396 397 if (pll->lock) 398 spin_unlock_irqrestore(pll->lock, flags); 399 } 400 401 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 402 { 403 struct tegra_clk_pll *pll = to_clk_pll(hw); 404 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 405 406 if (p_tohw) { 407 while (p_tohw->pdiv) { 408 if (p_div <= p_tohw->pdiv) 409 return p_tohw->hw_val; 410 p_tohw++; 411 } 412 return -EINVAL; 413 } 414 return -EINVAL; 415 } 416 417 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 418 { 419 struct tegra_clk_pll *pll = to_clk_pll(hw); 420 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 421 422 if (p_tohw) { 423 while (p_tohw->pdiv) { 424 if (p_div_hw == p_tohw->hw_val) 425 return p_tohw->pdiv; 426 p_tohw++; 427 } 428 return -EINVAL; 429 } 430 431 return 1 << p_div_hw; 432 } 433 434 static int _get_table_rate(struct clk_hw *hw, 435 struct tegra_clk_pll_freq_table *cfg, 436 unsigned long rate, unsigned long parent_rate) 437 { 438 struct tegra_clk_pll *pll = to_clk_pll(hw); 439 struct tegra_clk_pll_freq_table *sel; 440 int p; 441 442 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 443 if (sel->input_rate == parent_rate && 444 sel->output_rate == rate) 445 break; 446 447 if (sel->input_rate == 0) 448 return -EINVAL; 449 450 if (pll->params->pdiv_tohw) { 451 p = _p_div_to_hw(hw, sel->p); 452 if (p < 0) 453 return p; 454 } else { 455 p = ilog2(sel->p); 456 } 457 458 cfg->input_rate = sel->input_rate; 459 cfg->output_rate = sel->output_rate; 460 cfg->m = sel->m; 461 cfg->n = sel->n; 462 cfg->p = p; 463 cfg->cpcon = sel->cpcon; 464 cfg->sdm_data = sel->sdm_data; 465 466 return 0; 467 } 468 469 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 470 unsigned long rate, unsigned long parent_rate) 471 { 472 struct tegra_clk_pll *pll = to_clk_pll(hw); 473 unsigned long cfreq; 474 u32 p_div = 0; 475 int ret; 476 477 switch (parent_rate) { 478 case 12000000: 479 case 26000000: 480 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 481 break; 482 case 13000000: 483 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 484 break; 485 case 16800000: 486 case 19200000: 487 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 488 break; 489 case 9600000: 490 case 28800000: 491 /* 492 * PLL_P_OUT1 rate is not listed in PLLA table 493 */ 494 cfreq = parent_rate / (parent_rate / 1000000); 495 break; 496 default: 497 pr_err("%s Unexpected reference rate %lu\n", 498 __func__, parent_rate); 499 BUG(); 500 } 501 502 /* Raise VCO to guarantee 0.5% accuracy */ 503 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 504 cfg->output_rate <<= 1) 505 p_div++; 506 507 cfg->m = parent_rate / cfreq; 508 cfg->n = cfg->output_rate / cfreq; 509 cfg->cpcon = OUT_OF_TABLE_CPCON; 510 511 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 512 (1 << p_div) > divp_max(pll) 513 || cfg->output_rate > pll->params->vco_max) { 514 return -EINVAL; 515 } 516 517 cfg->output_rate >>= p_div; 518 519 if (pll->params->pdiv_tohw) { 520 ret = _p_div_to_hw(hw, 1 << p_div); 521 if (ret < 0) 522 return ret; 523 else 524 cfg->p = ret; 525 } else 526 cfg->p = p_div; 527 528 return 0; 529 } 530 531 /* 532 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number 533 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as 534 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used 535 * to indicate that SDM is disabled. 536 * 537 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 538 */ 539 static void clk_pll_set_sdm_data(struct clk_hw *hw, 540 struct tegra_clk_pll_freq_table *cfg) 541 { 542 struct tegra_clk_pll *pll = to_clk_pll(hw); 543 u32 val; 544 bool enabled; 545 546 if (!pll->params->sdm_din_reg) 547 return; 548 549 if (cfg->sdm_data) { 550 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); 551 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); 552 pll_writel_sdm_din(val, pll); 553 } 554 555 val = pll_readl_sdm_ctrl(pll); 556 enabled = (val & sdm_en_mask(pll)); 557 558 if (cfg->sdm_data == 0 && enabled) 559 val &= ~pll->params->sdm_ctrl_en_mask; 560 561 if (cfg->sdm_data != 0 && !enabled) 562 val |= pll->params->sdm_ctrl_en_mask; 563 564 pll_writel_sdm_ctrl(val, pll); 565 } 566 567 static void _update_pll_mnp(struct tegra_clk_pll *pll, 568 struct tegra_clk_pll_freq_table *cfg) 569 { 570 u32 val; 571 struct tegra_clk_pll_params *params = pll->params; 572 struct div_nmp *div_nmp = params->div_nmp; 573 574 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 575 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 576 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 577 val = pll_override_readl(params->pmc_divp_reg, pll); 578 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 579 val |= cfg->p << div_nmp->override_divp_shift; 580 pll_override_writel(val, params->pmc_divp_reg, pll); 581 582 val = pll_override_readl(params->pmc_divnm_reg, pll); 583 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | 584 ~(divn_mask(pll) << div_nmp->override_divn_shift); 585 val |= (cfg->m << div_nmp->override_divm_shift) | 586 (cfg->n << div_nmp->override_divn_shift); 587 pll_override_writel(val, params->pmc_divnm_reg, pll); 588 } else { 589 val = pll_readl_base(pll); 590 591 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 592 divp_mask_shifted(pll)); 593 594 val |= (cfg->m << divm_shift(pll)) | 595 (cfg->n << divn_shift(pll)) | 596 (cfg->p << divp_shift(pll)); 597 598 pll_writel_base(val, pll); 599 600 clk_pll_set_sdm_data(&pll->hw, cfg); 601 } 602 } 603 604 static void _get_pll_mnp(struct tegra_clk_pll *pll, 605 struct tegra_clk_pll_freq_table *cfg) 606 { 607 u32 val; 608 struct tegra_clk_pll_params *params = pll->params; 609 struct div_nmp *div_nmp = params->div_nmp; 610 611 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 612 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 613 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 614 val = pll_override_readl(params->pmc_divp_reg, pll); 615 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 616 617 val = pll_override_readl(params->pmc_divnm_reg, pll); 618 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 619 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 620 } else { 621 val = pll_readl_base(pll); 622 623 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 624 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 625 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 626 627 if (pll->params->sdm_din_reg) { 628 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { 629 val = pll_readl_sdm_din(pll); 630 val &= sdm_din_mask(pll); 631 cfg->sdm_data = sdin_din_to_data(val); 632 } 633 } 634 } 635 } 636 637 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 638 struct tegra_clk_pll_freq_table *cfg, 639 unsigned long rate) 640 { 641 u32 val; 642 643 val = pll_readl_misc(pll); 644 645 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 646 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 647 648 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 649 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 650 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 651 val |= 1 << PLL_MISC_LFCON_SHIFT; 652 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 653 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 654 if (rate >= (pll->params->vco_max >> 1)) 655 val |= 1 << PLL_MISC_DCCON_SHIFT; 656 } 657 658 pll_writel_misc(val, pll); 659 } 660 661 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 662 unsigned long rate) 663 { 664 struct tegra_clk_pll *pll = to_clk_pll(hw); 665 int state, ret = 0; 666 667 state = clk_pll_is_enabled(hw); 668 669 if (state) 670 _clk_pll_disable(hw); 671 672 _update_pll_mnp(pll, cfg); 673 674 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 675 _update_pll_cpcon(pll, cfg, rate); 676 677 if (state) { 678 _clk_pll_enable(hw); 679 ret = clk_pll_wait_for_lock(pll); 680 } 681 682 return ret; 683 } 684 685 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 686 unsigned long parent_rate) 687 { 688 struct tegra_clk_pll *pll = to_clk_pll(hw); 689 struct tegra_clk_pll_freq_table cfg, old_cfg; 690 unsigned long flags = 0; 691 int ret = 0; 692 693 if (pll->params->flags & TEGRA_PLL_FIXED) { 694 if (rate != pll->params->fixed_rate) { 695 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 696 __func__, clk_hw_get_name(hw), 697 pll->params->fixed_rate, rate); 698 return -EINVAL; 699 } 700 return 0; 701 } 702 703 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 704 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { 705 pr_err("%s: Failed to set %s rate %lu\n", __func__, 706 clk_hw_get_name(hw), rate); 707 WARN_ON(1); 708 return -EINVAL; 709 } 710 if (pll->lock) 711 spin_lock_irqsave(pll->lock, flags); 712 713 _get_pll_mnp(pll, &old_cfg); 714 715 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || 716 old_cfg.sdm_data != cfg.sdm_data) 717 ret = _program_pll(hw, &cfg, rate); 718 719 if (pll->lock) 720 spin_unlock_irqrestore(pll->lock, flags); 721 722 return ret; 723 } 724 725 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 726 unsigned long *prate) 727 { 728 struct tegra_clk_pll *pll = to_clk_pll(hw); 729 struct tegra_clk_pll_freq_table cfg; 730 731 if (pll->params->flags & TEGRA_PLL_FIXED) { 732 /* PLLM/MB are used for memory; we do not change rate */ 733 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) 734 return clk_hw_get_rate(hw); 735 return pll->params->fixed_rate; 736 } 737 738 if (_get_table_rate(hw, &cfg, rate, *prate) && 739 pll->params->calc_rate(hw, &cfg, rate, *prate)) 740 return -EINVAL; 741 742 return cfg.output_rate; 743 } 744 745 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 746 unsigned long parent_rate) 747 { 748 struct tegra_clk_pll *pll = to_clk_pll(hw); 749 struct tegra_clk_pll_freq_table cfg; 750 u32 val; 751 u64 rate = parent_rate; 752 int pdiv; 753 754 val = pll_readl_base(pll); 755 756 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 757 return parent_rate; 758 759 if ((pll->params->flags & TEGRA_PLL_FIXED) && 760 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 761 !(val & PLL_BASE_OVERRIDE)) { 762 struct tegra_clk_pll_freq_table sel; 763 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 764 parent_rate)) { 765 pr_err("Clock %s has unknown fixed frequency\n", 766 clk_hw_get_name(hw)); 767 BUG(); 768 } 769 return pll->params->fixed_rate; 770 } 771 772 _get_pll_mnp(pll, &cfg); 773 774 pdiv = _hw_to_p_div(hw, cfg.p); 775 if (pdiv < 0) { 776 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 777 __clk_get_name(hw->clk), cfg.p); 778 pdiv = 1; 779 } 780 781 if (pll->params->set_gain) 782 pll->params->set_gain(&cfg); 783 784 cfg.m *= pdiv; 785 786 rate *= cfg.n; 787 do_div(rate, cfg.m); 788 789 return rate; 790 } 791 792 static int clk_plle_training(struct tegra_clk_pll *pll) 793 { 794 u32 val; 795 unsigned long timeout; 796 797 if (!pll->pmc) 798 return -ENOSYS; 799 800 /* 801 * PLLE is already disabled, and setup cleared; 802 * create falling edge on PLLE IDDQ input. 803 */ 804 val = readl(pll->pmc + PMC_SATA_PWRGT); 805 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 806 writel(val, pll->pmc + PMC_SATA_PWRGT); 807 808 val = readl(pll->pmc + PMC_SATA_PWRGT); 809 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 810 writel(val, pll->pmc + PMC_SATA_PWRGT); 811 812 val = readl(pll->pmc + PMC_SATA_PWRGT); 813 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 814 writel(val, pll->pmc + PMC_SATA_PWRGT); 815 816 val = pll_readl_misc(pll); 817 818 timeout = jiffies + msecs_to_jiffies(100); 819 while (1) { 820 val = pll_readl_misc(pll); 821 if (val & PLLE_MISC_READY) 822 break; 823 if (time_after(jiffies, timeout)) { 824 pr_err("%s: timeout waiting for PLLE\n", __func__); 825 return -EBUSY; 826 } 827 udelay(300); 828 } 829 830 return 0; 831 } 832 833 static int clk_plle_enable(struct clk_hw *hw) 834 { 835 struct tegra_clk_pll *pll = to_clk_pll(hw); 836 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 837 struct tegra_clk_pll_freq_table sel; 838 u32 val; 839 int err; 840 841 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 842 return -EINVAL; 843 844 clk_pll_disable(hw); 845 846 val = pll_readl_misc(pll); 847 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 848 pll_writel_misc(val, pll); 849 850 val = pll_readl_misc(pll); 851 if (!(val & PLLE_MISC_READY)) { 852 err = clk_plle_training(pll); 853 if (err) 854 return err; 855 } 856 857 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 858 /* configure dividers */ 859 val = pll_readl_base(pll); 860 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 861 divm_mask_shifted(pll)); 862 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 863 val |= sel.m << divm_shift(pll); 864 val |= sel.n << divn_shift(pll); 865 val |= sel.p << divp_shift(pll); 866 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 867 pll_writel_base(val, pll); 868 } 869 870 val = pll_readl_misc(pll); 871 val |= PLLE_MISC_SETUP_VALUE; 872 val |= PLLE_MISC_LOCK_ENABLE; 873 pll_writel_misc(val, pll); 874 875 val = readl(pll->clk_base + PLLE_SS_CTRL); 876 val &= ~PLLE_SS_COEFFICIENTS_MASK; 877 val |= PLLE_SS_DISABLE; 878 writel(val, pll->clk_base + PLLE_SS_CTRL); 879 880 val = pll_readl_base(pll); 881 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 882 pll_writel_base(val, pll); 883 884 clk_pll_wait_for_lock(pll); 885 886 return 0; 887 } 888 889 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 890 unsigned long parent_rate) 891 { 892 struct tegra_clk_pll *pll = to_clk_pll(hw); 893 u32 val = pll_readl_base(pll); 894 u32 divn = 0, divm = 0, divp = 0; 895 u64 rate = parent_rate; 896 897 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 898 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 899 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 900 divm *= divp; 901 902 rate *= divn; 903 do_div(rate, divm); 904 return rate; 905 } 906 907 const struct clk_ops tegra_clk_pll_ops = { 908 .is_enabled = clk_pll_is_enabled, 909 .enable = clk_pll_enable, 910 .disable = clk_pll_disable, 911 .recalc_rate = clk_pll_recalc_rate, 912 .round_rate = clk_pll_round_rate, 913 .set_rate = clk_pll_set_rate, 914 }; 915 916 const struct clk_ops tegra_clk_plle_ops = { 917 .recalc_rate = clk_plle_recalc_rate, 918 .is_enabled = clk_pll_is_enabled, 919 .disable = clk_pll_disable, 920 .enable = clk_plle_enable, 921 }; 922 923 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 924 unsigned long parent_rate) 925 { 926 u16 mdiv = parent_rate / pll_params->cf_min; 927 928 if (pll_params->flags & TEGRA_MDIV_NEW) 929 return (!pll_params->mdiv_default ? mdiv : 930 min(mdiv, pll_params->mdiv_default)); 931 932 if (pll_params->mdiv_default) 933 return pll_params->mdiv_default; 934 935 if (parent_rate > pll_params->cf_max) 936 return 2; 937 else 938 return 1; 939 } 940 941 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 942 struct tegra_clk_pll_freq_table *cfg, 943 unsigned long rate, unsigned long parent_rate) 944 { 945 struct tegra_clk_pll *pll = to_clk_pll(hw); 946 unsigned int p; 947 int p_div; 948 949 if (!rate) 950 return -EINVAL; 951 952 p = DIV_ROUND_UP(pll->params->vco_min, rate); 953 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 954 cfg->output_rate = rate * p; 955 cfg->n = cfg->output_rate * cfg->m / parent_rate; 956 cfg->input_rate = parent_rate; 957 958 p_div = _p_div_to_hw(hw, p); 959 if (p_div < 0) 960 return p_div; 961 962 cfg->p = p_div; 963 964 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 965 return -EINVAL; 966 967 return 0; 968 } 969 970 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 971 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 972 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 973 defined(CONFIG_ARCH_TEGRA_210_SOC) 974 975 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) 976 { 977 struct tegra_clk_pll *pll = to_clk_pll(hw); 978 979 return (u16)_pll_fixed_mdiv(pll->params, input_rate); 980 } 981 982 static unsigned long _clip_vco_min(unsigned long vco_min, 983 unsigned long parent_rate) 984 { 985 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 986 } 987 988 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 989 void __iomem *clk_base, 990 unsigned long parent_rate) 991 { 992 u32 val; 993 u32 step_a, step_b; 994 995 switch (parent_rate) { 996 case 12000000: 997 case 13000000: 998 case 26000000: 999 step_a = 0x2B; 1000 step_b = 0x0B; 1001 break; 1002 case 16800000: 1003 step_a = 0x1A; 1004 step_b = 0x09; 1005 break; 1006 case 19200000: 1007 step_a = 0x12; 1008 step_b = 0x08; 1009 break; 1010 default: 1011 pr_err("%s: Unexpected reference rate %lu\n", 1012 __func__, parent_rate); 1013 WARN_ON(1); 1014 return -EINVAL; 1015 } 1016 1017 val = step_a << pll_params->stepa_shift; 1018 val |= step_b << pll_params->stepb_shift; 1019 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1020 1021 return 0; 1022 } 1023 1024 static int _pll_ramp_calc_pll(struct clk_hw *hw, 1025 struct tegra_clk_pll_freq_table *cfg, 1026 unsigned long rate, unsigned long parent_rate) 1027 { 1028 struct tegra_clk_pll *pll = to_clk_pll(hw); 1029 int err = 0; 1030 1031 err = _get_table_rate(hw, cfg, rate, parent_rate); 1032 if (err < 0) 1033 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 1034 else { 1035 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 1036 WARN_ON(1); 1037 err = -EINVAL; 1038 goto out; 1039 } 1040 } 1041 1042 if (cfg->p > pll->params->max_p) 1043 err = -EINVAL; 1044 1045 out: 1046 return err; 1047 } 1048 1049 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 1050 unsigned long parent_rate) 1051 { 1052 struct tegra_clk_pll *pll = to_clk_pll(hw); 1053 struct tegra_clk_pll_freq_table cfg, old_cfg; 1054 unsigned long flags = 0; 1055 int ret; 1056 1057 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1058 if (ret < 0) 1059 return ret; 1060 1061 if (pll->lock) 1062 spin_lock_irqsave(pll->lock, flags); 1063 1064 _get_pll_mnp(pll, &old_cfg); 1065 1066 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1067 ret = _program_pll(hw, &cfg, rate); 1068 1069 if (pll->lock) 1070 spin_unlock_irqrestore(pll->lock, flags); 1071 1072 return ret; 1073 } 1074 1075 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 1076 unsigned long *prate) 1077 { 1078 struct tegra_clk_pll *pll = to_clk_pll(hw); 1079 struct tegra_clk_pll_freq_table cfg; 1080 int ret, p_div; 1081 u64 output_rate = *prate; 1082 1083 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1084 if (ret < 0) 1085 return ret; 1086 1087 p_div = _hw_to_p_div(hw, cfg.p); 1088 if (p_div < 0) 1089 return p_div; 1090 1091 if (pll->params->set_gain) 1092 pll->params->set_gain(&cfg); 1093 1094 output_rate *= cfg.n; 1095 do_div(output_rate, cfg.m * p_div); 1096 1097 return output_rate; 1098 } 1099 1100 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1101 { 1102 u32 val; 1103 1104 val = pll_readl_misc(pll); 1105 val |= PLLCX_MISC_STROBE; 1106 pll_writel_misc(val, pll); 1107 udelay(2); 1108 1109 val &= ~PLLCX_MISC_STROBE; 1110 pll_writel_misc(val, pll); 1111 } 1112 1113 static int clk_pllc_enable(struct clk_hw *hw) 1114 { 1115 struct tegra_clk_pll *pll = to_clk_pll(hw); 1116 u32 val; 1117 int ret; 1118 unsigned long flags = 0; 1119 1120 if (pll->lock) 1121 spin_lock_irqsave(pll->lock, flags); 1122 1123 _clk_pll_enable(hw); 1124 udelay(2); 1125 1126 val = pll_readl_misc(pll); 1127 val &= ~PLLCX_MISC_RESET; 1128 pll_writel_misc(val, pll); 1129 udelay(2); 1130 1131 _pllcx_strobe(pll); 1132 1133 ret = clk_pll_wait_for_lock(pll); 1134 1135 if (pll->lock) 1136 spin_unlock_irqrestore(pll->lock, flags); 1137 1138 return ret; 1139 } 1140 1141 static void _clk_pllc_disable(struct clk_hw *hw) 1142 { 1143 struct tegra_clk_pll *pll = to_clk_pll(hw); 1144 u32 val; 1145 1146 _clk_pll_disable(hw); 1147 1148 val = pll_readl_misc(pll); 1149 val |= PLLCX_MISC_RESET; 1150 pll_writel_misc(val, pll); 1151 udelay(2); 1152 } 1153 1154 static void clk_pllc_disable(struct clk_hw *hw) 1155 { 1156 struct tegra_clk_pll *pll = to_clk_pll(hw); 1157 unsigned long flags = 0; 1158 1159 if (pll->lock) 1160 spin_lock_irqsave(pll->lock, flags); 1161 1162 _clk_pllc_disable(hw); 1163 1164 if (pll->lock) 1165 spin_unlock_irqrestore(pll->lock, flags); 1166 } 1167 1168 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1169 unsigned long input_rate, u32 n) 1170 { 1171 u32 val, n_threshold; 1172 1173 switch (input_rate) { 1174 case 12000000: 1175 n_threshold = 70; 1176 break; 1177 case 13000000: 1178 case 26000000: 1179 n_threshold = 71; 1180 break; 1181 case 16800000: 1182 n_threshold = 55; 1183 break; 1184 case 19200000: 1185 n_threshold = 48; 1186 break; 1187 default: 1188 pr_err("%s: Unexpected reference rate %lu\n", 1189 __func__, input_rate); 1190 return -EINVAL; 1191 } 1192 1193 val = pll_readl_misc(pll); 1194 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1195 val |= n <= n_threshold ? 1196 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1197 pll_writel_misc(val, pll); 1198 1199 return 0; 1200 } 1201 1202 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1203 unsigned long parent_rate) 1204 { 1205 struct tegra_clk_pll_freq_table cfg, old_cfg; 1206 struct tegra_clk_pll *pll = to_clk_pll(hw); 1207 unsigned long flags = 0; 1208 int state, ret = 0; 1209 1210 if (pll->lock) 1211 spin_lock_irqsave(pll->lock, flags); 1212 1213 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1214 if (ret < 0) 1215 goto out; 1216 1217 _get_pll_mnp(pll, &old_cfg); 1218 1219 if (cfg.m != old_cfg.m) { 1220 WARN_ON(1); 1221 goto out; 1222 } 1223 1224 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1225 goto out; 1226 1227 state = clk_pll_is_enabled(hw); 1228 if (state) 1229 _clk_pllc_disable(hw); 1230 1231 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1232 if (ret < 0) 1233 goto out; 1234 1235 _update_pll_mnp(pll, &cfg); 1236 1237 if (state) 1238 ret = clk_pllc_enable(hw); 1239 1240 out: 1241 if (pll->lock) 1242 spin_unlock_irqrestore(pll->lock, flags); 1243 1244 return ret; 1245 } 1246 1247 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1248 struct tegra_clk_pll_freq_table *cfg, 1249 unsigned long rate, unsigned long parent_rate) 1250 { 1251 u16 m, n; 1252 u64 output_rate = parent_rate; 1253 1254 m = _pll_fixed_mdiv(pll->params, parent_rate); 1255 n = rate * m / parent_rate; 1256 1257 output_rate *= n; 1258 do_div(output_rate, m); 1259 1260 if (cfg) { 1261 cfg->m = m; 1262 cfg->n = n; 1263 } 1264 1265 return output_rate; 1266 } 1267 1268 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1269 unsigned long parent_rate) 1270 { 1271 struct tegra_clk_pll_freq_table cfg, old_cfg; 1272 struct tegra_clk_pll *pll = to_clk_pll(hw); 1273 unsigned long flags = 0; 1274 int state, ret = 0; 1275 1276 if (pll->lock) 1277 spin_lock_irqsave(pll->lock, flags); 1278 1279 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1280 _get_pll_mnp(pll, &old_cfg); 1281 cfg.p = old_cfg.p; 1282 1283 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1284 state = clk_pll_is_enabled(hw); 1285 if (state) 1286 _clk_pll_disable(hw); 1287 1288 _update_pll_mnp(pll, &cfg); 1289 1290 if (state) { 1291 _clk_pll_enable(hw); 1292 ret = clk_pll_wait_for_lock(pll); 1293 } 1294 } 1295 1296 if (pll->lock) 1297 spin_unlock_irqrestore(pll->lock, flags); 1298 1299 return ret; 1300 } 1301 1302 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1303 unsigned long parent_rate) 1304 { 1305 struct tegra_clk_pll_freq_table cfg; 1306 struct tegra_clk_pll *pll = to_clk_pll(hw); 1307 u64 rate = parent_rate; 1308 1309 _get_pll_mnp(pll, &cfg); 1310 1311 rate *= cfg.n; 1312 do_div(rate, cfg.m); 1313 1314 return rate; 1315 } 1316 1317 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1318 unsigned long *prate) 1319 { 1320 struct tegra_clk_pll *pll = to_clk_pll(hw); 1321 1322 return _pllre_calc_rate(pll, NULL, rate, *prate); 1323 } 1324 1325 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1326 { 1327 struct tegra_clk_pll *pll = to_clk_pll(hw); 1328 struct tegra_clk_pll_freq_table sel; 1329 u32 val; 1330 int ret; 1331 unsigned long flags = 0; 1332 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1333 1334 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1335 return -EINVAL; 1336 1337 if (pll->lock) 1338 spin_lock_irqsave(pll->lock, flags); 1339 1340 val = pll_readl_base(pll); 1341 val &= ~BIT(29); /* Disable lock override */ 1342 pll_writel_base(val, pll); 1343 1344 val = pll_readl(pll->params->aux_reg, pll); 1345 val |= PLLE_AUX_ENABLE_SWCTL; 1346 val &= ~PLLE_AUX_SEQ_ENABLE; 1347 pll_writel(val, pll->params->aux_reg, pll); 1348 udelay(1); 1349 1350 val = pll_readl_misc(pll); 1351 val |= PLLE_MISC_LOCK_ENABLE; 1352 val |= PLLE_MISC_IDDQ_SW_CTRL; 1353 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1354 val |= PLLE_MISC_PLLE_PTS; 1355 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1356 pll_writel_misc(val, pll); 1357 udelay(5); 1358 1359 val = pll_readl(PLLE_SS_CTRL, pll); 1360 val |= PLLE_SS_DISABLE; 1361 pll_writel(val, PLLE_SS_CTRL, pll); 1362 1363 val = pll_readl_base(pll); 1364 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1365 divm_mask_shifted(pll)); 1366 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1367 val |= sel.m << divm_shift(pll); 1368 val |= sel.n << divn_shift(pll); 1369 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1370 pll_writel_base(val, pll); 1371 udelay(1); 1372 1373 _clk_pll_enable(hw); 1374 ret = clk_pll_wait_for_lock(pll); 1375 1376 if (ret < 0) 1377 goto out; 1378 1379 val = pll_readl(PLLE_SS_CTRL, pll); 1380 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1381 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1382 val |= PLLE_SS_COEFFICIENTS_VAL; 1383 pll_writel(val, PLLE_SS_CTRL, pll); 1384 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1385 pll_writel(val, PLLE_SS_CTRL, pll); 1386 udelay(1); 1387 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1388 pll_writel(val, PLLE_SS_CTRL, pll); 1389 udelay(1); 1390 1391 /* Enable hw control of xusb brick pll */ 1392 val = pll_readl_misc(pll); 1393 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1394 pll_writel_misc(val, pll); 1395 1396 val = pll_readl(pll->params->aux_reg, pll); 1397 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1398 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1399 pll_writel(val, pll->params->aux_reg, pll); 1400 udelay(1); 1401 val |= PLLE_AUX_SEQ_ENABLE; 1402 pll_writel(val, pll->params->aux_reg, pll); 1403 1404 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1405 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1406 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1407 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1408 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1409 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1410 udelay(1); 1411 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1412 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1413 1414 /* Enable hw control of SATA pll */ 1415 val = pll_readl(SATA_PLL_CFG0, pll); 1416 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1417 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1418 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1419 pll_writel(val, SATA_PLL_CFG0, pll); 1420 1421 udelay(1); 1422 1423 val = pll_readl(SATA_PLL_CFG0, pll); 1424 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1425 pll_writel(val, SATA_PLL_CFG0, pll); 1426 1427 out: 1428 if (pll->lock) 1429 spin_unlock_irqrestore(pll->lock, flags); 1430 1431 return ret; 1432 } 1433 1434 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1435 { 1436 struct tegra_clk_pll *pll = to_clk_pll(hw); 1437 unsigned long flags = 0; 1438 u32 val; 1439 1440 if (pll->lock) 1441 spin_lock_irqsave(pll->lock, flags); 1442 1443 _clk_pll_disable(hw); 1444 1445 val = pll_readl_misc(pll); 1446 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1447 pll_writel_misc(val, pll); 1448 udelay(1); 1449 1450 if (pll->lock) 1451 spin_unlock_irqrestore(pll->lock, flags); 1452 } 1453 #endif 1454 1455 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1456 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1457 spinlock_t *lock) 1458 { 1459 struct tegra_clk_pll *pll; 1460 1461 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1462 if (!pll) 1463 return ERR_PTR(-ENOMEM); 1464 1465 pll->clk_base = clk_base; 1466 pll->pmc = pmc; 1467 1468 pll->params = pll_params; 1469 pll->lock = lock; 1470 1471 if (!pll_params->div_nmp) 1472 pll_params->div_nmp = &default_nmp; 1473 1474 return pll; 1475 } 1476 1477 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1478 const char *name, const char *parent_name, unsigned long flags, 1479 const struct clk_ops *ops) 1480 { 1481 struct clk_init_data init; 1482 1483 init.name = name; 1484 init.ops = ops; 1485 init.flags = flags; 1486 init.parent_names = (parent_name ? &parent_name : NULL); 1487 init.num_parents = (parent_name ? 1 : 0); 1488 1489 /* Default to _calc_rate if unspecified */ 1490 if (!pll->params->calc_rate) { 1491 if (pll->params->flags & TEGRA_PLLM) 1492 pll->params->calc_rate = _calc_dynamic_ramp_rate; 1493 else 1494 pll->params->calc_rate = _calc_rate; 1495 } 1496 1497 /* Data in .init is copied by clk_register(), so stack variable OK */ 1498 pll->hw.init = &init; 1499 1500 return clk_register(NULL, &pll->hw); 1501 } 1502 1503 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1504 void __iomem *clk_base, void __iomem *pmc, 1505 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1506 spinlock_t *lock) 1507 { 1508 struct tegra_clk_pll *pll; 1509 struct clk *clk; 1510 1511 pll_params->flags |= TEGRA_PLL_BYPASS; 1512 1513 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1514 if (IS_ERR(pll)) 1515 return ERR_CAST(pll); 1516 1517 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1518 &tegra_clk_pll_ops); 1519 if (IS_ERR(clk)) 1520 kfree(pll); 1521 1522 return clk; 1523 } 1524 1525 static struct div_nmp pll_e_nmp = { 1526 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1527 .divn_width = PLLE_BASE_DIVN_WIDTH, 1528 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1529 .divm_width = PLLE_BASE_DIVM_WIDTH, 1530 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1531 .divp_width = PLLE_BASE_DIVP_WIDTH, 1532 }; 1533 1534 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1535 void __iomem *clk_base, void __iomem *pmc, 1536 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1537 spinlock_t *lock) 1538 { 1539 struct tegra_clk_pll *pll; 1540 struct clk *clk; 1541 1542 pll_params->flags |= TEGRA_PLL_BYPASS; 1543 1544 if (!pll_params->div_nmp) 1545 pll_params->div_nmp = &pll_e_nmp; 1546 1547 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1548 if (IS_ERR(pll)) 1549 return ERR_CAST(pll); 1550 1551 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1552 &tegra_clk_plle_ops); 1553 if (IS_ERR(clk)) 1554 kfree(pll); 1555 1556 return clk; 1557 } 1558 1559 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1560 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1561 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1562 defined(CONFIG_ARCH_TEGRA_210_SOC) 1563 static const struct clk_ops tegra_clk_pllxc_ops = { 1564 .is_enabled = clk_pll_is_enabled, 1565 .enable = clk_pll_enable, 1566 .disable = clk_pll_disable, 1567 .recalc_rate = clk_pll_recalc_rate, 1568 .round_rate = clk_pll_ramp_round_rate, 1569 .set_rate = clk_pllxc_set_rate, 1570 }; 1571 1572 static const struct clk_ops tegra_clk_pllc_ops = { 1573 .is_enabled = clk_pll_is_enabled, 1574 .enable = clk_pllc_enable, 1575 .disable = clk_pllc_disable, 1576 .recalc_rate = clk_pll_recalc_rate, 1577 .round_rate = clk_pll_ramp_round_rate, 1578 .set_rate = clk_pllc_set_rate, 1579 }; 1580 1581 static const struct clk_ops tegra_clk_pllre_ops = { 1582 .is_enabled = clk_pll_is_enabled, 1583 .enable = clk_pll_enable, 1584 .disable = clk_pll_disable, 1585 .recalc_rate = clk_pllre_recalc_rate, 1586 .round_rate = clk_pllre_round_rate, 1587 .set_rate = clk_pllre_set_rate, 1588 }; 1589 1590 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1591 .is_enabled = clk_pll_is_enabled, 1592 .enable = clk_plle_tegra114_enable, 1593 .disable = clk_plle_tegra114_disable, 1594 .recalc_rate = clk_pll_recalc_rate, 1595 }; 1596 1597 1598 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1599 void __iomem *clk_base, void __iomem *pmc, 1600 unsigned long flags, 1601 struct tegra_clk_pll_params *pll_params, 1602 spinlock_t *lock) 1603 { 1604 struct tegra_clk_pll *pll; 1605 struct clk *clk, *parent; 1606 unsigned long parent_rate; 1607 int err; 1608 u32 val, val_iddq; 1609 1610 parent = __clk_lookup(parent_name); 1611 if (!parent) { 1612 WARN(1, "parent clk %s of %s must be registered first\n", 1613 parent_name, name); 1614 return ERR_PTR(-EINVAL); 1615 } 1616 1617 if (!pll_params->pdiv_tohw) 1618 return ERR_PTR(-EINVAL); 1619 1620 parent_rate = clk_get_rate(parent); 1621 1622 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1623 1624 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1625 if (err) 1626 return ERR_PTR(err); 1627 1628 val = readl_relaxed(clk_base + pll_params->base_reg); 1629 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1630 1631 if (val & PLL_BASE_ENABLE) 1632 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1633 else { 1634 val_iddq |= BIT(pll_params->iddq_bit_idx); 1635 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1636 } 1637 1638 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1639 if (IS_ERR(pll)) 1640 return ERR_CAST(pll); 1641 1642 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1643 &tegra_clk_pllxc_ops); 1644 if (IS_ERR(clk)) 1645 kfree(pll); 1646 1647 return clk; 1648 } 1649 1650 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1651 void __iomem *clk_base, void __iomem *pmc, 1652 unsigned long flags, 1653 struct tegra_clk_pll_params *pll_params, 1654 spinlock_t *lock, unsigned long parent_rate) 1655 { 1656 u32 val; 1657 struct tegra_clk_pll *pll; 1658 struct clk *clk; 1659 1660 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1661 1662 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1663 if (IS_ERR(pll)) 1664 return ERR_CAST(pll); 1665 1666 /* program minimum rate by default */ 1667 1668 val = pll_readl_base(pll); 1669 if (val & PLL_BASE_ENABLE) 1670 WARN_ON(val & pll_params->iddq_bit_idx); 1671 else { 1672 int m; 1673 1674 m = _pll_fixed_mdiv(pll_params, parent_rate); 1675 val = m << divm_shift(pll); 1676 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 1677 pll_writel_base(val, pll); 1678 } 1679 1680 /* disable lock override */ 1681 1682 val = pll_readl_misc(pll); 1683 val &= ~BIT(29); 1684 pll_writel_misc(val, pll); 1685 1686 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1687 &tegra_clk_pllre_ops); 1688 if (IS_ERR(clk)) 1689 kfree(pll); 1690 1691 return clk; 1692 } 1693 1694 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1695 void __iomem *clk_base, void __iomem *pmc, 1696 unsigned long flags, 1697 struct tegra_clk_pll_params *pll_params, 1698 spinlock_t *lock) 1699 { 1700 struct tegra_clk_pll *pll; 1701 struct clk *clk, *parent; 1702 unsigned long parent_rate; 1703 1704 if (!pll_params->pdiv_tohw) 1705 return ERR_PTR(-EINVAL); 1706 1707 parent = __clk_lookup(parent_name); 1708 if (!parent) { 1709 WARN(1, "parent clk %s of %s must be registered first\n", 1710 parent_name, name); 1711 return ERR_PTR(-EINVAL); 1712 } 1713 1714 parent_rate = clk_get_rate(parent); 1715 1716 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1717 1718 pll_params->flags |= TEGRA_PLL_BYPASS; 1719 pll_params->flags |= TEGRA_PLLM; 1720 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1721 if (IS_ERR(pll)) 1722 return ERR_CAST(pll); 1723 1724 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1725 &tegra_clk_pll_ops); 1726 if (IS_ERR(clk)) 1727 kfree(pll); 1728 1729 return clk; 1730 } 1731 1732 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1733 void __iomem *clk_base, void __iomem *pmc, 1734 unsigned long flags, 1735 struct tegra_clk_pll_params *pll_params, 1736 spinlock_t *lock) 1737 { 1738 struct clk *parent, *clk; 1739 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1740 struct tegra_clk_pll *pll; 1741 struct tegra_clk_pll_freq_table cfg; 1742 unsigned long parent_rate; 1743 1744 if (!p_tohw) 1745 return ERR_PTR(-EINVAL); 1746 1747 parent = __clk_lookup(parent_name); 1748 if (!parent) { 1749 WARN(1, "parent clk %s of %s must be registered first\n", 1750 parent_name, name); 1751 return ERR_PTR(-EINVAL); 1752 } 1753 1754 parent_rate = clk_get_rate(parent); 1755 1756 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1757 1758 pll_params->flags |= TEGRA_PLL_BYPASS; 1759 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1760 if (IS_ERR(pll)) 1761 return ERR_CAST(pll); 1762 1763 /* 1764 * Most of PLLC register fields are shadowed, and can not be read 1765 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1766 * Initialize PLL to default state: disabled, reset; shadow registers 1767 * loaded with default parameters; dividers are preset for half of 1768 * minimum VCO rate (the latter assured that shadowed divider settings 1769 * are within supported range). 1770 */ 1771 1772 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1773 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1774 1775 while (p_tohw->pdiv) { 1776 if (p_tohw->pdiv == 2) { 1777 cfg.p = p_tohw->hw_val; 1778 break; 1779 } 1780 p_tohw++; 1781 } 1782 1783 if (!p_tohw->pdiv) { 1784 WARN_ON(1); 1785 return ERR_PTR(-EINVAL); 1786 } 1787 1788 pll_writel_base(0, pll); 1789 _update_pll_mnp(pll, &cfg); 1790 1791 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1792 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1793 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1794 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1795 1796 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1797 1798 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1799 &tegra_clk_pllc_ops); 1800 if (IS_ERR(clk)) 1801 kfree(pll); 1802 1803 return clk; 1804 } 1805 1806 struct clk *tegra_clk_register_plle_tegra114(const char *name, 1807 const char *parent_name, 1808 void __iomem *clk_base, unsigned long flags, 1809 struct tegra_clk_pll_params *pll_params, 1810 spinlock_t *lock) 1811 { 1812 struct tegra_clk_pll *pll; 1813 struct clk *clk; 1814 u32 val, val_aux; 1815 1816 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1817 if (IS_ERR(pll)) 1818 return ERR_CAST(pll); 1819 1820 /* ensure parent is set to pll_re_vco */ 1821 1822 val = pll_readl_base(pll); 1823 val_aux = pll_readl(pll_params->aux_reg, pll); 1824 1825 if (val & PLL_BASE_ENABLE) { 1826 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1827 (val_aux & PLLE_AUX_PLLP_SEL)) 1828 WARN(1, "pll_e enabled with unsupported parent %s\n", 1829 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1830 "pll_re_vco"); 1831 } else { 1832 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1833 pll_writel(val_aux, pll_params->aux_reg, pll); 1834 } 1835 1836 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1837 &tegra_clk_plle_tegra114_ops); 1838 if (IS_ERR(clk)) 1839 kfree(pll); 1840 1841 return clk; 1842 } 1843 #endif 1844 1845 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 1846 static const struct clk_ops tegra_clk_pllss_ops = { 1847 .is_enabled = clk_pll_is_enabled, 1848 .enable = clk_pll_enable, 1849 .disable = clk_pll_disable, 1850 .recalc_rate = clk_pll_recalc_rate, 1851 .round_rate = clk_pll_ramp_round_rate, 1852 .set_rate = clk_pllxc_set_rate, 1853 }; 1854 1855 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 1856 void __iomem *clk_base, unsigned long flags, 1857 struct tegra_clk_pll_params *pll_params, 1858 spinlock_t *lock) 1859 { 1860 struct tegra_clk_pll *pll; 1861 struct clk *clk, *parent; 1862 struct tegra_clk_pll_freq_table cfg; 1863 unsigned long parent_rate; 1864 u32 val; 1865 int i; 1866 1867 if (!pll_params->div_nmp) 1868 return ERR_PTR(-EINVAL); 1869 1870 parent = __clk_lookup(parent_name); 1871 if (!parent) { 1872 WARN(1, "parent clk %s of %s must be registered first\n", 1873 parent_name, name); 1874 return ERR_PTR(-EINVAL); 1875 } 1876 1877 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1878 if (IS_ERR(pll)) 1879 return ERR_CAST(pll); 1880 1881 val = pll_readl_base(pll); 1882 val &= ~PLLSS_REF_SRC_SEL_MASK; 1883 pll_writel_base(val, pll); 1884 1885 parent_rate = clk_get_rate(parent); 1886 1887 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1888 1889 /* initialize PLL to minimum rate */ 1890 1891 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1892 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1893 1894 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 1895 ; 1896 if (!i) { 1897 kfree(pll); 1898 return ERR_PTR(-EINVAL); 1899 } 1900 1901 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 1902 1903 _update_pll_mnp(pll, &cfg); 1904 1905 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 1906 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 1907 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 1908 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1909 1910 val = pll_readl_base(pll); 1911 if (val & PLL_BASE_ENABLE) { 1912 if (val & BIT(pll_params->iddq_bit_idx)) { 1913 WARN(1, "%s is on but IDDQ set\n", name); 1914 kfree(pll); 1915 return ERR_PTR(-EINVAL); 1916 } 1917 } else 1918 val |= BIT(pll_params->iddq_bit_idx); 1919 1920 val &= ~PLLSS_LOCK_OVERRIDE; 1921 pll_writel_base(val, pll); 1922 1923 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1924 &tegra_clk_pllss_ops); 1925 1926 if (IS_ERR(clk)) 1927 kfree(pll); 1928 1929 return clk; 1930 } 1931 #endif 1932 1933 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 1934 static int clk_plle_tegra210_enable(struct clk_hw *hw) 1935 { 1936 struct tegra_clk_pll *pll = to_clk_pll(hw); 1937 struct tegra_clk_pll_freq_table sel; 1938 u32 val; 1939 int ret; 1940 unsigned long flags = 0; 1941 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1942 1943 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1944 return -EINVAL; 1945 1946 if (pll->lock) 1947 spin_lock_irqsave(pll->lock, flags); 1948 1949 val = pll_readl_base(pll); 1950 val &= ~BIT(30); /* Disable lock override */ 1951 pll_writel_base(val, pll); 1952 1953 val = pll_readl(pll->params->aux_reg, pll); 1954 val |= PLLE_AUX_ENABLE_SWCTL; 1955 val &= ~PLLE_AUX_SEQ_ENABLE; 1956 pll_writel(val, pll->params->aux_reg, pll); 1957 udelay(1); 1958 1959 val = pll_readl_misc(pll); 1960 val |= PLLE_MISC_LOCK_ENABLE; 1961 val |= PLLE_MISC_IDDQ_SW_CTRL; 1962 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1963 val |= PLLE_MISC_PLLE_PTS; 1964 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1965 pll_writel_misc(val, pll); 1966 udelay(5); 1967 1968 val = pll_readl(PLLE_SS_CTRL, pll); 1969 val |= PLLE_SS_DISABLE; 1970 pll_writel(val, PLLE_SS_CTRL, pll); 1971 1972 val = pll_readl_base(pll); 1973 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1974 divm_mask_shifted(pll)); 1975 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1976 val |= sel.m << divm_shift(pll); 1977 val |= sel.n << divn_shift(pll); 1978 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1979 pll_writel_base(val, pll); 1980 udelay(1); 1981 1982 val = pll_readl_base(pll); 1983 val |= PLLE_BASE_ENABLE; 1984 pll_writel_base(val, pll); 1985 1986 ret = clk_pll_wait_for_lock(pll); 1987 1988 if (ret < 0) 1989 goto out; 1990 1991 val = pll_readl(PLLE_SS_CTRL, pll); 1992 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1993 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1994 val |= PLLE_SS_COEFFICIENTS_VAL; 1995 pll_writel(val, PLLE_SS_CTRL, pll); 1996 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1997 pll_writel(val, PLLE_SS_CTRL, pll); 1998 udelay(1); 1999 val &= ~PLLE_SS_CNTL_INTERP_RESET; 2000 pll_writel(val, PLLE_SS_CTRL, pll); 2001 udelay(1); 2002 2003 val = pll_readl_misc(pll); 2004 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 2005 pll_writel_misc(val, pll); 2006 2007 val = pll_readl(pll->params->aux_reg, pll); 2008 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); 2009 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 2010 pll_writel(val, pll->params->aux_reg, pll); 2011 udelay(1); 2012 val |= PLLE_AUX_SEQ_ENABLE; 2013 pll_writel(val, pll->params->aux_reg, pll); 2014 2015 out: 2016 if (pll->lock) 2017 spin_unlock_irqrestore(pll->lock, flags); 2018 2019 return ret; 2020 } 2021 2022 static void clk_plle_tegra210_disable(struct clk_hw *hw) 2023 { 2024 struct tegra_clk_pll *pll = to_clk_pll(hw); 2025 unsigned long flags = 0; 2026 u32 val; 2027 2028 if (pll->lock) 2029 spin_lock_irqsave(pll->lock, flags); 2030 2031 val = pll_readl_base(pll); 2032 val &= ~PLLE_BASE_ENABLE; 2033 pll_writel_base(val, pll); 2034 2035 val = pll_readl_misc(pll); 2036 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 2037 pll_writel_misc(val, pll); 2038 udelay(1); 2039 2040 if (pll->lock) 2041 spin_unlock_irqrestore(pll->lock, flags); 2042 } 2043 2044 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw) 2045 { 2046 struct tegra_clk_pll *pll = to_clk_pll(hw); 2047 u32 val; 2048 2049 val = pll_readl_base(pll); 2050 2051 return val & PLLE_BASE_ENABLE ? 1 : 0; 2052 } 2053 2054 static const struct clk_ops tegra_clk_plle_tegra210_ops = { 2055 .is_enabled = clk_plle_tegra210_is_enabled, 2056 .enable = clk_plle_tegra210_enable, 2057 .disable = clk_plle_tegra210_disable, 2058 .recalc_rate = clk_pll_recalc_rate, 2059 }; 2060 2061 struct clk *tegra_clk_register_plle_tegra210(const char *name, 2062 const char *parent_name, 2063 void __iomem *clk_base, unsigned long flags, 2064 struct tegra_clk_pll_params *pll_params, 2065 spinlock_t *lock) 2066 { 2067 struct tegra_clk_pll *pll; 2068 struct clk *clk; 2069 u32 val, val_aux; 2070 2071 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2072 if (IS_ERR(pll)) 2073 return ERR_CAST(pll); 2074 2075 /* ensure parent is set to pll_re_vco */ 2076 2077 val = pll_readl_base(pll); 2078 val_aux = pll_readl(pll_params->aux_reg, pll); 2079 2080 if (val & PLLE_BASE_ENABLE) { 2081 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 2082 (val_aux & PLLE_AUX_PLLP_SEL)) 2083 WARN(1, "pll_e enabled with unsupported parent %s\n", 2084 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 2085 "pll_re_vco"); 2086 } else { 2087 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 2088 pll_writel(val_aux, pll_params->aux_reg, pll); 2089 } 2090 2091 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2092 &tegra_clk_plle_tegra210_ops); 2093 if (IS_ERR(clk)) 2094 kfree(pll); 2095 2096 return clk; 2097 } 2098 2099 struct clk *tegra_clk_register_pllc_tegra210(const char *name, 2100 const char *parent_name, void __iomem *clk_base, 2101 void __iomem *pmc, unsigned long flags, 2102 struct tegra_clk_pll_params *pll_params, 2103 spinlock_t *lock) 2104 { 2105 struct clk *parent, *clk; 2106 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 2107 struct tegra_clk_pll *pll; 2108 unsigned long parent_rate; 2109 2110 if (!p_tohw) 2111 return ERR_PTR(-EINVAL); 2112 2113 parent = __clk_lookup(parent_name); 2114 if (!parent) { 2115 WARN(1, "parent clk %s of %s must be registered first\n", 2116 name, parent_name); 2117 return ERR_PTR(-EINVAL); 2118 } 2119 2120 parent_rate = clk_get_rate(parent); 2121 2122 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2123 2124 pll_params->flags |= TEGRA_PLL_BYPASS; 2125 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2126 if (IS_ERR(pll)) 2127 return ERR_CAST(pll); 2128 2129 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2130 &tegra_clk_pll_ops); 2131 if (IS_ERR(clk)) 2132 kfree(pll); 2133 2134 return clk; 2135 } 2136 2137 struct clk *tegra_clk_register_pllxc_tegra210(const char *name, 2138 const char *parent_name, void __iomem *clk_base, 2139 void __iomem *pmc, unsigned long flags, 2140 struct tegra_clk_pll_params *pll_params, 2141 spinlock_t *lock) 2142 { 2143 struct tegra_clk_pll *pll; 2144 struct clk *clk, *parent; 2145 unsigned long parent_rate; 2146 2147 parent = __clk_lookup(parent_name); 2148 if (!parent) { 2149 WARN(1, "parent clk %s of %s must be registered first\n", 2150 name, parent_name); 2151 return ERR_PTR(-EINVAL); 2152 } 2153 2154 if (!pll_params->pdiv_tohw) 2155 return ERR_PTR(-EINVAL); 2156 2157 parent_rate = clk_get_rate(parent); 2158 2159 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2160 2161 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2162 if (IS_ERR(pll)) 2163 return ERR_CAST(pll); 2164 2165 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2166 &tegra_clk_pll_ops); 2167 if (IS_ERR(clk)) 2168 kfree(pll); 2169 2170 return clk; 2171 } 2172 2173 struct clk *tegra_clk_register_pllss_tegra210(const char *name, 2174 const char *parent_name, void __iomem *clk_base, 2175 unsigned long flags, 2176 struct tegra_clk_pll_params *pll_params, 2177 spinlock_t *lock) 2178 { 2179 struct tegra_clk_pll *pll; 2180 struct clk *clk, *parent; 2181 struct tegra_clk_pll_freq_table cfg; 2182 unsigned long parent_rate; 2183 u32 val; 2184 int i; 2185 2186 if (!pll_params->div_nmp) 2187 return ERR_PTR(-EINVAL); 2188 2189 parent = __clk_lookup(parent_name); 2190 if (!parent) { 2191 WARN(1, "parent clk %s of %s must be registered first\n", 2192 name, parent_name); 2193 return ERR_PTR(-EINVAL); 2194 } 2195 2196 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2197 if (IS_ERR(pll)) 2198 return ERR_CAST(pll); 2199 2200 val = pll_readl_base(pll); 2201 val &= ~PLLSS_REF_SRC_SEL_MASK; 2202 pll_writel_base(val, pll); 2203 2204 parent_rate = clk_get_rate(parent); 2205 2206 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2207 2208 /* initialize PLL to minimum rate */ 2209 2210 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 2211 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 2212 2213 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 2214 ; 2215 if (!i) { 2216 kfree(pll); 2217 return ERR_PTR(-EINVAL); 2218 } 2219 2220 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 2221 2222 _update_pll_mnp(pll, &cfg); 2223 2224 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 2225 2226 val = pll_readl_base(pll); 2227 if (val & PLL_BASE_ENABLE) { 2228 if (val & BIT(pll_params->iddq_bit_idx)) { 2229 WARN(1, "%s is on but IDDQ set\n", name); 2230 kfree(pll); 2231 return ERR_PTR(-EINVAL); 2232 } 2233 } else 2234 val |= BIT(pll_params->iddq_bit_idx); 2235 2236 val &= ~PLLSS_LOCK_OVERRIDE; 2237 pll_writel_base(val, pll); 2238 2239 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2240 &tegra_clk_pll_ops); 2241 2242 if (IS_ERR(clk)) 2243 kfree(pll); 2244 2245 return clk; 2246 } 2247 2248 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 2249 void __iomem *clk_base, void __iomem *pmc, 2250 unsigned long flags, 2251 struct tegra_clk_pll_params *pll_params, 2252 spinlock_t *lock) 2253 { 2254 struct tegra_clk_pll *pll; 2255 struct clk *clk, *parent; 2256 unsigned long parent_rate; 2257 2258 if (!pll_params->pdiv_tohw) 2259 return ERR_PTR(-EINVAL); 2260 2261 parent = __clk_lookup(parent_name); 2262 if (!parent) { 2263 WARN(1, "parent clk %s of %s must be registered first\n", 2264 parent_name, name); 2265 return ERR_PTR(-EINVAL); 2266 } 2267 2268 parent_rate = clk_get_rate(parent); 2269 2270 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2271 2272 pll_params->flags |= TEGRA_PLL_BYPASS; 2273 pll_params->flags |= TEGRA_PLLMB; 2274 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2275 if (IS_ERR(pll)) 2276 return ERR_CAST(pll); 2277 2278 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2279 &tegra_clk_pll_ops); 2280 if (IS_ERR(clk)) 2281 kfree(pll); 2282 2283 return clk; 2284 } 2285 #endif 2286