1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 69 #define PLLE_MISC_SETUP_BASE_SHIFT 16 70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 71 #define PLLE_MISC_LOCK_ENABLE BIT(9) 72 #define PLLE_MISC_READY BIT(15) 73 #define PLLE_MISC_SETUP_EX_SHIFT 2 74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 76 PLLE_MISC_SETUP_EX_MASK) 77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 78 79 #define PLLE_SS_CTRL 0x68 80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 82 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 83 #define PLLE_SS_CNTL_CENTER BIT(14) 84 #define PLLE_SS_CNTL_INVERT BIT(15) 85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 86 PLLE_SS_CNTL_SSC_BYP) 87 #define PLLE_SS_MAX_MASK 0x1ff 88 #define PLLE_SS_MAX_VAL 0x25 89 #define PLLE_SS_INC_MASK (0xff << 16) 90 #define PLLE_SS_INC_VAL (0x1 << 16) 91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 93 #define PLLE_SS_COEFFICIENTS_MASK \ 94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 95 #define PLLE_SS_COEFFICIENTS_VAL \ 96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 97 98 #define PLLE_AUX_PLLP_SEL BIT(2) 99 #define PLLE_AUX_USE_LOCKDET BIT(3) 100 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 101 #define PLLE_AUX_SS_SWCTL BIT(6) 102 #define PLLE_AUX_SEQ_ENABLE BIT(24) 103 #define PLLE_AUX_SEQ_START_STATE BIT(25) 104 #define PLLE_AUX_PLLRE_SEL BIT(28) 105 106 #define XUSBIO_PLL_CFG0 0x51c 107 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 108 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 109 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 110 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 111 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 112 113 #define SATA_PLL_CFG0 0x490 114 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 115 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 116 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 117 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 118 119 #define PLLE_MISC_PLLE_PTS BIT(8) 120 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 121 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 122 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 123 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 124 #define PLLE_MISC_VREG_CTRL_SHIFT 2 125 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 126 127 #define PLLCX_MISC_STROBE BIT(31) 128 #define PLLCX_MISC_RESET BIT(30) 129 #define PLLCX_MISC_SDM_DIV_SHIFT 28 130 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 131 #define PLLCX_MISC_FILT_DIV_SHIFT 26 132 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 133 #define PLLCX_MISC_ALPHA_SHIFT 18 134 #define PLLCX_MISC_DIV_LOW_RANGE \ 135 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 136 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 137 #define PLLCX_MISC_DIV_HIGH_RANGE \ 138 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 139 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 140 #define PLLCX_MISC_COEF_LOW_RANGE \ 141 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 142 #define PLLCX_MISC_KA_SHIFT 2 143 #define PLLCX_MISC_KB_SHIFT 9 144 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 145 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 146 PLLCX_MISC_DIV_LOW_RANGE | \ 147 PLLCX_MISC_RESET) 148 #define PLLCX_MISC1_DEFAULT 0x000d2308 149 #define PLLCX_MISC2_DEFAULT 0x30211200 150 #define PLLCX_MISC3_DEFAULT 0x200 151 152 #define PMC_SATA_PWRGT 0x1ac 153 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 154 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 155 156 #define PLLSS_MISC_KCP 0 157 #define PLLSS_MISC_KVCO 0 158 #define PLLSS_MISC_SETUP 0 159 #define PLLSS_EN_SDM 0 160 #define PLLSS_EN_SSC 0 161 #define PLLSS_EN_DITHER2 0 162 #define PLLSS_EN_DITHER 1 163 #define PLLSS_SDM_RESET 0 164 #define PLLSS_CLAMP 0 165 #define PLLSS_SDM_SSC_MAX 0 166 #define PLLSS_SDM_SSC_MIN 0 167 #define PLLSS_SDM_SSC_STEP 0 168 #define PLLSS_SDM_DIN 0 169 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 170 (PLLSS_MISC_KVCO << 24) | \ 171 PLLSS_MISC_SETUP) 172 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 173 (PLLSS_EN_SSC << 30) | \ 174 (PLLSS_EN_DITHER2 << 29) | \ 175 (PLLSS_EN_DITHER << 28) | \ 176 (PLLSS_SDM_RESET) << 27 | \ 177 (PLLSS_CLAMP << 22)) 178 #define PLLSS_CTRL1_DEFAULT \ 179 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 180 #define PLLSS_CTRL2_DEFAULT \ 181 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 182 #define PLLSS_LOCK_OVERRIDE BIT(24) 183 #define PLLSS_REF_SRC_SEL_SHIFT 25 184 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 185 186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 187 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 188 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 189 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 190 191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 194 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 195 196 #define mask(w) ((1 << (w)) - 1) 197 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 198 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 199 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 200 mask(p->params->div_nmp->divp_width)) 201 202 #define divm_shift(p) (p)->params->div_nmp->divm_shift 203 #define divn_shift(p) (p)->params->div_nmp->divn_shift 204 #define divp_shift(p) (p)->params->div_nmp->divp_shift 205 206 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 207 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 208 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 209 210 #define divm_max(p) (divm_mask(p)) 211 #define divn_max(p) (divn_mask(p)) 212 #define divp_max(p) (1 << (divp_mask(p))) 213 214 static struct div_nmp default_nmp = { 215 .divn_shift = PLL_BASE_DIVN_SHIFT, 216 .divn_width = PLL_BASE_DIVN_WIDTH, 217 .divm_shift = PLL_BASE_DIVM_SHIFT, 218 .divm_width = PLL_BASE_DIVM_WIDTH, 219 .divp_shift = PLL_BASE_DIVP_SHIFT, 220 .divp_width = PLL_BASE_DIVP_WIDTH, 221 }; 222 223 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 224 { 225 u32 val; 226 227 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 228 return; 229 230 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 231 return; 232 233 val = pll_readl_misc(pll); 234 val |= BIT(pll->params->lock_enable_bit_idx); 235 pll_writel_misc(val, pll); 236 } 237 238 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 239 { 240 int i; 241 u32 val, lock_mask; 242 void __iomem *lock_addr; 243 244 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 245 udelay(pll->params->lock_delay); 246 return 0; 247 } 248 249 lock_addr = pll->clk_base; 250 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 251 lock_addr += pll->params->misc_reg; 252 else 253 lock_addr += pll->params->base_reg; 254 255 lock_mask = pll->params->lock_mask; 256 257 for (i = 0; i < pll->params->lock_delay; i++) { 258 val = readl_relaxed(lock_addr); 259 if ((val & lock_mask) == lock_mask) { 260 udelay(PLL_POST_LOCK_DELAY); 261 return 0; 262 } 263 udelay(2); /* timeout = 2 * lock time */ 264 } 265 266 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 267 clk_hw_get_name(&pll->hw)); 268 269 return -1; 270 } 271 272 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 273 { 274 return clk_pll_wait_for_lock(pll); 275 } 276 277 static int clk_pll_is_enabled(struct clk_hw *hw) 278 { 279 struct tegra_clk_pll *pll = to_clk_pll(hw); 280 u32 val; 281 282 if (pll->params->flags & TEGRA_PLLM) { 283 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 284 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 285 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 286 } 287 288 val = pll_readl_base(pll); 289 290 return val & PLL_BASE_ENABLE ? 1 : 0; 291 } 292 293 static void _clk_pll_enable(struct clk_hw *hw) 294 { 295 struct tegra_clk_pll *pll = to_clk_pll(hw); 296 u32 val; 297 298 if (pll->params->iddq_reg) { 299 val = pll_readl(pll->params->iddq_reg, pll); 300 val &= ~BIT(pll->params->iddq_bit_idx); 301 pll_writel(val, pll->params->iddq_reg, pll); 302 udelay(2); 303 } 304 305 clk_pll_enable_lock(pll); 306 307 val = pll_readl_base(pll); 308 if (pll->params->flags & TEGRA_PLL_BYPASS) 309 val &= ~PLL_BASE_BYPASS; 310 val |= PLL_BASE_ENABLE; 311 pll_writel_base(val, pll); 312 313 if (pll->params->flags & TEGRA_PLLM) { 314 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 315 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 316 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 317 } 318 } 319 320 static void _clk_pll_disable(struct clk_hw *hw) 321 { 322 struct tegra_clk_pll *pll = to_clk_pll(hw); 323 u32 val; 324 325 val = pll_readl_base(pll); 326 if (pll->params->flags & TEGRA_PLL_BYPASS) 327 val &= ~PLL_BASE_BYPASS; 328 val &= ~PLL_BASE_ENABLE; 329 pll_writel_base(val, pll); 330 331 if (pll->params->flags & TEGRA_PLLM) { 332 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 333 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 334 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 335 } 336 337 if (pll->params->iddq_reg) { 338 val = pll_readl(pll->params->iddq_reg, pll); 339 val |= BIT(pll->params->iddq_bit_idx); 340 pll_writel(val, pll->params->iddq_reg, pll); 341 udelay(2); 342 } 343 } 344 345 static int clk_pll_enable(struct clk_hw *hw) 346 { 347 struct tegra_clk_pll *pll = to_clk_pll(hw); 348 unsigned long flags = 0; 349 int ret; 350 351 if (pll->lock) 352 spin_lock_irqsave(pll->lock, flags); 353 354 _clk_pll_enable(hw); 355 356 ret = clk_pll_wait_for_lock(pll); 357 358 if (pll->lock) 359 spin_unlock_irqrestore(pll->lock, flags); 360 361 return ret; 362 } 363 364 static void clk_pll_disable(struct clk_hw *hw) 365 { 366 struct tegra_clk_pll *pll = to_clk_pll(hw); 367 unsigned long flags = 0; 368 369 if (pll->lock) 370 spin_lock_irqsave(pll->lock, flags); 371 372 _clk_pll_disable(hw); 373 374 if (pll->lock) 375 spin_unlock_irqrestore(pll->lock, flags); 376 } 377 378 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 379 { 380 struct tegra_clk_pll *pll = to_clk_pll(hw); 381 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 382 383 if (p_tohw) { 384 while (p_tohw->pdiv) { 385 if (p_div <= p_tohw->pdiv) 386 return p_tohw->hw_val; 387 p_tohw++; 388 } 389 return -EINVAL; 390 } 391 return -EINVAL; 392 } 393 394 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 395 { 396 struct tegra_clk_pll *pll = to_clk_pll(hw); 397 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 398 399 if (p_tohw) { 400 while (p_tohw->pdiv) { 401 if (p_div_hw == p_tohw->hw_val) 402 return p_tohw->pdiv; 403 p_tohw++; 404 } 405 return -EINVAL; 406 } 407 408 return 1 << p_div_hw; 409 } 410 411 static int _get_table_rate(struct clk_hw *hw, 412 struct tegra_clk_pll_freq_table *cfg, 413 unsigned long rate, unsigned long parent_rate) 414 { 415 struct tegra_clk_pll *pll = to_clk_pll(hw); 416 struct tegra_clk_pll_freq_table *sel; 417 418 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 419 if (sel->input_rate == parent_rate && 420 sel->output_rate == rate) 421 break; 422 423 if (sel->input_rate == 0) 424 return -EINVAL; 425 426 cfg->input_rate = sel->input_rate; 427 cfg->output_rate = sel->output_rate; 428 cfg->m = sel->m; 429 cfg->n = sel->n; 430 cfg->p = sel->p; 431 cfg->cpcon = sel->cpcon; 432 433 return 0; 434 } 435 436 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 437 unsigned long rate, unsigned long parent_rate) 438 { 439 struct tegra_clk_pll *pll = to_clk_pll(hw); 440 unsigned long cfreq; 441 u32 p_div = 0; 442 int ret; 443 444 switch (parent_rate) { 445 case 12000000: 446 case 26000000: 447 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 448 break; 449 case 13000000: 450 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 451 break; 452 case 16800000: 453 case 19200000: 454 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 455 break; 456 case 9600000: 457 case 28800000: 458 /* 459 * PLL_P_OUT1 rate is not listed in PLLA table 460 */ 461 cfreq = parent_rate / (parent_rate / 1000000); 462 break; 463 default: 464 pr_err("%s Unexpected reference rate %lu\n", 465 __func__, parent_rate); 466 BUG(); 467 } 468 469 /* Raise VCO to guarantee 0.5% accuracy */ 470 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 471 cfg->output_rate <<= 1) 472 p_div++; 473 474 cfg->m = parent_rate / cfreq; 475 cfg->n = cfg->output_rate / cfreq; 476 cfg->cpcon = OUT_OF_TABLE_CPCON; 477 478 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 479 (1 << p_div) > divp_max(pll) 480 || cfg->output_rate > pll->params->vco_max) { 481 return -EINVAL; 482 } 483 484 cfg->output_rate >>= p_div; 485 486 if (pll->params->pdiv_tohw) { 487 ret = _p_div_to_hw(hw, 1 << p_div); 488 if (ret < 0) 489 return ret; 490 else 491 cfg->p = ret; 492 } else 493 cfg->p = p_div; 494 495 return 0; 496 } 497 498 static void _update_pll_mnp(struct tegra_clk_pll *pll, 499 struct tegra_clk_pll_freq_table *cfg) 500 { 501 u32 val; 502 struct tegra_clk_pll_params *params = pll->params; 503 struct div_nmp *div_nmp = params->div_nmp; 504 505 if ((params->flags & TEGRA_PLLM) && 506 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 507 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 508 val = pll_override_readl(params->pmc_divp_reg, pll); 509 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 510 val |= cfg->p << div_nmp->override_divp_shift; 511 pll_override_writel(val, params->pmc_divp_reg, pll); 512 513 val = pll_override_readl(params->pmc_divnm_reg, pll); 514 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | 515 ~(divn_mask(pll) << div_nmp->override_divn_shift); 516 val |= (cfg->m << div_nmp->override_divm_shift) | 517 (cfg->n << div_nmp->override_divn_shift); 518 pll_override_writel(val, params->pmc_divnm_reg, pll); 519 } else { 520 val = pll_readl_base(pll); 521 522 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 523 divp_mask_shifted(pll)); 524 525 val |= (cfg->m << divm_shift(pll)) | 526 (cfg->n << divn_shift(pll)) | 527 (cfg->p << divp_shift(pll)); 528 529 pll_writel_base(val, pll); 530 } 531 } 532 533 static void _get_pll_mnp(struct tegra_clk_pll *pll, 534 struct tegra_clk_pll_freq_table *cfg) 535 { 536 u32 val; 537 struct tegra_clk_pll_params *params = pll->params; 538 struct div_nmp *div_nmp = params->div_nmp; 539 540 if ((params->flags & TEGRA_PLLM) && 541 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 542 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 543 val = pll_override_readl(params->pmc_divp_reg, pll); 544 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 545 546 val = pll_override_readl(params->pmc_divnm_reg, pll); 547 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 548 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 549 } else { 550 val = pll_readl_base(pll); 551 552 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 553 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 554 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 555 } 556 } 557 558 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 559 struct tegra_clk_pll_freq_table *cfg, 560 unsigned long rate) 561 { 562 u32 val; 563 564 val = pll_readl_misc(pll); 565 566 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 567 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 568 569 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 570 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 571 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 572 val |= 1 << PLL_MISC_LFCON_SHIFT; 573 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 574 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 575 if (rate >= (pll->params->vco_max >> 1)) 576 val |= 1 << PLL_MISC_DCCON_SHIFT; 577 } 578 579 pll_writel_misc(val, pll); 580 } 581 582 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 583 unsigned long rate) 584 { 585 struct tegra_clk_pll *pll = to_clk_pll(hw); 586 int state, ret = 0; 587 588 state = clk_pll_is_enabled(hw); 589 590 if (state) 591 _clk_pll_disable(hw); 592 593 _update_pll_mnp(pll, cfg); 594 595 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 596 _update_pll_cpcon(pll, cfg, rate); 597 598 if (state) { 599 _clk_pll_enable(hw); 600 ret = clk_pll_wait_for_lock(pll); 601 } 602 603 return ret; 604 } 605 606 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 607 unsigned long parent_rate) 608 { 609 struct tegra_clk_pll *pll = to_clk_pll(hw); 610 struct tegra_clk_pll_freq_table cfg, old_cfg; 611 unsigned long flags = 0; 612 int ret = 0; 613 614 if (pll->params->flags & TEGRA_PLL_FIXED) { 615 if (rate != pll->params->fixed_rate) { 616 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 617 __func__, clk_hw_get_name(hw), 618 pll->params->fixed_rate, rate); 619 return -EINVAL; 620 } 621 return 0; 622 } 623 624 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 625 _calc_rate(hw, &cfg, rate, parent_rate)) { 626 pr_err("%s: Failed to set %s rate %lu\n", __func__, 627 clk_hw_get_name(hw), rate); 628 WARN_ON(1); 629 return -EINVAL; 630 } 631 if (pll->lock) 632 spin_lock_irqsave(pll->lock, flags); 633 634 _get_pll_mnp(pll, &old_cfg); 635 636 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 637 ret = _program_pll(hw, &cfg, rate); 638 639 if (pll->lock) 640 spin_unlock_irqrestore(pll->lock, flags); 641 642 return ret; 643 } 644 645 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 646 unsigned long *prate) 647 { 648 struct tegra_clk_pll *pll = to_clk_pll(hw); 649 struct tegra_clk_pll_freq_table cfg; 650 651 if (pll->params->flags & TEGRA_PLL_FIXED) 652 return pll->params->fixed_rate; 653 654 /* PLLM is used for memory; we do not change rate */ 655 if (pll->params->flags & TEGRA_PLLM) 656 return clk_hw_get_rate(hw); 657 658 if (_get_table_rate(hw, &cfg, rate, *prate) && 659 _calc_rate(hw, &cfg, rate, *prate)) 660 return -EINVAL; 661 662 return cfg.output_rate; 663 } 664 665 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 666 unsigned long parent_rate) 667 { 668 struct tegra_clk_pll *pll = to_clk_pll(hw); 669 struct tegra_clk_pll_freq_table cfg; 670 u32 val; 671 u64 rate = parent_rate; 672 int pdiv; 673 674 val = pll_readl_base(pll); 675 676 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 677 return parent_rate; 678 679 if ((pll->params->flags & TEGRA_PLL_FIXED) && 680 !(val & PLL_BASE_OVERRIDE)) { 681 struct tegra_clk_pll_freq_table sel; 682 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 683 parent_rate)) { 684 pr_err("Clock %s has unknown fixed frequency\n", 685 clk_hw_get_name(hw)); 686 BUG(); 687 } 688 return pll->params->fixed_rate; 689 } 690 691 _get_pll_mnp(pll, &cfg); 692 693 pdiv = _hw_to_p_div(hw, cfg.p); 694 if (pdiv < 0) { 695 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 696 __clk_get_name(hw->clk), cfg.p); 697 pdiv = 1; 698 } 699 700 cfg.m *= pdiv; 701 702 rate *= cfg.n; 703 do_div(rate, cfg.m); 704 705 return rate; 706 } 707 708 static int clk_plle_training(struct tegra_clk_pll *pll) 709 { 710 u32 val; 711 unsigned long timeout; 712 713 if (!pll->pmc) 714 return -ENOSYS; 715 716 /* 717 * PLLE is already disabled, and setup cleared; 718 * create falling edge on PLLE IDDQ input. 719 */ 720 val = readl(pll->pmc + PMC_SATA_PWRGT); 721 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 722 writel(val, pll->pmc + PMC_SATA_PWRGT); 723 724 val = readl(pll->pmc + PMC_SATA_PWRGT); 725 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 726 writel(val, pll->pmc + PMC_SATA_PWRGT); 727 728 val = readl(pll->pmc + PMC_SATA_PWRGT); 729 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 730 writel(val, pll->pmc + PMC_SATA_PWRGT); 731 732 val = pll_readl_misc(pll); 733 734 timeout = jiffies + msecs_to_jiffies(100); 735 while (1) { 736 val = pll_readl_misc(pll); 737 if (val & PLLE_MISC_READY) 738 break; 739 if (time_after(jiffies, timeout)) { 740 pr_err("%s: timeout waiting for PLLE\n", __func__); 741 return -EBUSY; 742 } 743 udelay(300); 744 } 745 746 return 0; 747 } 748 749 static int clk_plle_enable(struct clk_hw *hw) 750 { 751 struct tegra_clk_pll *pll = to_clk_pll(hw); 752 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 753 struct tegra_clk_pll_freq_table sel; 754 u32 val; 755 int err; 756 757 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 758 return -EINVAL; 759 760 clk_pll_disable(hw); 761 762 val = pll_readl_misc(pll); 763 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 764 pll_writel_misc(val, pll); 765 766 val = pll_readl_misc(pll); 767 if (!(val & PLLE_MISC_READY)) { 768 err = clk_plle_training(pll); 769 if (err) 770 return err; 771 } 772 773 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 774 /* configure dividers */ 775 val = pll_readl_base(pll); 776 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 777 divm_mask_shifted(pll)); 778 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 779 val |= sel.m << divm_shift(pll); 780 val |= sel.n << divn_shift(pll); 781 val |= sel.p << divp_shift(pll); 782 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 783 pll_writel_base(val, pll); 784 } 785 786 val = pll_readl_misc(pll); 787 val |= PLLE_MISC_SETUP_VALUE; 788 val |= PLLE_MISC_LOCK_ENABLE; 789 pll_writel_misc(val, pll); 790 791 val = readl(pll->clk_base + PLLE_SS_CTRL); 792 val &= ~PLLE_SS_COEFFICIENTS_MASK; 793 val |= PLLE_SS_DISABLE; 794 writel(val, pll->clk_base + PLLE_SS_CTRL); 795 796 val = pll_readl_base(pll); 797 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 798 pll_writel_base(val, pll); 799 800 clk_pll_wait_for_lock(pll); 801 802 return 0; 803 } 804 805 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 806 unsigned long parent_rate) 807 { 808 struct tegra_clk_pll *pll = to_clk_pll(hw); 809 u32 val = pll_readl_base(pll); 810 u32 divn = 0, divm = 0, divp = 0; 811 u64 rate = parent_rate; 812 813 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 814 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 815 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 816 divm *= divp; 817 818 rate *= divn; 819 do_div(rate, divm); 820 return rate; 821 } 822 823 const struct clk_ops tegra_clk_pll_ops = { 824 .is_enabled = clk_pll_is_enabled, 825 .enable = clk_pll_enable, 826 .disable = clk_pll_disable, 827 .recalc_rate = clk_pll_recalc_rate, 828 .round_rate = clk_pll_round_rate, 829 .set_rate = clk_pll_set_rate, 830 }; 831 832 const struct clk_ops tegra_clk_plle_ops = { 833 .recalc_rate = clk_plle_recalc_rate, 834 .is_enabled = clk_pll_is_enabled, 835 .disable = clk_pll_disable, 836 .enable = clk_plle_enable, 837 }; 838 839 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 840 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 841 defined(CONFIG_ARCH_TEGRA_132_SOC) 842 843 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 844 unsigned long parent_rate) 845 { 846 if (parent_rate > pll_params->cf_max) 847 return 2; 848 else 849 return 1; 850 } 851 852 static unsigned long _clip_vco_min(unsigned long vco_min, 853 unsigned long parent_rate) 854 { 855 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 856 } 857 858 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 859 void __iomem *clk_base, 860 unsigned long parent_rate) 861 { 862 u32 val; 863 u32 step_a, step_b; 864 865 switch (parent_rate) { 866 case 12000000: 867 case 13000000: 868 case 26000000: 869 step_a = 0x2B; 870 step_b = 0x0B; 871 break; 872 case 16800000: 873 step_a = 0x1A; 874 step_b = 0x09; 875 break; 876 case 19200000: 877 step_a = 0x12; 878 step_b = 0x08; 879 break; 880 default: 881 pr_err("%s: Unexpected reference rate %lu\n", 882 __func__, parent_rate); 883 WARN_ON(1); 884 return -EINVAL; 885 } 886 887 val = step_a << pll_params->stepa_shift; 888 val |= step_b << pll_params->stepb_shift; 889 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 890 891 return 0; 892 } 893 894 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 895 struct tegra_clk_pll_freq_table *cfg, 896 unsigned long rate, unsigned long parent_rate) 897 { 898 struct tegra_clk_pll *pll = to_clk_pll(hw); 899 unsigned int p; 900 int p_div; 901 902 if (!rate) 903 return -EINVAL; 904 905 p = DIV_ROUND_UP(pll->params->vco_min, rate); 906 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 907 cfg->output_rate = rate * p; 908 cfg->n = cfg->output_rate * cfg->m / parent_rate; 909 910 p_div = _p_div_to_hw(hw, p); 911 if (p_div < 0) 912 return p_div; 913 914 cfg->p = p_div; 915 916 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 917 return -EINVAL; 918 919 return 0; 920 } 921 922 static int _pll_ramp_calc_pll(struct clk_hw *hw, 923 struct tegra_clk_pll_freq_table *cfg, 924 unsigned long rate, unsigned long parent_rate) 925 { 926 struct tegra_clk_pll *pll = to_clk_pll(hw); 927 int err = 0, p_div; 928 929 err = _get_table_rate(hw, cfg, rate, parent_rate); 930 if (err < 0) 931 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 932 else { 933 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 934 WARN_ON(1); 935 err = -EINVAL; 936 goto out; 937 } 938 p_div = _p_div_to_hw(hw, cfg->p); 939 if (p_div < 0) 940 return p_div; 941 else 942 cfg->p = p_div; 943 } 944 945 if (cfg->p > pll->params->max_p) 946 err = -EINVAL; 947 948 out: 949 return err; 950 } 951 952 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 953 unsigned long parent_rate) 954 { 955 struct tegra_clk_pll *pll = to_clk_pll(hw); 956 struct tegra_clk_pll_freq_table cfg, old_cfg; 957 unsigned long flags = 0; 958 int ret; 959 960 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 961 if (ret < 0) 962 return ret; 963 964 if (pll->lock) 965 spin_lock_irqsave(pll->lock, flags); 966 967 _get_pll_mnp(pll, &old_cfg); 968 969 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 970 ret = _program_pll(hw, &cfg, rate); 971 972 if (pll->lock) 973 spin_unlock_irqrestore(pll->lock, flags); 974 975 return ret; 976 } 977 978 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 979 unsigned long *prate) 980 { 981 struct tegra_clk_pll_freq_table cfg; 982 int ret, p_div; 983 u64 output_rate = *prate; 984 985 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 986 if (ret < 0) 987 return ret; 988 989 p_div = _hw_to_p_div(hw, cfg.p); 990 if (p_div < 0) 991 return p_div; 992 993 output_rate *= cfg.n; 994 do_div(output_rate, cfg.m * p_div); 995 996 return output_rate; 997 } 998 999 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, 1000 unsigned long parent_rate) 1001 { 1002 struct tegra_clk_pll_freq_table cfg; 1003 struct tegra_clk_pll *pll = to_clk_pll(hw); 1004 unsigned long flags = 0; 1005 int state, ret = 0; 1006 1007 if (pll->lock) 1008 spin_lock_irqsave(pll->lock, flags); 1009 1010 state = clk_pll_is_enabled(hw); 1011 if (state) { 1012 if (rate != clk_get_rate(hw->clk)) { 1013 pr_err("%s: Cannot change active PLLM\n", __func__); 1014 ret = -EINVAL; 1015 goto out; 1016 } 1017 goto out; 1018 } 1019 1020 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1021 if (ret < 0) 1022 goto out; 1023 1024 _update_pll_mnp(pll, &cfg); 1025 1026 out: 1027 if (pll->lock) 1028 spin_unlock_irqrestore(pll->lock, flags); 1029 1030 return ret; 1031 } 1032 1033 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1034 { 1035 u32 val; 1036 1037 val = pll_readl_misc(pll); 1038 val |= PLLCX_MISC_STROBE; 1039 pll_writel_misc(val, pll); 1040 udelay(2); 1041 1042 val &= ~PLLCX_MISC_STROBE; 1043 pll_writel_misc(val, pll); 1044 } 1045 1046 static int clk_pllc_enable(struct clk_hw *hw) 1047 { 1048 struct tegra_clk_pll *pll = to_clk_pll(hw); 1049 u32 val; 1050 int ret; 1051 unsigned long flags = 0; 1052 1053 if (pll->lock) 1054 spin_lock_irqsave(pll->lock, flags); 1055 1056 _clk_pll_enable(hw); 1057 udelay(2); 1058 1059 val = pll_readl_misc(pll); 1060 val &= ~PLLCX_MISC_RESET; 1061 pll_writel_misc(val, pll); 1062 udelay(2); 1063 1064 _pllcx_strobe(pll); 1065 1066 ret = clk_pll_wait_for_lock(pll); 1067 1068 if (pll->lock) 1069 spin_unlock_irqrestore(pll->lock, flags); 1070 1071 return ret; 1072 } 1073 1074 static void _clk_pllc_disable(struct clk_hw *hw) 1075 { 1076 struct tegra_clk_pll *pll = to_clk_pll(hw); 1077 u32 val; 1078 1079 _clk_pll_disable(hw); 1080 1081 val = pll_readl_misc(pll); 1082 val |= PLLCX_MISC_RESET; 1083 pll_writel_misc(val, pll); 1084 udelay(2); 1085 } 1086 1087 static void clk_pllc_disable(struct clk_hw *hw) 1088 { 1089 struct tegra_clk_pll *pll = to_clk_pll(hw); 1090 unsigned long flags = 0; 1091 1092 if (pll->lock) 1093 spin_lock_irqsave(pll->lock, flags); 1094 1095 _clk_pllc_disable(hw); 1096 1097 if (pll->lock) 1098 spin_unlock_irqrestore(pll->lock, flags); 1099 } 1100 1101 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1102 unsigned long input_rate, u32 n) 1103 { 1104 u32 val, n_threshold; 1105 1106 switch (input_rate) { 1107 case 12000000: 1108 n_threshold = 70; 1109 break; 1110 case 13000000: 1111 case 26000000: 1112 n_threshold = 71; 1113 break; 1114 case 16800000: 1115 n_threshold = 55; 1116 break; 1117 case 19200000: 1118 n_threshold = 48; 1119 break; 1120 default: 1121 pr_err("%s: Unexpected reference rate %lu\n", 1122 __func__, input_rate); 1123 return -EINVAL; 1124 } 1125 1126 val = pll_readl_misc(pll); 1127 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1128 val |= n <= n_threshold ? 1129 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1130 pll_writel_misc(val, pll); 1131 1132 return 0; 1133 } 1134 1135 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1136 unsigned long parent_rate) 1137 { 1138 struct tegra_clk_pll_freq_table cfg, old_cfg; 1139 struct tegra_clk_pll *pll = to_clk_pll(hw); 1140 unsigned long flags = 0; 1141 int state, ret = 0; 1142 1143 if (pll->lock) 1144 spin_lock_irqsave(pll->lock, flags); 1145 1146 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1147 if (ret < 0) 1148 goto out; 1149 1150 _get_pll_mnp(pll, &old_cfg); 1151 1152 if (cfg.m != old_cfg.m) { 1153 WARN_ON(1); 1154 goto out; 1155 } 1156 1157 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1158 goto out; 1159 1160 state = clk_pll_is_enabled(hw); 1161 if (state) 1162 _clk_pllc_disable(hw); 1163 1164 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1165 if (ret < 0) 1166 goto out; 1167 1168 _update_pll_mnp(pll, &cfg); 1169 1170 if (state) 1171 ret = clk_pllc_enable(hw); 1172 1173 out: 1174 if (pll->lock) 1175 spin_unlock_irqrestore(pll->lock, flags); 1176 1177 return ret; 1178 } 1179 1180 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1181 struct tegra_clk_pll_freq_table *cfg, 1182 unsigned long rate, unsigned long parent_rate) 1183 { 1184 u16 m, n; 1185 u64 output_rate = parent_rate; 1186 1187 m = _pll_fixed_mdiv(pll->params, parent_rate); 1188 n = rate * m / parent_rate; 1189 1190 output_rate *= n; 1191 do_div(output_rate, m); 1192 1193 if (cfg) { 1194 cfg->m = m; 1195 cfg->n = n; 1196 } 1197 1198 return output_rate; 1199 } 1200 1201 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1202 unsigned long parent_rate) 1203 { 1204 struct tegra_clk_pll_freq_table cfg, old_cfg; 1205 struct tegra_clk_pll *pll = to_clk_pll(hw); 1206 unsigned long flags = 0; 1207 int state, ret = 0; 1208 1209 if (pll->lock) 1210 spin_lock_irqsave(pll->lock, flags); 1211 1212 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1213 _get_pll_mnp(pll, &old_cfg); 1214 cfg.p = old_cfg.p; 1215 1216 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1217 state = clk_pll_is_enabled(hw); 1218 if (state) 1219 _clk_pll_disable(hw); 1220 1221 _update_pll_mnp(pll, &cfg); 1222 1223 if (state) { 1224 _clk_pll_enable(hw); 1225 ret = clk_pll_wait_for_lock(pll); 1226 } 1227 } 1228 1229 if (pll->lock) 1230 spin_unlock_irqrestore(pll->lock, flags); 1231 1232 return ret; 1233 } 1234 1235 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1236 unsigned long parent_rate) 1237 { 1238 struct tegra_clk_pll_freq_table cfg; 1239 struct tegra_clk_pll *pll = to_clk_pll(hw); 1240 u64 rate = parent_rate; 1241 1242 _get_pll_mnp(pll, &cfg); 1243 1244 rate *= cfg.n; 1245 do_div(rate, cfg.m); 1246 1247 return rate; 1248 } 1249 1250 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1251 unsigned long *prate) 1252 { 1253 struct tegra_clk_pll *pll = to_clk_pll(hw); 1254 1255 return _pllre_calc_rate(pll, NULL, rate, *prate); 1256 } 1257 1258 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1259 { 1260 struct tegra_clk_pll *pll = to_clk_pll(hw); 1261 struct tegra_clk_pll_freq_table sel; 1262 u32 val; 1263 int ret; 1264 unsigned long flags = 0; 1265 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1266 1267 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1268 return -EINVAL; 1269 1270 if (pll->lock) 1271 spin_lock_irqsave(pll->lock, flags); 1272 1273 val = pll_readl_base(pll); 1274 val &= ~BIT(29); /* Disable lock override */ 1275 pll_writel_base(val, pll); 1276 1277 val = pll_readl(pll->params->aux_reg, pll); 1278 val |= PLLE_AUX_ENABLE_SWCTL; 1279 val &= ~PLLE_AUX_SEQ_ENABLE; 1280 pll_writel(val, pll->params->aux_reg, pll); 1281 udelay(1); 1282 1283 val = pll_readl_misc(pll); 1284 val |= PLLE_MISC_LOCK_ENABLE; 1285 val |= PLLE_MISC_IDDQ_SW_CTRL; 1286 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1287 val |= PLLE_MISC_PLLE_PTS; 1288 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1289 pll_writel_misc(val, pll); 1290 udelay(5); 1291 1292 val = pll_readl(PLLE_SS_CTRL, pll); 1293 val |= PLLE_SS_DISABLE; 1294 pll_writel(val, PLLE_SS_CTRL, pll); 1295 1296 val = pll_readl_base(pll); 1297 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1298 divm_mask_shifted(pll)); 1299 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1300 val |= sel.m << divm_shift(pll); 1301 val |= sel.n << divn_shift(pll); 1302 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1303 pll_writel_base(val, pll); 1304 udelay(1); 1305 1306 _clk_pll_enable(hw); 1307 ret = clk_pll_wait_for_lock(pll); 1308 1309 if (ret < 0) 1310 goto out; 1311 1312 val = pll_readl(PLLE_SS_CTRL, pll); 1313 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1314 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1315 val |= PLLE_SS_COEFFICIENTS_VAL; 1316 pll_writel(val, PLLE_SS_CTRL, pll); 1317 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1318 pll_writel(val, PLLE_SS_CTRL, pll); 1319 udelay(1); 1320 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1321 pll_writel(val, PLLE_SS_CTRL, pll); 1322 udelay(1); 1323 1324 /* Enable hw control of xusb brick pll */ 1325 val = pll_readl_misc(pll); 1326 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1327 pll_writel_misc(val, pll); 1328 1329 val = pll_readl(pll->params->aux_reg, pll); 1330 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1331 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1332 pll_writel(val, pll->params->aux_reg, pll); 1333 udelay(1); 1334 val |= PLLE_AUX_SEQ_ENABLE; 1335 pll_writel(val, pll->params->aux_reg, pll); 1336 1337 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1338 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1339 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1340 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1341 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1342 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1343 udelay(1); 1344 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1345 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1346 1347 /* Enable hw control of SATA pll */ 1348 val = pll_readl(SATA_PLL_CFG0, pll); 1349 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1350 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1351 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1352 pll_writel(val, SATA_PLL_CFG0, pll); 1353 1354 udelay(1); 1355 1356 val = pll_readl(SATA_PLL_CFG0, pll); 1357 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1358 pll_writel(val, SATA_PLL_CFG0, pll); 1359 1360 out: 1361 if (pll->lock) 1362 spin_unlock_irqrestore(pll->lock, flags); 1363 1364 return ret; 1365 } 1366 1367 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1368 { 1369 struct tegra_clk_pll *pll = to_clk_pll(hw); 1370 unsigned long flags = 0; 1371 u32 val; 1372 1373 if (pll->lock) 1374 spin_lock_irqsave(pll->lock, flags); 1375 1376 _clk_pll_disable(hw); 1377 1378 val = pll_readl_misc(pll); 1379 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1380 pll_writel_misc(val, pll); 1381 udelay(1); 1382 1383 if (pll->lock) 1384 spin_unlock_irqrestore(pll->lock, flags); 1385 } 1386 #endif 1387 1388 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1389 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1390 spinlock_t *lock) 1391 { 1392 struct tegra_clk_pll *pll; 1393 1394 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1395 if (!pll) 1396 return ERR_PTR(-ENOMEM); 1397 1398 pll->clk_base = clk_base; 1399 pll->pmc = pmc; 1400 1401 pll->params = pll_params; 1402 pll->lock = lock; 1403 1404 if (!pll_params->div_nmp) 1405 pll_params->div_nmp = &default_nmp; 1406 1407 return pll; 1408 } 1409 1410 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1411 const char *name, const char *parent_name, unsigned long flags, 1412 const struct clk_ops *ops) 1413 { 1414 struct clk_init_data init; 1415 1416 init.name = name; 1417 init.ops = ops; 1418 init.flags = flags; 1419 init.parent_names = (parent_name ? &parent_name : NULL); 1420 init.num_parents = (parent_name ? 1 : 0); 1421 1422 /* Data in .init is copied by clk_register(), so stack variable OK */ 1423 pll->hw.init = &init; 1424 1425 return clk_register(NULL, &pll->hw); 1426 } 1427 1428 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1429 void __iomem *clk_base, void __iomem *pmc, 1430 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1431 spinlock_t *lock) 1432 { 1433 struct tegra_clk_pll *pll; 1434 struct clk *clk; 1435 1436 pll_params->flags |= TEGRA_PLL_BYPASS; 1437 1438 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1439 if (IS_ERR(pll)) 1440 return ERR_CAST(pll); 1441 1442 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1443 &tegra_clk_pll_ops); 1444 if (IS_ERR(clk)) 1445 kfree(pll); 1446 1447 return clk; 1448 } 1449 1450 static struct div_nmp pll_e_nmp = { 1451 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1452 .divn_width = PLLE_BASE_DIVN_WIDTH, 1453 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1454 .divm_width = PLLE_BASE_DIVM_WIDTH, 1455 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1456 .divp_width = PLLE_BASE_DIVP_WIDTH, 1457 }; 1458 1459 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1460 void __iomem *clk_base, void __iomem *pmc, 1461 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1462 spinlock_t *lock) 1463 { 1464 struct tegra_clk_pll *pll; 1465 struct clk *clk; 1466 1467 pll_params->flags |= TEGRA_PLL_BYPASS; 1468 1469 if (!pll_params->div_nmp) 1470 pll_params->div_nmp = &pll_e_nmp; 1471 1472 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1473 if (IS_ERR(pll)) 1474 return ERR_CAST(pll); 1475 1476 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1477 &tegra_clk_plle_ops); 1478 if (IS_ERR(clk)) 1479 kfree(pll); 1480 1481 return clk; 1482 } 1483 1484 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1485 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1486 defined(CONFIG_ARCH_TEGRA_132_SOC) 1487 static const struct clk_ops tegra_clk_pllxc_ops = { 1488 .is_enabled = clk_pll_is_enabled, 1489 .enable = clk_pll_enable, 1490 .disable = clk_pll_disable, 1491 .recalc_rate = clk_pll_recalc_rate, 1492 .round_rate = clk_pll_ramp_round_rate, 1493 .set_rate = clk_pllxc_set_rate, 1494 }; 1495 1496 static const struct clk_ops tegra_clk_pllm_ops = { 1497 .is_enabled = clk_pll_is_enabled, 1498 .enable = clk_pll_enable, 1499 .disable = clk_pll_disable, 1500 .recalc_rate = clk_pll_recalc_rate, 1501 .round_rate = clk_pll_ramp_round_rate, 1502 .set_rate = clk_pllm_set_rate, 1503 }; 1504 1505 static const struct clk_ops tegra_clk_pllc_ops = { 1506 .is_enabled = clk_pll_is_enabled, 1507 .enable = clk_pllc_enable, 1508 .disable = clk_pllc_disable, 1509 .recalc_rate = clk_pll_recalc_rate, 1510 .round_rate = clk_pll_ramp_round_rate, 1511 .set_rate = clk_pllc_set_rate, 1512 }; 1513 1514 static const struct clk_ops tegra_clk_pllre_ops = { 1515 .is_enabled = clk_pll_is_enabled, 1516 .enable = clk_pll_enable, 1517 .disable = clk_pll_disable, 1518 .recalc_rate = clk_pllre_recalc_rate, 1519 .round_rate = clk_pllre_round_rate, 1520 .set_rate = clk_pllre_set_rate, 1521 }; 1522 1523 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1524 .is_enabled = clk_pll_is_enabled, 1525 .enable = clk_plle_tegra114_enable, 1526 .disable = clk_plle_tegra114_disable, 1527 .recalc_rate = clk_pll_recalc_rate, 1528 }; 1529 1530 1531 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1532 void __iomem *clk_base, void __iomem *pmc, 1533 unsigned long flags, 1534 struct tegra_clk_pll_params *pll_params, 1535 spinlock_t *lock) 1536 { 1537 struct tegra_clk_pll *pll; 1538 struct clk *clk, *parent; 1539 unsigned long parent_rate; 1540 int err; 1541 u32 val, val_iddq; 1542 1543 parent = __clk_lookup(parent_name); 1544 if (!parent) { 1545 WARN(1, "parent clk %s of %s must be registered first\n", 1546 parent_name, name); 1547 return ERR_PTR(-EINVAL); 1548 } 1549 1550 if (!pll_params->pdiv_tohw) 1551 return ERR_PTR(-EINVAL); 1552 1553 parent_rate = clk_get_rate(parent); 1554 1555 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1556 1557 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1558 if (err) 1559 return ERR_PTR(err); 1560 1561 val = readl_relaxed(clk_base + pll_params->base_reg); 1562 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1563 1564 if (val & PLL_BASE_ENABLE) 1565 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1566 else { 1567 val_iddq |= BIT(pll_params->iddq_bit_idx); 1568 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1569 } 1570 1571 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1572 if (IS_ERR(pll)) 1573 return ERR_CAST(pll); 1574 1575 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1576 &tegra_clk_pllxc_ops); 1577 if (IS_ERR(clk)) 1578 kfree(pll); 1579 1580 return clk; 1581 } 1582 1583 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1584 void __iomem *clk_base, void __iomem *pmc, 1585 unsigned long flags, 1586 struct tegra_clk_pll_params *pll_params, 1587 spinlock_t *lock, unsigned long parent_rate) 1588 { 1589 u32 val; 1590 struct tegra_clk_pll *pll; 1591 struct clk *clk; 1592 1593 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1594 1595 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1596 if (IS_ERR(pll)) 1597 return ERR_CAST(pll); 1598 1599 /* program minimum rate by default */ 1600 1601 val = pll_readl_base(pll); 1602 if (val & PLL_BASE_ENABLE) 1603 WARN_ON(val & pll_params->iddq_bit_idx); 1604 else { 1605 int m; 1606 1607 m = _pll_fixed_mdiv(pll_params, parent_rate); 1608 val = m << divm_shift(pll); 1609 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 1610 pll_writel_base(val, pll); 1611 } 1612 1613 /* disable lock override */ 1614 1615 val = pll_readl_misc(pll); 1616 val &= ~BIT(29); 1617 pll_writel_misc(val, pll); 1618 1619 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1620 &tegra_clk_pllre_ops); 1621 if (IS_ERR(clk)) 1622 kfree(pll); 1623 1624 return clk; 1625 } 1626 1627 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1628 void __iomem *clk_base, void __iomem *pmc, 1629 unsigned long flags, 1630 struct tegra_clk_pll_params *pll_params, 1631 spinlock_t *lock) 1632 { 1633 struct tegra_clk_pll *pll; 1634 struct clk *clk, *parent; 1635 unsigned long parent_rate; 1636 1637 if (!pll_params->pdiv_tohw) 1638 return ERR_PTR(-EINVAL); 1639 1640 parent = __clk_lookup(parent_name); 1641 if (!parent) { 1642 WARN(1, "parent clk %s of %s must be registered first\n", 1643 parent_name, name); 1644 return ERR_PTR(-EINVAL); 1645 } 1646 1647 parent_rate = clk_get_rate(parent); 1648 1649 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1650 1651 pll_params->flags |= TEGRA_PLL_BYPASS; 1652 pll_params->flags |= TEGRA_PLLM; 1653 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1654 if (IS_ERR(pll)) 1655 return ERR_CAST(pll); 1656 1657 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1658 &tegra_clk_pllm_ops); 1659 if (IS_ERR(clk)) 1660 kfree(pll); 1661 1662 return clk; 1663 } 1664 1665 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1666 void __iomem *clk_base, void __iomem *pmc, 1667 unsigned long flags, 1668 struct tegra_clk_pll_params *pll_params, 1669 spinlock_t *lock) 1670 { 1671 struct clk *parent, *clk; 1672 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1673 struct tegra_clk_pll *pll; 1674 struct tegra_clk_pll_freq_table cfg; 1675 unsigned long parent_rate; 1676 1677 if (!p_tohw) 1678 return ERR_PTR(-EINVAL); 1679 1680 parent = __clk_lookup(parent_name); 1681 if (!parent) { 1682 WARN(1, "parent clk %s of %s must be registered first\n", 1683 parent_name, name); 1684 return ERR_PTR(-EINVAL); 1685 } 1686 1687 parent_rate = clk_get_rate(parent); 1688 1689 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1690 1691 pll_params->flags |= TEGRA_PLL_BYPASS; 1692 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1693 if (IS_ERR(pll)) 1694 return ERR_CAST(pll); 1695 1696 /* 1697 * Most of PLLC register fields are shadowed, and can not be read 1698 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1699 * Initialize PLL to default state: disabled, reset; shadow registers 1700 * loaded with default parameters; dividers are preset for half of 1701 * minimum VCO rate (the latter assured that shadowed divider settings 1702 * are within supported range). 1703 */ 1704 1705 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1706 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1707 1708 while (p_tohw->pdiv) { 1709 if (p_tohw->pdiv == 2) { 1710 cfg.p = p_tohw->hw_val; 1711 break; 1712 } 1713 p_tohw++; 1714 } 1715 1716 if (!p_tohw->pdiv) { 1717 WARN_ON(1); 1718 return ERR_PTR(-EINVAL); 1719 } 1720 1721 pll_writel_base(0, pll); 1722 _update_pll_mnp(pll, &cfg); 1723 1724 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1725 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1726 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1727 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1728 1729 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1730 1731 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1732 &tegra_clk_pllc_ops); 1733 if (IS_ERR(clk)) 1734 kfree(pll); 1735 1736 return clk; 1737 } 1738 1739 struct clk *tegra_clk_register_plle_tegra114(const char *name, 1740 const char *parent_name, 1741 void __iomem *clk_base, unsigned long flags, 1742 struct tegra_clk_pll_params *pll_params, 1743 spinlock_t *lock) 1744 { 1745 struct tegra_clk_pll *pll; 1746 struct clk *clk; 1747 u32 val, val_aux; 1748 1749 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1750 if (IS_ERR(pll)) 1751 return ERR_CAST(pll); 1752 1753 /* ensure parent is set to pll_re_vco */ 1754 1755 val = pll_readl_base(pll); 1756 val_aux = pll_readl(pll_params->aux_reg, pll); 1757 1758 if (val & PLL_BASE_ENABLE) { 1759 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1760 (val_aux & PLLE_AUX_PLLP_SEL)) 1761 WARN(1, "pll_e enabled with unsupported parent %s\n", 1762 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1763 "pll_re_vco"); 1764 } else { 1765 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1766 pll_writel(val_aux, pll_params->aux_reg, pll); 1767 } 1768 1769 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1770 &tegra_clk_plle_tegra114_ops); 1771 if (IS_ERR(clk)) 1772 kfree(pll); 1773 1774 return clk; 1775 } 1776 #endif 1777 1778 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 1779 static const struct clk_ops tegra_clk_pllss_ops = { 1780 .is_enabled = clk_pll_is_enabled, 1781 .enable = clk_pll_enable, 1782 .disable = clk_pll_disable, 1783 .recalc_rate = clk_pll_recalc_rate, 1784 .round_rate = clk_pll_ramp_round_rate, 1785 .set_rate = clk_pllxc_set_rate, 1786 }; 1787 1788 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 1789 void __iomem *clk_base, unsigned long flags, 1790 struct tegra_clk_pll_params *pll_params, 1791 spinlock_t *lock) 1792 { 1793 struct tegra_clk_pll *pll; 1794 struct clk *clk, *parent; 1795 struct tegra_clk_pll_freq_table cfg; 1796 unsigned long parent_rate; 1797 u32 val; 1798 int i; 1799 1800 if (!pll_params->div_nmp) 1801 return ERR_PTR(-EINVAL); 1802 1803 parent = __clk_lookup(parent_name); 1804 if (!parent) { 1805 WARN(1, "parent clk %s of %s must be registered first\n", 1806 parent_name, name); 1807 return ERR_PTR(-EINVAL); 1808 } 1809 1810 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1811 if (IS_ERR(pll)) 1812 return ERR_CAST(pll); 1813 1814 val = pll_readl_base(pll); 1815 val &= ~PLLSS_REF_SRC_SEL_MASK; 1816 pll_writel_base(val, pll); 1817 1818 parent_rate = clk_get_rate(parent); 1819 1820 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1821 1822 /* initialize PLL to minimum rate */ 1823 1824 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1825 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1826 1827 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 1828 ; 1829 if (!i) { 1830 kfree(pll); 1831 return ERR_PTR(-EINVAL); 1832 } 1833 1834 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 1835 1836 _update_pll_mnp(pll, &cfg); 1837 1838 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 1839 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 1840 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 1841 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1842 1843 val = pll_readl_base(pll); 1844 if (val & PLL_BASE_ENABLE) { 1845 if (val & BIT(pll_params->iddq_bit_idx)) { 1846 WARN(1, "%s is on but IDDQ set\n", name); 1847 kfree(pll); 1848 return ERR_PTR(-EINVAL); 1849 } 1850 } else 1851 val |= BIT(pll_params->iddq_bit_idx); 1852 1853 val &= ~PLLSS_LOCK_OVERRIDE; 1854 pll_writel_base(val, pll); 1855 1856 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1857 &tegra_clk_pllss_ops); 1858 1859 if (IS_ERR(clk)) 1860 kfree(pll); 1861 1862 return clk; 1863 } 1864 #endif 1865