1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 #define PLLE_BASE_ENABLE BIT(31) 69 70 #define PLLE_MISC_SETUP_BASE_SHIFT 16 71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 72 #define PLLE_MISC_LOCK_ENABLE BIT(9) 73 #define PLLE_MISC_READY BIT(15) 74 #define PLLE_MISC_SETUP_EX_SHIFT 2 75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 77 PLLE_MISC_SETUP_EX_MASK) 78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 79 80 #define PLLE_SS_CTRL 0x68 81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 83 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 84 #define PLLE_SS_CNTL_CENTER BIT(14) 85 #define PLLE_SS_CNTL_INVERT BIT(15) 86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 87 PLLE_SS_CNTL_SSC_BYP) 88 #define PLLE_SS_MAX_MASK 0x1ff 89 #define PLLE_SS_MAX_VAL 0x25 90 #define PLLE_SS_INC_MASK (0xff << 16) 91 #define PLLE_SS_INC_VAL (0x1 << 16) 92 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 93 #define PLLE_SS_INCINTRV_VAL (0x20 << 24) 94 #define PLLE_SS_COEFFICIENTS_MASK \ 95 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 96 #define PLLE_SS_COEFFICIENTS_VAL \ 97 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) 98 99 #define PLLE_AUX_PLLP_SEL BIT(2) 100 #define PLLE_AUX_USE_LOCKDET BIT(3) 101 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 102 #define PLLE_AUX_SS_SWCTL BIT(6) 103 #define PLLE_AUX_SEQ_ENABLE BIT(24) 104 #define PLLE_AUX_SEQ_START_STATE BIT(25) 105 #define PLLE_AUX_PLLRE_SEL BIT(28) 106 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31) 107 108 #define XUSBIO_PLL_CFG0 0x51c 109 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 110 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 111 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 112 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 113 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 114 115 #define SATA_PLL_CFG0 0x490 116 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 117 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 118 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 119 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 120 121 #define PLLE_MISC_PLLE_PTS BIT(8) 122 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 123 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 124 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 125 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 126 #define PLLE_MISC_VREG_CTRL_SHIFT 2 127 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 128 129 #define PLLCX_MISC_STROBE BIT(31) 130 #define PLLCX_MISC_RESET BIT(30) 131 #define PLLCX_MISC_SDM_DIV_SHIFT 28 132 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 133 #define PLLCX_MISC_FILT_DIV_SHIFT 26 134 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 135 #define PLLCX_MISC_ALPHA_SHIFT 18 136 #define PLLCX_MISC_DIV_LOW_RANGE \ 137 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 138 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 139 #define PLLCX_MISC_DIV_HIGH_RANGE \ 140 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 141 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 142 #define PLLCX_MISC_COEF_LOW_RANGE \ 143 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 144 #define PLLCX_MISC_KA_SHIFT 2 145 #define PLLCX_MISC_KB_SHIFT 9 146 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 147 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 148 PLLCX_MISC_DIV_LOW_RANGE | \ 149 PLLCX_MISC_RESET) 150 #define PLLCX_MISC1_DEFAULT 0x000d2308 151 #define PLLCX_MISC2_DEFAULT 0x30211200 152 #define PLLCX_MISC3_DEFAULT 0x200 153 154 #define PMC_SATA_PWRGT 0x1ac 155 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 156 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 157 158 #define PLLSS_MISC_KCP 0 159 #define PLLSS_MISC_KVCO 0 160 #define PLLSS_MISC_SETUP 0 161 #define PLLSS_EN_SDM 0 162 #define PLLSS_EN_SSC 0 163 #define PLLSS_EN_DITHER2 0 164 #define PLLSS_EN_DITHER 1 165 #define PLLSS_SDM_RESET 0 166 #define PLLSS_CLAMP 0 167 #define PLLSS_SDM_SSC_MAX 0 168 #define PLLSS_SDM_SSC_MIN 0 169 #define PLLSS_SDM_SSC_STEP 0 170 #define PLLSS_SDM_DIN 0 171 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 172 (PLLSS_MISC_KVCO << 24) | \ 173 PLLSS_MISC_SETUP) 174 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 175 (PLLSS_EN_SSC << 30) | \ 176 (PLLSS_EN_DITHER2 << 29) | \ 177 (PLLSS_EN_DITHER << 28) | \ 178 (PLLSS_SDM_RESET) << 27 | \ 179 (PLLSS_CLAMP << 22)) 180 #define PLLSS_CTRL1_DEFAULT \ 181 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 182 #define PLLSS_CTRL2_DEFAULT \ 183 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 184 #define PLLSS_LOCK_OVERRIDE BIT(24) 185 #define PLLSS_REF_SRC_SEL_SHIFT 25 186 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 187 188 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 189 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 190 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 191 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 192 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p) 193 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p) 194 195 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 196 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 197 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 198 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 199 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) 200 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) 201 202 #define mask(w) ((1 << (w)) - 1) 203 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 204 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 205 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 206 mask(p->params->div_nmp->divp_width)) 207 #define sdm_din_mask(p) p->params->sdm_din_mask 208 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask 209 210 #define divm_shift(p) (p)->params->div_nmp->divm_shift 211 #define divn_shift(p) (p)->params->div_nmp->divn_shift 212 #define divp_shift(p) (p)->params->div_nmp->divp_shift 213 214 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 215 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 216 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 217 218 #define divm_max(p) (divm_mask(p)) 219 #define divn_max(p) (divn_mask(p)) 220 #define divp_max(p) (1 << (divp_mask(p))) 221 222 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 223 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 224 225 static struct div_nmp default_nmp = { 226 .divn_shift = PLL_BASE_DIVN_SHIFT, 227 .divn_width = PLL_BASE_DIVN_WIDTH, 228 .divm_shift = PLL_BASE_DIVM_SHIFT, 229 .divm_width = PLL_BASE_DIVM_WIDTH, 230 .divp_shift = PLL_BASE_DIVP_SHIFT, 231 .divp_width = PLL_BASE_DIVP_WIDTH, 232 }; 233 234 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 235 { 236 u32 val; 237 238 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 239 return; 240 241 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 242 return; 243 244 val = pll_readl_misc(pll); 245 val |= BIT(pll->params->lock_enable_bit_idx); 246 pll_writel_misc(val, pll); 247 } 248 249 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 250 { 251 int i; 252 u32 val, lock_mask; 253 void __iomem *lock_addr; 254 255 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 256 udelay(pll->params->lock_delay); 257 return 0; 258 } 259 260 lock_addr = pll->clk_base; 261 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 262 lock_addr += pll->params->misc_reg; 263 else 264 lock_addr += pll->params->base_reg; 265 266 lock_mask = pll->params->lock_mask; 267 268 for (i = 0; i < pll->params->lock_delay; i++) { 269 val = readl_relaxed(lock_addr); 270 if ((val & lock_mask) == lock_mask) { 271 udelay(PLL_POST_LOCK_DELAY); 272 return 0; 273 } 274 udelay(2); /* timeout = 2 * lock time */ 275 } 276 277 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 278 clk_hw_get_name(&pll->hw)); 279 280 return -1; 281 } 282 283 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 284 { 285 return clk_pll_wait_for_lock(pll); 286 } 287 288 static int clk_pll_is_enabled(struct clk_hw *hw) 289 { 290 struct tegra_clk_pll *pll = to_clk_pll(hw); 291 u32 val; 292 293 if (pll->params->flags & TEGRA_PLLM) { 294 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 295 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 296 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 297 } 298 299 val = pll_readl_base(pll); 300 301 return val & PLL_BASE_ENABLE ? 1 : 0; 302 } 303 304 static void _clk_pll_enable(struct clk_hw *hw) 305 { 306 struct tegra_clk_pll *pll = to_clk_pll(hw); 307 u32 val; 308 309 if (pll->params->iddq_reg) { 310 val = pll_readl(pll->params->iddq_reg, pll); 311 val &= ~BIT(pll->params->iddq_bit_idx); 312 pll_writel(val, pll->params->iddq_reg, pll); 313 udelay(2); 314 } 315 316 if (pll->params->reset_reg) { 317 val = pll_readl(pll->params->reset_reg, pll); 318 val &= ~BIT(pll->params->reset_bit_idx); 319 pll_writel(val, pll->params->reset_reg, pll); 320 } 321 322 clk_pll_enable_lock(pll); 323 324 val = pll_readl_base(pll); 325 if (pll->params->flags & TEGRA_PLL_BYPASS) 326 val &= ~PLL_BASE_BYPASS; 327 val |= PLL_BASE_ENABLE; 328 pll_writel_base(val, pll); 329 330 if (pll->params->flags & TEGRA_PLLM) { 331 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 332 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 333 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 334 } 335 } 336 337 static void _clk_pll_disable(struct clk_hw *hw) 338 { 339 struct tegra_clk_pll *pll = to_clk_pll(hw); 340 u32 val; 341 342 val = pll_readl_base(pll); 343 if (pll->params->flags & TEGRA_PLL_BYPASS) 344 val &= ~PLL_BASE_BYPASS; 345 val &= ~PLL_BASE_ENABLE; 346 pll_writel_base(val, pll); 347 348 if (pll->params->flags & TEGRA_PLLM) { 349 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 350 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 351 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 352 } 353 354 if (pll->params->reset_reg) { 355 val = pll_readl(pll->params->reset_reg, pll); 356 val |= BIT(pll->params->reset_bit_idx); 357 pll_writel(val, pll->params->reset_reg, pll); 358 } 359 360 if (pll->params->iddq_reg) { 361 val = pll_readl(pll->params->iddq_reg, pll); 362 val |= BIT(pll->params->iddq_bit_idx); 363 pll_writel(val, pll->params->iddq_reg, pll); 364 udelay(2); 365 } 366 } 367 368 static int clk_pll_enable(struct clk_hw *hw) 369 { 370 struct tegra_clk_pll *pll = to_clk_pll(hw); 371 unsigned long flags = 0; 372 int ret; 373 374 if (pll->lock) 375 spin_lock_irqsave(pll->lock, flags); 376 377 _clk_pll_enable(hw); 378 379 ret = clk_pll_wait_for_lock(pll); 380 381 if (pll->lock) 382 spin_unlock_irqrestore(pll->lock, flags); 383 384 return ret; 385 } 386 387 static void clk_pll_disable(struct clk_hw *hw) 388 { 389 struct tegra_clk_pll *pll = to_clk_pll(hw); 390 unsigned long flags = 0; 391 392 if (pll->lock) 393 spin_lock_irqsave(pll->lock, flags); 394 395 _clk_pll_disable(hw); 396 397 if (pll->lock) 398 spin_unlock_irqrestore(pll->lock, flags); 399 } 400 401 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 402 { 403 struct tegra_clk_pll *pll = to_clk_pll(hw); 404 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 405 406 if (p_tohw) { 407 while (p_tohw->pdiv) { 408 if (p_div <= p_tohw->pdiv) 409 return p_tohw->hw_val; 410 p_tohw++; 411 } 412 return -EINVAL; 413 } 414 return -EINVAL; 415 } 416 417 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 418 { 419 struct tegra_clk_pll *pll = to_clk_pll(hw); 420 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 421 422 if (p_tohw) { 423 while (p_tohw->pdiv) { 424 if (p_div_hw == p_tohw->hw_val) 425 return p_tohw->pdiv; 426 p_tohw++; 427 } 428 return -EINVAL; 429 } 430 431 return 1 << p_div_hw; 432 } 433 434 static int _get_table_rate(struct clk_hw *hw, 435 struct tegra_clk_pll_freq_table *cfg, 436 unsigned long rate, unsigned long parent_rate) 437 { 438 struct tegra_clk_pll *pll = to_clk_pll(hw); 439 struct tegra_clk_pll_freq_table *sel; 440 int p; 441 442 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 443 if (sel->input_rate == parent_rate && 444 sel->output_rate == rate) 445 break; 446 447 if (sel->input_rate == 0) 448 return -EINVAL; 449 450 if (pll->params->pdiv_tohw) { 451 p = _p_div_to_hw(hw, sel->p); 452 if (p < 0) 453 return p; 454 } else { 455 p = ilog2(sel->p); 456 } 457 458 cfg->input_rate = sel->input_rate; 459 cfg->output_rate = sel->output_rate; 460 cfg->m = sel->m; 461 cfg->n = sel->n; 462 cfg->p = p; 463 cfg->cpcon = sel->cpcon; 464 cfg->sdm_data = sel->sdm_data; 465 466 return 0; 467 } 468 469 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 470 unsigned long rate, unsigned long parent_rate) 471 { 472 struct tegra_clk_pll *pll = to_clk_pll(hw); 473 unsigned long cfreq; 474 u32 p_div = 0; 475 int ret; 476 477 switch (parent_rate) { 478 case 12000000: 479 case 26000000: 480 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 481 break; 482 case 13000000: 483 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 484 break; 485 case 16800000: 486 case 19200000: 487 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 488 break; 489 case 9600000: 490 case 28800000: 491 /* 492 * PLL_P_OUT1 rate is not listed in PLLA table 493 */ 494 cfreq = parent_rate / (parent_rate / 1000000); 495 break; 496 default: 497 pr_err("%s Unexpected reference rate %lu\n", 498 __func__, parent_rate); 499 BUG(); 500 } 501 502 /* Raise VCO to guarantee 0.5% accuracy */ 503 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 504 cfg->output_rate <<= 1) 505 p_div++; 506 507 cfg->m = parent_rate / cfreq; 508 cfg->n = cfg->output_rate / cfreq; 509 cfg->cpcon = OUT_OF_TABLE_CPCON; 510 511 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 512 (1 << p_div) > divp_max(pll) 513 || cfg->output_rate > pll->params->vco_max) { 514 return -EINVAL; 515 } 516 517 cfg->output_rate >>= p_div; 518 519 if (pll->params->pdiv_tohw) { 520 ret = _p_div_to_hw(hw, 1 << p_div); 521 if (ret < 0) 522 return ret; 523 else 524 cfg->p = ret; 525 } else 526 cfg->p = p_div; 527 528 return 0; 529 } 530 531 /* 532 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number 533 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as 534 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used 535 * to indicate that SDM is disabled. 536 * 537 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 538 */ 539 static void clk_pll_set_sdm_data(struct clk_hw *hw, 540 struct tegra_clk_pll_freq_table *cfg) 541 { 542 struct tegra_clk_pll *pll = to_clk_pll(hw); 543 u32 val; 544 bool enabled; 545 546 if (!pll->params->sdm_din_reg) 547 return; 548 549 if (cfg->sdm_data) { 550 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); 551 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); 552 pll_writel_sdm_din(val, pll); 553 } 554 555 val = pll_readl_sdm_ctrl(pll); 556 enabled = (val & sdm_en_mask(pll)); 557 558 if (cfg->sdm_data == 0 && enabled) 559 val &= ~pll->params->sdm_ctrl_en_mask; 560 561 if (cfg->sdm_data != 0 && !enabled) 562 val |= pll->params->sdm_ctrl_en_mask; 563 564 pll_writel_sdm_ctrl(val, pll); 565 } 566 567 static void _update_pll_mnp(struct tegra_clk_pll *pll, 568 struct tegra_clk_pll_freq_table *cfg) 569 { 570 u32 val; 571 struct tegra_clk_pll_params *params = pll->params; 572 struct div_nmp *div_nmp = params->div_nmp; 573 574 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 575 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 576 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 577 val = pll_override_readl(params->pmc_divp_reg, pll); 578 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 579 val |= cfg->p << div_nmp->override_divp_shift; 580 pll_override_writel(val, params->pmc_divp_reg, pll); 581 582 val = pll_override_readl(params->pmc_divnm_reg, pll); 583 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | 584 ~(divn_mask(pll) << div_nmp->override_divn_shift); 585 val |= (cfg->m << div_nmp->override_divm_shift) | 586 (cfg->n << div_nmp->override_divn_shift); 587 pll_override_writel(val, params->pmc_divnm_reg, pll); 588 } else { 589 val = pll_readl_base(pll); 590 591 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 592 divp_mask_shifted(pll)); 593 594 val |= (cfg->m << divm_shift(pll)) | 595 (cfg->n << divn_shift(pll)) | 596 (cfg->p << divp_shift(pll)); 597 598 pll_writel_base(val, pll); 599 600 clk_pll_set_sdm_data(&pll->hw, cfg); 601 } 602 } 603 604 static void _get_pll_mnp(struct tegra_clk_pll *pll, 605 struct tegra_clk_pll_freq_table *cfg) 606 { 607 u32 val; 608 struct tegra_clk_pll_params *params = pll->params; 609 struct div_nmp *div_nmp = params->div_nmp; 610 611 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 612 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 613 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 614 val = pll_override_readl(params->pmc_divp_reg, pll); 615 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 616 617 val = pll_override_readl(params->pmc_divnm_reg, pll); 618 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 619 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 620 } else { 621 val = pll_readl_base(pll); 622 623 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 624 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 625 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 626 627 if (pll->params->sdm_din_reg) { 628 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { 629 val = pll_readl_sdm_din(pll); 630 val &= sdm_din_mask(pll); 631 cfg->sdm_data = sdin_din_to_data(val); 632 } 633 } 634 } 635 } 636 637 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 638 struct tegra_clk_pll_freq_table *cfg, 639 unsigned long rate) 640 { 641 u32 val; 642 643 val = pll_readl_misc(pll); 644 645 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 646 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 647 648 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 649 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 650 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 651 val |= 1 << PLL_MISC_LFCON_SHIFT; 652 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 653 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 654 if (rate >= (pll->params->vco_max >> 1)) 655 val |= 1 << PLL_MISC_DCCON_SHIFT; 656 } 657 658 pll_writel_misc(val, pll); 659 } 660 661 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 662 unsigned long rate) 663 { 664 struct tegra_clk_pll *pll = to_clk_pll(hw); 665 struct tegra_clk_pll_freq_table old_cfg; 666 int state, ret = 0; 667 668 state = clk_pll_is_enabled(hw); 669 670 _get_pll_mnp(pll, &old_cfg); 671 672 if (state && pll->params->defaults_set && pll->params->dyn_ramp && 673 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { 674 ret = pll->params->dyn_ramp(pll, cfg); 675 if (!ret) 676 return 0; 677 } 678 679 if (state) 680 _clk_pll_disable(hw); 681 682 if (!pll->params->defaults_set && pll->params->set_defaults) 683 pll->params->set_defaults(pll); 684 685 _update_pll_mnp(pll, cfg); 686 687 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 688 _update_pll_cpcon(pll, cfg, rate); 689 690 if (state) { 691 _clk_pll_enable(hw); 692 ret = clk_pll_wait_for_lock(pll); 693 } 694 695 return ret; 696 } 697 698 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 699 unsigned long parent_rate) 700 { 701 struct tegra_clk_pll *pll = to_clk_pll(hw); 702 struct tegra_clk_pll_freq_table cfg, old_cfg; 703 unsigned long flags = 0; 704 int ret = 0; 705 706 if (pll->params->flags & TEGRA_PLL_FIXED) { 707 if (rate != pll->params->fixed_rate) { 708 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 709 __func__, clk_hw_get_name(hw), 710 pll->params->fixed_rate, rate); 711 return -EINVAL; 712 } 713 return 0; 714 } 715 716 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 717 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { 718 pr_err("%s: Failed to set %s rate %lu\n", __func__, 719 clk_hw_get_name(hw), rate); 720 WARN_ON(1); 721 return -EINVAL; 722 } 723 if (pll->lock) 724 spin_lock_irqsave(pll->lock, flags); 725 726 _get_pll_mnp(pll, &old_cfg); 727 728 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || 729 old_cfg.sdm_data != cfg.sdm_data) 730 ret = _program_pll(hw, &cfg, rate); 731 732 if (pll->lock) 733 spin_unlock_irqrestore(pll->lock, flags); 734 735 return ret; 736 } 737 738 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 739 unsigned long *prate) 740 { 741 struct tegra_clk_pll *pll = to_clk_pll(hw); 742 struct tegra_clk_pll_freq_table cfg; 743 744 if (pll->params->flags & TEGRA_PLL_FIXED) { 745 /* PLLM/MB are used for memory; we do not change rate */ 746 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) 747 return clk_hw_get_rate(hw); 748 return pll->params->fixed_rate; 749 } 750 751 if (_get_table_rate(hw, &cfg, rate, *prate) && 752 pll->params->calc_rate(hw, &cfg, rate, *prate)) 753 return -EINVAL; 754 755 return cfg.output_rate; 756 } 757 758 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 759 unsigned long parent_rate) 760 { 761 struct tegra_clk_pll *pll = to_clk_pll(hw); 762 struct tegra_clk_pll_freq_table cfg; 763 u32 val; 764 u64 rate = parent_rate; 765 int pdiv; 766 767 val = pll_readl_base(pll); 768 769 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 770 return parent_rate; 771 772 if ((pll->params->flags & TEGRA_PLL_FIXED) && 773 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 774 !(val & PLL_BASE_OVERRIDE)) { 775 struct tegra_clk_pll_freq_table sel; 776 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 777 parent_rate)) { 778 pr_err("Clock %s has unknown fixed frequency\n", 779 clk_hw_get_name(hw)); 780 BUG(); 781 } 782 return pll->params->fixed_rate; 783 } 784 785 _get_pll_mnp(pll, &cfg); 786 787 pdiv = _hw_to_p_div(hw, cfg.p); 788 if (pdiv < 0) { 789 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 790 __clk_get_name(hw->clk), cfg.p); 791 pdiv = 1; 792 } 793 794 if (pll->params->set_gain) 795 pll->params->set_gain(&cfg); 796 797 cfg.m *= pdiv; 798 799 rate *= cfg.n; 800 do_div(rate, cfg.m); 801 802 return rate; 803 } 804 805 static int clk_plle_training(struct tegra_clk_pll *pll) 806 { 807 u32 val; 808 unsigned long timeout; 809 810 if (!pll->pmc) 811 return -ENOSYS; 812 813 /* 814 * PLLE is already disabled, and setup cleared; 815 * create falling edge on PLLE IDDQ input. 816 */ 817 val = readl(pll->pmc + PMC_SATA_PWRGT); 818 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 819 writel(val, pll->pmc + PMC_SATA_PWRGT); 820 821 val = readl(pll->pmc + PMC_SATA_PWRGT); 822 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 823 writel(val, pll->pmc + PMC_SATA_PWRGT); 824 825 val = readl(pll->pmc + PMC_SATA_PWRGT); 826 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 827 writel(val, pll->pmc + PMC_SATA_PWRGT); 828 829 val = pll_readl_misc(pll); 830 831 timeout = jiffies + msecs_to_jiffies(100); 832 while (1) { 833 val = pll_readl_misc(pll); 834 if (val & PLLE_MISC_READY) 835 break; 836 if (time_after(jiffies, timeout)) { 837 pr_err("%s: timeout waiting for PLLE\n", __func__); 838 return -EBUSY; 839 } 840 udelay(300); 841 } 842 843 return 0; 844 } 845 846 static int clk_plle_enable(struct clk_hw *hw) 847 { 848 struct tegra_clk_pll *pll = to_clk_pll(hw); 849 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 850 struct tegra_clk_pll_freq_table sel; 851 u32 val; 852 int err; 853 854 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 855 return -EINVAL; 856 857 clk_pll_disable(hw); 858 859 val = pll_readl_misc(pll); 860 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 861 pll_writel_misc(val, pll); 862 863 val = pll_readl_misc(pll); 864 if (!(val & PLLE_MISC_READY)) { 865 err = clk_plle_training(pll); 866 if (err) 867 return err; 868 } 869 870 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 871 /* configure dividers */ 872 val = pll_readl_base(pll); 873 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 874 divm_mask_shifted(pll)); 875 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 876 val |= sel.m << divm_shift(pll); 877 val |= sel.n << divn_shift(pll); 878 val |= sel.p << divp_shift(pll); 879 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 880 pll_writel_base(val, pll); 881 } 882 883 val = pll_readl_misc(pll); 884 val |= PLLE_MISC_SETUP_VALUE; 885 val |= PLLE_MISC_LOCK_ENABLE; 886 pll_writel_misc(val, pll); 887 888 val = readl(pll->clk_base + PLLE_SS_CTRL); 889 val &= ~PLLE_SS_COEFFICIENTS_MASK; 890 val |= PLLE_SS_DISABLE; 891 writel(val, pll->clk_base + PLLE_SS_CTRL); 892 893 val = pll_readl_base(pll); 894 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 895 pll_writel_base(val, pll); 896 897 clk_pll_wait_for_lock(pll); 898 899 return 0; 900 } 901 902 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 903 unsigned long parent_rate) 904 { 905 struct tegra_clk_pll *pll = to_clk_pll(hw); 906 u32 val = pll_readl_base(pll); 907 u32 divn = 0, divm = 0, divp = 0; 908 u64 rate = parent_rate; 909 910 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 911 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 912 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 913 divm *= divp; 914 915 rate *= divn; 916 do_div(rate, divm); 917 return rate; 918 } 919 920 const struct clk_ops tegra_clk_pll_ops = { 921 .is_enabled = clk_pll_is_enabled, 922 .enable = clk_pll_enable, 923 .disable = clk_pll_disable, 924 .recalc_rate = clk_pll_recalc_rate, 925 .round_rate = clk_pll_round_rate, 926 .set_rate = clk_pll_set_rate, 927 }; 928 929 const struct clk_ops tegra_clk_plle_ops = { 930 .recalc_rate = clk_plle_recalc_rate, 931 .is_enabled = clk_pll_is_enabled, 932 .disable = clk_pll_disable, 933 .enable = clk_plle_enable, 934 }; 935 936 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 937 unsigned long parent_rate) 938 { 939 u16 mdiv = parent_rate / pll_params->cf_min; 940 941 if (pll_params->flags & TEGRA_MDIV_NEW) 942 return (!pll_params->mdiv_default ? mdiv : 943 min(mdiv, pll_params->mdiv_default)); 944 945 if (pll_params->mdiv_default) 946 return pll_params->mdiv_default; 947 948 if (parent_rate > pll_params->cf_max) 949 return 2; 950 else 951 return 1; 952 } 953 954 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 955 struct tegra_clk_pll_freq_table *cfg, 956 unsigned long rate, unsigned long parent_rate) 957 { 958 struct tegra_clk_pll *pll = to_clk_pll(hw); 959 unsigned int p; 960 int p_div; 961 962 if (!rate) 963 return -EINVAL; 964 965 p = DIV_ROUND_UP(pll->params->vco_min, rate); 966 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 967 cfg->output_rate = rate * p; 968 cfg->n = cfg->output_rate * cfg->m / parent_rate; 969 cfg->input_rate = parent_rate; 970 971 p_div = _p_div_to_hw(hw, p); 972 if (p_div < 0) 973 return p_div; 974 975 cfg->p = p_div; 976 977 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 978 return -EINVAL; 979 980 return 0; 981 } 982 983 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 984 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 985 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 986 defined(CONFIG_ARCH_TEGRA_210_SOC) 987 988 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) 989 { 990 struct tegra_clk_pll *pll = to_clk_pll(hw); 991 992 return (u16)_pll_fixed_mdiv(pll->params, input_rate); 993 } 994 995 static unsigned long _clip_vco_min(unsigned long vco_min, 996 unsigned long parent_rate) 997 { 998 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 999 } 1000 1001 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1002 void __iomem *clk_base, 1003 unsigned long parent_rate) 1004 { 1005 u32 val; 1006 u32 step_a, step_b; 1007 1008 switch (parent_rate) { 1009 case 12000000: 1010 case 13000000: 1011 case 26000000: 1012 step_a = 0x2B; 1013 step_b = 0x0B; 1014 break; 1015 case 16800000: 1016 step_a = 0x1A; 1017 step_b = 0x09; 1018 break; 1019 case 19200000: 1020 step_a = 0x12; 1021 step_b = 0x08; 1022 break; 1023 default: 1024 pr_err("%s: Unexpected reference rate %lu\n", 1025 __func__, parent_rate); 1026 WARN_ON(1); 1027 return -EINVAL; 1028 } 1029 1030 val = step_a << pll_params->stepa_shift; 1031 val |= step_b << pll_params->stepb_shift; 1032 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1033 1034 return 0; 1035 } 1036 1037 static int _pll_ramp_calc_pll(struct clk_hw *hw, 1038 struct tegra_clk_pll_freq_table *cfg, 1039 unsigned long rate, unsigned long parent_rate) 1040 { 1041 struct tegra_clk_pll *pll = to_clk_pll(hw); 1042 int err = 0; 1043 1044 err = _get_table_rate(hw, cfg, rate, parent_rate); 1045 if (err < 0) 1046 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 1047 else { 1048 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 1049 WARN_ON(1); 1050 err = -EINVAL; 1051 goto out; 1052 } 1053 } 1054 1055 if (cfg->p > pll->params->max_p) 1056 err = -EINVAL; 1057 1058 out: 1059 return err; 1060 } 1061 1062 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 1063 unsigned long parent_rate) 1064 { 1065 struct tegra_clk_pll *pll = to_clk_pll(hw); 1066 struct tegra_clk_pll_freq_table cfg, old_cfg; 1067 unsigned long flags = 0; 1068 int ret; 1069 1070 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1071 if (ret < 0) 1072 return ret; 1073 1074 if (pll->lock) 1075 spin_lock_irqsave(pll->lock, flags); 1076 1077 _get_pll_mnp(pll, &old_cfg); 1078 1079 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1080 ret = _program_pll(hw, &cfg, rate); 1081 1082 if (pll->lock) 1083 spin_unlock_irqrestore(pll->lock, flags); 1084 1085 return ret; 1086 } 1087 1088 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 1089 unsigned long *prate) 1090 { 1091 struct tegra_clk_pll *pll = to_clk_pll(hw); 1092 struct tegra_clk_pll_freq_table cfg; 1093 int ret, p_div; 1094 u64 output_rate = *prate; 1095 1096 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1097 if (ret < 0) 1098 return ret; 1099 1100 p_div = _hw_to_p_div(hw, cfg.p); 1101 if (p_div < 0) 1102 return p_div; 1103 1104 if (pll->params->set_gain) 1105 pll->params->set_gain(&cfg); 1106 1107 output_rate *= cfg.n; 1108 do_div(output_rate, cfg.m * p_div); 1109 1110 return output_rate; 1111 } 1112 1113 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1114 { 1115 u32 val; 1116 1117 val = pll_readl_misc(pll); 1118 val |= PLLCX_MISC_STROBE; 1119 pll_writel_misc(val, pll); 1120 udelay(2); 1121 1122 val &= ~PLLCX_MISC_STROBE; 1123 pll_writel_misc(val, pll); 1124 } 1125 1126 static int clk_pllc_enable(struct clk_hw *hw) 1127 { 1128 struct tegra_clk_pll *pll = to_clk_pll(hw); 1129 u32 val; 1130 int ret; 1131 unsigned long flags = 0; 1132 1133 if (pll->lock) 1134 spin_lock_irqsave(pll->lock, flags); 1135 1136 _clk_pll_enable(hw); 1137 udelay(2); 1138 1139 val = pll_readl_misc(pll); 1140 val &= ~PLLCX_MISC_RESET; 1141 pll_writel_misc(val, pll); 1142 udelay(2); 1143 1144 _pllcx_strobe(pll); 1145 1146 ret = clk_pll_wait_for_lock(pll); 1147 1148 if (pll->lock) 1149 spin_unlock_irqrestore(pll->lock, flags); 1150 1151 return ret; 1152 } 1153 1154 static void _clk_pllc_disable(struct clk_hw *hw) 1155 { 1156 struct tegra_clk_pll *pll = to_clk_pll(hw); 1157 u32 val; 1158 1159 _clk_pll_disable(hw); 1160 1161 val = pll_readl_misc(pll); 1162 val |= PLLCX_MISC_RESET; 1163 pll_writel_misc(val, pll); 1164 udelay(2); 1165 } 1166 1167 static void clk_pllc_disable(struct clk_hw *hw) 1168 { 1169 struct tegra_clk_pll *pll = to_clk_pll(hw); 1170 unsigned long flags = 0; 1171 1172 if (pll->lock) 1173 spin_lock_irqsave(pll->lock, flags); 1174 1175 _clk_pllc_disable(hw); 1176 1177 if (pll->lock) 1178 spin_unlock_irqrestore(pll->lock, flags); 1179 } 1180 1181 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1182 unsigned long input_rate, u32 n) 1183 { 1184 u32 val, n_threshold; 1185 1186 switch (input_rate) { 1187 case 12000000: 1188 n_threshold = 70; 1189 break; 1190 case 13000000: 1191 case 26000000: 1192 n_threshold = 71; 1193 break; 1194 case 16800000: 1195 n_threshold = 55; 1196 break; 1197 case 19200000: 1198 n_threshold = 48; 1199 break; 1200 default: 1201 pr_err("%s: Unexpected reference rate %lu\n", 1202 __func__, input_rate); 1203 return -EINVAL; 1204 } 1205 1206 val = pll_readl_misc(pll); 1207 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1208 val |= n <= n_threshold ? 1209 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1210 pll_writel_misc(val, pll); 1211 1212 return 0; 1213 } 1214 1215 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1216 unsigned long parent_rate) 1217 { 1218 struct tegra_clk_pll_freq_table cfg, old_cfg; 1219 struct tegra_clk_pll *pll = to_clk_pll(hw); 1220 unsigned long flags = 0; 1221 int state, ret = 0; 1222 1223 if (pll->lock) 1224 spin_lock_irqsave(pll->lock, flags); 1225 1226 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1227 if (ret < 0) 1228 goto out; 1229 1230 _get_pll_mnp(pll, &old_cfg); 1231 1232 if (cfg.m != old_cfg.m) { 1233 WARN_ON(1); 1234 goto out; 1235 } 1236 1237 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1238 goto out; 1239 1240 state = clk_pll_is_enabled(hw); 1241 if (state) 1242 _clk_pllc_disable(hw); 1243 1244 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1245 if (ret < 0) 1246 goto out; 1247 1248 _update_pll_mnp(pll, &cfg); 1249 1250 if (state) 1251 ret = clk_pllc_enable(hw); 1252 1253 out: 1254 if (pll->lock) 1255 spin_unlock_irqrestore(pll->lock, flags); 1256 1257 return ret; 1258 } 1259 1260 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1261 struct tegra_clk_pll_freq_table *cfg, 1262 unsigned long rate, unsigned long parent_rate) 1263 { 1264 u16 m, n; 1265 u64 output_rate = parent_rate; 1266 1267 m = _pll_fixed_mdiv(pll->params, parent_rate); 1268 n = rate * m / parent_rate; 1269 1270 output_rate *= n; 1271 do_div(output_rate, m); 1272 1273 if (cfg) { 1274 cfg->m = m; 1275 cfg->n = n; 1276 } 1277 1278 return output_rate; 1279 } 1280 1281 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1282 unsigned long parent_rate) 1283 { 1284 struct tegra_clk_pll_freq_table cfg, old_cfg; 1285 struct tegra_clk_pll *pll = to_clk_pll(hw); 1286 unsigned long flags = 0; 1287 int state, ret = 0; 1288 1289 if (pll->lock) 1290 spin_lock_irqsave(pll->lock, flags); 1291 1292 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1293 _get_pll_mnp(pll, &old_cfg); 1294 cfg.p = old_cfg.p; 1295 1296 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1297 state = clk_pll_is_enabled(hw); 1298 if (state) 1299 _clk_pll_disable(hw); 1300 1301 _update_pll_mnp(pll, &cfg); 1302 1303 if (state) { 1304 _clk_pll_enable(hw); 1305 ret = clk_pll_wait_for_lock(pll); 1306 } 1307 } 1308 1309 if (pll->lock) 1310 spin_unlock_irqrestore(pll->lock, flags); 1311 1312 return ret; 1313 } 1314 1315 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1316 unsigned long parent_rate) 1317 { 1318 struct tegra_clk_pll_freq_table cfg; 1319 struct tegra_clk_pll *pll = to_clk_pll(hw); 1320 u64 rate = parent_rate; 1321 1322 _get_pll_mnp(pll, &cfg); 1323 1324 rate *= cfg.n; 1325 do_div(rate, cfg.m); 1326 1327 return rate; 1328 } 1329 1330 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1331 unsigned long *prate) 1332 { 1333 struct tegra_clk_pll *pll = to_clk_pll(hw); 1334 1335 return _pllre_calc_rate(pll, NULL, rate, *prate); 1336 } 1337 1338 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1339 { 1340 struct tegra_clk_pll *pll = to_clk_pll(hw); 1341 struct tegra_clk_pll_freq_table sel; 1342 u32 val; 1343 int ret; 1344 unsigned long flags = 0; 1345 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1346 1347 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1348 return -EINVAL; 1349 1350 if (pll->lock) 1351 spin_lock_irqsave(pll->lock, flags); 1352 1353 val = pll_readl_base(pll); 1354 val &= ~BIT(29); /* Disable lock override */ 1355 pll_writel_base(val, pll); 1356 1357 val = pll_readl(pll->params->aux_reg, pll); 1358 val |= PLLE_AUX_ENABLE_SWCTL; 1359 val &= ~PLLE_AUX_SEQ_ENABLE; 1360 pll_writel(val, pll->params->aux_reg, pll); 1361 udelay(1); 1362 1363 val = pll_readl_misc(pll); 1364 val |= PLLE_MISC_LOCK_ENABLE; 1365 val |= PLLE_MISC_IDDQ_SW_CTRL; 1366 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1367 val |= PLLE_MISC_PLLE_PTS; 1368 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1369 pll_writel_misc(val, pll); 1370 udelay(5); 1371 1372 val = pll_readl(PLLE_SS_CTRL, pll); 1373 val |= PLLE_SS_DISABLE; 1374 pll_writel(val, PLLE_SS_CTRL, pll); 1375 1376 val = pll_readl_base(pll); 1377 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1378 divm_mask_shifted(pll)); 1379 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1380 val |= sel.m << divm_shift(pll); 1381 val |= sel.n << divn_shift(pll); 1382 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1383 pll_writel_base(val, pll); 1384 udelay(1); 1385 1386 _clk_pll_enable(hw); 1387 ret = clk_pll_wait_for_lock(pll); 1388 1389 if (ret < 0) 1390 goto out; 1391 1392 val = pll_readl(PLLE_SS_CTRL, pll); 1393 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1394 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1395 val |= PLLE_SS_COEFFICIENTS_VAL; 1396 pll_writel(val, PLLE_SS_CTRL, pll); 1397 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1398 pll_writel(val, PLLE_SS_CTRL, pll); 1399 udelay(1); 1400 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1401 pll_writel(val, PLLE_SS_CTRL, pll); 1402 udelay(1); 1403 1404 /* Enable hw control of xusb brick pll */ 1405 val = pll_readl_misc(pll); 1406 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1407 pll_writel_misc(val, pll); 1408 1409 val = pll_readl(pll->params->aux_reg, pll); 1410 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1411 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1412 pll_writel(val, pll->params->aux_reg, pll); 1413 udelay(1); 1414 val |= PLLE_AUX_SEQ_ENABLE; 1415 pll_writel(val, pll->params->aux_reg, pll); 1416 1417 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1418 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1419 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1420 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1421 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1422 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1423 udelay(1); 1424 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1425 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1426 1427 /* Enable hw control of SATA pll */ 1428 val = pll_readl(SATA_PLL_CFG0, pll); 1429 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1430 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1431 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1432 pll_writel(val, SATA_PLL_CFG0, pll); 1433 1434 udelay(1); 1435 1436 val = pll_readl(SATA_PLL_CFG0, pll); 1437 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1438 pll_writel(val, SATA_PLL_CFG0, pll); 1439 1440 out: 1441 if (pll->lock) 1442 spin_unlock_irqrestore(pll->lock, flags); 1443 1444 return ret; 1445 } 1446 1447 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1448 { 1449 struct tegra_clk_pll *pll = to_clk_pll(hw); 1450 unsigned long flags = 0; 1451 u32 val; 1452 1453 if (pll->lock) 1454 spin_lock_irqsave(pll->lock, flags); 1455 1456 _clk_pll_disable(hw); 1457 1458 val = pll_readl_misc(pll); 1459 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1460 pll_writel_misc(val, pll); 1461 udelay(1); 1462 1463 if (pll->lock) 1464 spin_unlock_irqrestore(pll->lock, flags); 1465 } 1466 #endif 1467 1468 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1469 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1470 spinlock_t *lock) 1471 { 1472 struct tegra_clk_pll *pll; 1473 1474 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1475 if (!pll) 1476 return ERR_PTR(-ENOMEM); 1477 1478 pll->clk_base = clk_base; 1479 pll->pmc = pmc; 1480 1481 pll->params = pll_params; 1482 pll->lock = lock; 1483 1484 if (!pll_params->div_nmp) 1485 pll_params->div_nmp = &default_nmp; 1486 1487 return pll; 1488 } 1489 1490 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1491 const char *name, const char *parent_name, unsigned long flags, 1492 const struct clk_ops *ops) 1493 { 1494 struct clk_init_data init; 1495 1496 init.name = name; 1497 init.ops = ops; 1498 init.flags = flags; 1499 init.parent_names = (parent_name ? &parent_name : NULL); 1500 init.num_parents = (parent_name ? 1 : 0); 1501 1502 /* Default to _calc_rate if unspecified */ 1503 if (!pll->params->calc_rate) { 1504 if (pll->params->flags & TEGRA_PLLM) 1505 pll->params->calc_rate = _calc_dynamic_ramp_rate; 1506 else 1507 pll->params->calc_rate = _calc_rate; 1508 } 1509 1510 if (pll->params->set_defaults) 1511 pll->params->set_defaults(pll); 1512 1513 /* Data in .init is copied by clk_register(), so stack variable OK */ 1514 pll->hw.init = &init; 1515 1516 return clk_register(NULL, &pll->hw); 1517 } 1518 1519 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1520 void __iomem *clk_base, void __iomem *pmc, 1521 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1522 spinlock_t *lock) 1523 { 1524 struct tegra_clk_pll *pll; 1525 struct clk *clk; 1526 1527 pll_params->flags |= TEGRA_PLL_BYPASS; 1528 1529 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1530 if (IS_ERR(pll)) 1531 return ERR_CAST(pll); 1532 1533 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1534 &tegra_clk_pll_ops); 1535 if (IS_ERR(clk)) 1536 kfree(pll); 1537 1538 return clk; 1539 } 1540 1541 static struct div_nmp pll_e_nmp = { 1542 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1543 .divn_width = PLLE_BASE_DIVN_WIDTH, 1544 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1545 .divm_width = PLLE_BASE_DIVM_WIDTH, 1546 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1547 .divp_width = PLLE_BASE_DIVP_WIDTH, 1548 }; 1549 1550 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1551 void __iomem *clk_base, void __iomem *pmc, 1552 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1553 spinlock_t *lock) 1554 { 1555 struct tegra_clk_pll *pll; 1556 struct clk *clk; 1557 1558 pll_params->flags |= TEGRA_PLL_BYPASS; 1559 1560 if (!pll_params->div_nmp) 1561 pll_params->div_nmp = &pll_e_nmp; 1562 1563 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1564 if (IS_ERR(pll)) 1565 return ERR_CAST(pll); 1566 1567 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1568 &tegra_clk_plle_ops); 1569 if (IS_ERR(clk)) 1570 kfree(pll); 1571 1572 return clk; 1573 } 1574 1575 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1576 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1577 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1578 defined(CONFIG_ARCH_TEGRA_210_SOC) 1579 static const struct clk_ops tegra_clk_pllxc_ops = { 1580 .is_enabled = clk_pll_is_enabled, 1581 .enable = clk_pll_enable, 1582 .disable = clk_pll_disable, 1583 .recalc_rate = clk_pll_recalc_rate, 1584 .round_rate = clk_pll_ramp_round_rate, 1585 .set_rate = clk_pllxc_set_rate, 1586 }; 1587 1588 static const struct clk_ops tegra_clk_pllc_ops = { 1589 .is_enabled = clk_pll_is_enabled, 1590 .enable = clk_pllc_enable, 1591 .disable = clk_pllc_disable, 1592 .recalc_rate = clk_pll_recalc_rate, 1593 .round_rate = clk_pll_ramp_round_rate, 1594 .set_rate = clk_pllc_set_rate, 1595 }; 1596 1597 static const struct clk_ops tegra_clk_pllre_ops = { 1598 .is_enabled = clk_pll_is_enabled, 1599 .enable = clk_pll_enable, 1600 .disable = clk_pll_disable, 1601 .recalc_rate = clk_pllre_recalc_rate, 1602 .round_rate = clk_pllre_round_rate, 1603 .set_rate = clk_pllre_set_rate, 1604 }; 1605 1606 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1607 .is_enabled = clk_pll_is_enabled, 1608 .enable = clk_plle_tegra114_enable, 1609 .disable = clk_plle_tegra114_disable, 1610 .recalc_rate = clk_pll_recalc_rate, 1611 }; 1612 1613 1614 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1615 void __iomem *clk_base, void __iomem *pmc, 1616 unsigned long flags, 1617 struct tegra_clk_pll_params *pll_params, 1618 spinlock_t *lock) 1619 { 1620 struct tegra_clk_pll *pll; 1621 struct clk *clk, *parent; 1622 unsigned long parent_rate; 1623 u32 val, val_iddq; 1624 1625 parent = __clk_lookup(parent_name); 1626 if (!parent) { 1627 WARN(1, "parent clk %s of %s must be registered first\n", 1628 parent_name, name); 1629 return ERR_PTR(-EINVAL); 1630 } 1631 1632 if (!pll_params->pdiv_tohw) 1633 return ERR_PTR(-EINVAL); 1634 1635 parent_rate = clk_get_rate(parent); 1636 1637 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1638 1639 if (pll_params->adjust_vco) 1640 pll_params->vco_min = pll_params->adjust_vco(pll_params, 1641 parent_rate); 1642 1643 /* 1644 * If the pll has a set_defaults callback, it will take care of 1645 * configuring dynamic ramping and setting IDDQ in that path. 1646 */ 1647 if (!pll_params->set_defaults) { 1648 int err; 1649 1650 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1651 if (err) 1652 return ERR_PTR(err); 1653 1654 val = readl_relaxed(clk_base + pll_params->base_reg); 1655 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1656 1657 if (val & PLL_BASE_ENABLE) 1658 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1659 else { 1660 val_iddq |= BIT(pll_params->iddq_bit_idx); 1661 writel_relaxed(val_iddq, 1662 clk_base + pll_params->iddq_reg); 1663 } 1664 } 1665 1666 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1667 if (IS_ERR(pll)) 1668 return ERR_CAST(pll); 1669 1670 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1671 &tegra_clk_pllxc_ops); 1672 if (IS_ERR(clk)) 1673 kfree(pll); 1674 1675 return clk; 1676 } 1677 1678 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1679 void __iomem *clk_base, void __iomem *pmc, 1680 unsigned long flags, 1681 struct tegra_clk_pll_params *pll_params, 1682 spinlock_t *lock, unsigned long parent_rate) 1683 { 1684 u32 val; 1685 struct tegra_clk_pll *pll; 1686 struct clk *clk; 1687 1688 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1689 1690 if (pll_params->adjust_vco) 1691 pll_params->vco_min = pll_params->adjust_vco(pll_params, 1692 parent_rate); 1693 1694 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1695 if (IS_ERR(pll)) 1696 return ERR_CAST(pll); 1697 1698 /* program minimum rate by default */ 1699 1700 val = pll_readl_base(pll); 1701 if (val & PLL_BASE_ENABLE) 1702 WARN_ON(val & pll_params->iddq_bit_idx); 1703 else { 1704 int m; 1705 1706 m = _pll_fixed_mdiv(pll_params, parent_rate); 1707 val = m << divm_shift(pll); 1708 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 1709 pll_writel_base(val, pll); 1710 } 1711 1712 /* disable lock override */ 1713 1714 val = pll_readl_misc(pll); 1715 val &= ~BIT(29); 1716 pll_writel_misc(val, pll); 1717 1718 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1719 &tegra_clk_pllre_ops); 1720 if (IS_ERR(clk)) 1721 kfree(pll); 1722 1723 return clk; 1724 } 1725 1726 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1727 void __iomem *clk_base, void __iomem *pmc, 1728 unsigned long flags, 1729 struct tegra_clk_pll_params *pll_params, 1730 spinlock_t *lock) 1731 { 1732 struct tegra_clk_pll *pll; 1733 struct clk *clk, *parent; 1734 unsigned long parent_rate; 1735 1736 if (!pll_params->pdiv_tohw) 1737 return ERR_PTR(-EINVAL); 1738 1739 parent = __clk_lookup(parent_name); 1740 if (!parent) { 1741 WARN(1, "parent clk %s of %s must be registered first\n", 1742 parent_name, name); 1743 return ERR_PTR(-EINVAL); 1744 } 1745 1746 parent_rate = clk_get_rate(parent); 1747 1748 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1749 1750 if (pll_params->adjust_vco) 1751 pll_params->vco_min = pll_params->adjust_vco(pll_params, 1752 parent_rate); 1753 1754 pll_params->flags |= TEGRA_PLL_BYPASS; 1755 pll_params->flags |= TEGRA_PLLM; 1756 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1757 if (IS_ERR(pll)) 1758 return ERR_CAST(pll); 1759 1760 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1761 &tegra_clk_pll_ops); 1762 if (IS_ERR(clk)) 1763 kfree(pll); 1764 1765 return clk; 1766 } 1767 1768 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1769 void __iomem *clk_base, void __iomem *pmc, 1770 unsigned long flags, 1771 struct tegra_clk_pll_params *pll_params, 1772 spinlock_t *lock) 1773 { 1774 struct clk *parent, *clk; 1775 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1776 struct tegra_clk_pll *pll; 1777 struct tegra_clk_pll_freq_table cfg; 1778 unsigned long parent_rate; 1779 1780 if (!p_tohw) 1781 return ERR_PTR(-EINVAL); 1782 1783 parent = __clk_lookup(parent_name); 1784 if (!parent) { 1785 WARN(1, "parent clk %s of %s must be registered first\n", 1786 parent_name, name); 1787 return ERR_PTR(-EINVAL); 1788 } 1789 1790 parent_rate = clk_get_rate(parent); 1791 1792 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1793 1794 pll_params->flags |= TEGRA_PLL_BYPASS; 1795 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1796 if (IS_ERR(pll)) 1797 return ERR_CAST(pll); 1798 1799 /* 1800 * Most of PLLC register fields are shadowed, and can not be read 1801 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1802 * Initialize PLL to default state: disabled, reset; shadow registers 1803 * loaded with default parameters; dividers are preset for half of 1804 * minimum VCO rate (the latter assured that shadowed divider settings 1805 * are within supported range). 1806 */ 1807 1808 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1809 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1810 1811 while (p_tohw->pdiv) { 1812 if (p_tohw->pdiv == 2) { 1813 cfg.p = p_tohw->hw_val; 1814 break; 1815 } 1816 p_tohw++; 1817 } 1818 1819 if (!p_tohw->pdiv) { 1820 WARN_ON(1); 1821 return ERR_PTR(-EINVAL); 1822 } 1823 1824 pll_writel_base(0, pll); 1825 _update_pll_mnp(pll, &cfg); 1826 1827 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1828 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1829 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1830 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1831 1832 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1833 1834 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1835 &tegra_clk_pllc_ops); 1836 if (IS_ERR(clk)) 1837 kfree(pll); 1838 1839 return clk; 1840 } 1841 1842 struct clk *tegra_clk_register_plle_tegra114(const char *name, 1843 const char *parent_name, 1844 void __iomem *clk_base, unsigned long flags, 1845 struct tegra_clk_pll_params *pll_params, 1846 spinlock_t *lock) 1847 { 1848 struct tegra_clk_pll *pll; 1849 struct clk *clk; 1850 u32 val, val_aux; 1851 1852 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1853 if (IS_ERR(pll)) 1854 return ERR_CAST(pll); 1855 1856 /* ensure parent is set to pll_re_vco */ 1857 1858 val = pll_readl_base(pll); 1859 val_aux = pll_readl(pll_params->aux_reg, pll); 1860 1861 if (val & PLL_BASE_ENABLE) { 1862 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1863 (val_aux & PLLE_AUX_PLLP_SEL)) 1864 WARN(1, "pll_e enabled with unsupported parent %s\n", 1865 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1866 "pll_re_vco"); 1867 } else { 1868 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1869 pll_writel(val_aux, pll_params->aux_reg, pll); 1870 } 1871 1872 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1873 &tegra_clk_plle_tegra114_ops); 1874 if (IS_ERR(clk)) 1875 kfree(pll); 1876 1877 return clk; 1878 } 1879 #endif 1880 1881 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 1882 static const struct clk_ops tegra_clk_pllss_ops = { 1883 .is_enabled = clk_pll_is_enabled, 1884 .enable = clk_pll_enable, 1885 .disable = clk_pll_disable, 1886 .recalc_rate = clk_pll_recalc_rate, 1887 .round_rate = clk_pll_ramp_round_rate, 1888 .set_rate = clk_pllxc_set_rate, 1889 }; 1890 1891 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 1892 void __iomem *clk_base, unsigned long flags, 1893 struct tegra_clk_pll_params *pll_params, 1894 spinlock_t *lock) 1895 { 1896 struct tegra_clk_pll *pll; 1897 struct clk *clk, *parent; 1898 struct tegra_clk_pll_freq_table cfg; 1899 unsigned long parent_rate; 1900 u32 val; 1901 int i; 1902 1903 if (!pll_params->div_nmp) 1904 return ERR_PTR(-EINVAL); 1905 1906 parent = __clk_lookup(parent_name); 1907 if (!parent) { 1908 WARN(1, "parent clk %s of %s must be registered first\n", 1909 parent_name, name); 1910 return ERR_PTR(-EINVAL); 1911 } 1912 1913 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1914 if (IS_ERR(pll)) 1915 return ERR_CAST(pll); 1916 1917 val = pll_readl_base(pll); 1918 val &= ~PLLSS_REF_SRC_SEL_MASK; 1919 pll_writel_base(val, pll); 1920 1921 parent_rate = clk_get_rate(parent); 1922 1923 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1924 1925 /* initialize PLL to minimum rate */ 1926 1927 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1928 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1929 1930 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 1931 ; 1932 if (!i) { 1933 kfree(pll); 1934 return ERR_PTR(-EINVAL); 1935 } 1936 1937 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 1938 1939 _update_pll_mnp(pll, &cfg); 1940 1941 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 1942 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 1943 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 1944 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1945 1946 val = pll_readl_base(pll); 1947 if (val & PLL_BASE_ENABLE) { 1948 if (val & BIT(pll_params->iddq_bit_idx)) { 1949 WARN(1, "%s is on but IDDQ set\n", name); 1950 kfree(pll); 1951 return ERR_PTR(-EINVAL); 1952 } 1953 } else 1954 val |= BIT(pll_params->iddq_bit_idx); 1955 1956 val &= ~PLLSS_LOCK_OVERRIDE; 1957 pll_writel_base(val, pll); 1958 1959 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1960 &tegra_clk_pllss_ops); 1961 1962 if (IS_ERR(clk)) 1963 kfree(pll); 1964 1965 return clk; 1966 } 1967 #endif 1968 1969 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 1970 static int clk_plle_tegra210_enable(struct clk_hw *hw) 1971 { 1972 struct tegra_clk_pll *pll = to_clk_pll(hw); 1973 struct tegra_clk_pll_freq_table sel; 1974 u32 val; 1975 int ret; 1976 unsigned long flags = 0; 1977 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1978 1979 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1980 return -EINVAL; 1981 1982 if (pll->lock) 1983 spin_lock_irqsave(pll->lock, flags); 1984 1985 val = pll_readl_base(pll); 1986 val &= ~BIT(30); /* Disable lock override */ 1987 pll_writel_base(val, pll); 1988 1989 val = pll_readl(pll->params->aux_reg, pll); 1990 val |= PLLE_AUX_ENABLE_SWCTL; 1991 val &= ~PLLE_AUX_SEQ_ENABLE; 1992 pll_writel(val, pll->params->aux_reg, pll); 1993 udelay(1); 1994 1995 val = pll_readl_misc(pll); 1996 val |= PLLE_MISC_LOCK_ENABLE; 1997 val |= PLLE_MISC_IDDQ_SW_CTRL; 1998 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1999 val |= PLLE_MISC_PLLE_PTS; 2000 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 2001 pll_writel_misc(val, pll); 2002 udelay(5); 2003 2004 val = pll_readl(PLLE_SS_CTRL, pll); 2005 val |= PLLE_SS_DISABLE; 2006 pll_writel(val, PLLE_SS_CTRL, pll); 2007 2008 val = pll_readl_base(pll); 2009 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 2010 divm_mask_shifted(pll)); 2011 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 2012 val |= sel.m << divm_shift(pll); 2013 val |= sel.n << divn_shift(pll); 2014 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 2015 pll_writel_base(val, pll); 2016 udelay(1); 2017 2018 val = pll_readl_base(pll); 2019 val |= PLLE_BASE_ENABLE; 2020 pll_writel_base(val, pll); 2021 2022 ret = clk_pll_wait_for_lock(pll); 2023 2024 if (ret < 0) 2025 goto out; 2026 2027 val = pll_readl(PLLE_SS_CTRL, pll); 2028 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 2029 val &= ~PLLE_SS_COEFFICIENTS_MASK; 2030 val |= PLLE_SS_COEFFICIENTS_VAL; 2031 pll_writel(val, PLLE_SS_CTRL, pll); 2032 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 2033 pll_writel(val, PLLE_SS_CTRL, pll); 2034 udelay(1); 2035 val &= ~PLLE_SS_CNTL_INTERP_RESET; 2036 pll_writel(val, PLLE_SS_CTRL, pll); 2037 udelay(1); 2038 2039 val = pll_readl_misc(pll); 2040 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 2041 pll_writel_misc(val, pll); 2042 2043 val = pll_readl(pll->params->aux_reg, pll); 2044 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); 2045 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 2046 pll_writel(val, pll->params->aux_reg, pll); 2047 udelay(1); 2048 val |= PLLE_AUX_SEQ_ENABLE; 2049 pll_writel(val, pll->params->aux_reg, pll); 2050 2051 out: 2052 if (pll->lock) 2053 spin_unlock_irqrestore(pll->lock, flags); 2054 2055 return ret; 2056 } 2057 2058 static void clk_plle_tegra210_disable(struct clk_hw *hw) 2059 { 2060 struct tegra_clk_pll *pll = to_clk_pll(hw); 2061 unsigned long flags = 0; 2062 u32 val; 2063 2064 if (pll->lock) 2065 spin_lock_irqsave(pll->lock, flags); 2066 2067 val = pll_readl_base(pll); 2068 val &= ~PLLE_BASE_ENABLE; 2069 pll_writel_base(val, pll); 2070 2071 val = pll_readl_misc(pll); 2072 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 2073 pll_writel_misc(val, pll); 2074 udelay(1); 2075 2076 if (pll->lock) 2077 spin_unlock_irqrestore(pll->lock, flags); 2078 } 2079 2080 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw) 2081 { 2082 struct tegra_clk_pll *pll = to_clk_pll(hw); 2083 u32 val; 2084 2085 val = pll_readl_base(pll); 2086 2087 return val & PLLE_BASE_ENABLE ? 1 : 0; 2088 } 2089 2090 static const struct clk_ops tegra_clk_plle_tegra210_ops = { 2091 .is_enabled = clk_plle_tegra210_is_enabled, 2092 .enable = clk_plle_tegra210_enable, 2093 .disable = clk_plle_tegra210_disable, 2094 .recalc_rate = clk_pll_recalc_rate, 2095 }; 2096 2097 struct clk *tegra_clk_register_plle_tegra210(const char *name, 2098 const char *parent_name, 2099 void __iomem *clk_base, unsigned long flags, 2100 struct tegra_clk_pll_params *pll_params, 2101 spinlock_t *lock) 2102 { 2103 struct tegra_clk_pll *pll; 2104 struct clk *clk; 2105 u32 val, val_aux; 2106 2107 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2108 if (IS_ERR(pll)) 2109 return ERR_CAST(pll); 2110 2111 /* ensure parent is set to pll_re_vco */ 2112 2113 val = pll_readl_base(pll); 2114 val_aux = pll_readl(pll_params->aux_reg, pll); 2115 2116 if (val & PLLE_BASE_ENABLE) { 2117 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 2118 (val_aux & PLLE_AUX_PLLP_SEL)) 2119 WARN(1, "pll_e enabled with unsupported parent %s\n", 2120 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 2121 "pll_re_vco"); 2122 } else { 2123 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 2124 pll_writel(val_aux, pll_params->aux_reg, pll); 2125 } 2126 2127 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2128 &tegra_clk_plle_tegra210_ops); 2129 if (IS_ERR(clk)) 2130 kfree(pll); 2131 2132 return clk; 2133 } 2134 2135 struct clk *tegra_clk_register_pllc_tegra210(const char *name, 2136 const char *parent_name, void __iomem *clk_base, 2137 void __iomem *pmc, unsigned long flags, 2138 struct tegra_clk_pll_params *pll_params, 2139 spinlock_t *lock) 2140 { 2141 struct clk *parent, *clk; 2142 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 2143 struct tegra_clk_pll *pll; 2144 unsigned long parent_rate; 2145 2146 if (!p_tohw) 2147 return ERR_PTR(-EINVAL); 2148 2149 parent = __clk_lookup(parent_name); 2150 if (!parent) { 2151 WARN(1, "parent clk %s of %s must be registered first\n", 2152 name, parent_name); 2153 return ERR_PTR(-EINVAL); 2154 } 2155 2156 parent_rate = clk_get_rate(parent); 2157 2158 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2159 2160 if (pll_params->adjust_vco) 2161 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2162 parent_rate); 2163 2164 pll_params->flags |= TEGRA_PLL_BYPASS; 2165 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2166 if (IS_ERR(pll)) 2167 return ERR_CAST(pll); 2168 2169 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2170 &tegra_clk_pll_ops); 2171 if (IS_ERR(clk)) 2172 kfree(pll); 2173 2174 return clk; 2175 } 2176 2177 struct clk *tegra_clk_register_pllxc_tegra210(const char *name, 2178 const char *parent_name, void __iomem *clk_base, 2179 void __iomem *pmc, unsigned long flags, 2180 struct tegra_clk_pll_params *pll_params, 2181 spinlock_t *lock) 2182 { 2183 struct tegra_clk_pll *pll; 2184 struct clk *clk, *parent; 2185 unsigned long parent_rate; 2186 2187 parent = __clk_lookup(parent_name); 2188 if (!parent) { 2189 WARN(1, "parent clk %s of %s must be registered first\n", 2190 name, parent_name); 2191 return ERR_PTR(-EINVAL); 2192 } 2193 2194 if (!pll_params->pdiv_tohw) 2195 return ERR_PTR(-EINVAL); 2196 2197 parent_rate = clk_get_rate(parent); 2198 2199 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2200 2201 if (pll_params->adjust_vco) 2202 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2203 parent_rate); 2204 2205 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2206 if (IS_ERR(pll)) 2207 return ERR_CAST(pll); 2208 2209 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2210 &tegra_clk_pll_ops); 2211 if (IS_ERR(clk)) 2212 kfree(pll); 2213 2214 return clk; 2215 } 2216 2217 struct clk *tegra_clk_register_pllss_tegra210(const char *name, 2218 const char *parent_name, void __iomem *clk_base, 2219 unsigned long flags, 2220 struct tegra_clk_pll_params *pll_params, 2221 spinlock_t *lock) 2222 { 2223 struct tegra_clk_pll *pll; 2224 struct clk *clk, *parent; 2225 struct tegra_clk_pll_freq_table cfg; 2226 unsigned long parent_rate; 2227 u32 val; 2228 int i; 2229 2230 if (!pll_params->div_nmp) 2231 return ERR_PTR(-EINVAL); 2232 2233 parent = __clk_lookup(parent_name); 2234 if (!parent) { 2235 WARN(1, "parent clk %s of %s must be registered first\n", 2236 name, parent_name); 2237 return ERR_PTR(-EINVAL); 2238 } 2239 2240 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2241 if (IS_ERR(pll)) 2242 return ERR_CAST(pll); 2243 2244 val = pll_readl_base(pll); 2245 val &= ~PLLSS_REF_SRC_SEL_MASK; 2246 pll_writel_base(val, pll); 2247 2248 parent_rate = clk_get_rate(parent); 2249 2250 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2251 2252 if (pll_params->adjust_vco) 2253 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2254 parent_rate); 2255 2256 /* initialize PLL to minimum rate */ 2257 2258 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 2259 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 2260 2261 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 2262 ; 2263 if (!i) { 2264 kfree(pll); 2265 return ERR_PTR(-EINVAL); 2266 } 2267 2268 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 2269 2270 _update_pll_mnp(pll, &cfg); 2271 2272 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 2273 2274 val = pll_readl_base(pll); 2275 if (val & PLL_BASE_ENABLE) { 2276 if (val & BIT(pll_params->iddq_bit_idx)) { 2277 WARN(1, "%s is on but IDDQ set\n", name); 2278 kfree(pll); 2279 return ERR_PTR(-EINVAL); 2280 } 2281 } else 2282 val |= BIT(pll_params->iddq_bit_idx); 2283 2284 val &= ~PLLSS_LOCK_OVERRIDE; 2285 pll_writel_base(val, pll); 2286 2287 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2288 &tegra_clk_pll_ops); 2289 2290 if (IS_ERR(clk)) 2291 kfree(pll); 2292 2293 return clk; 2294 } 2295 2296 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 2297 void __iomem *clk_base, void __iomem *pmc, 2298 unsigned long flags, 2299 struct tegra_clk_pll_params *pll_params, 2300 spinlock_t *lock) 2301 { 2302 struct tegra_clk_pll *pll; 2303 struct clk *clk, *parent; 2304 unsigned long parent_rate; 2305 2306 if (!pll_params->pdiv_tohw) 2307 return ERR_PTR(-EINVAL); 2308 2309 parent = __clk_lookup(parent_name); 2310 if (!parent) { 2311 WARN(1, "parent clk %s of %s must be registered first\n", 2312 parent_name, name); 2313 return ERR_PTR(-EINVAL); 2314 } 2315 2316 parent_rate = clk_get_rate(parent); 2317 2318 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2319 2320 if (pll_params->adjust_vco) 2321 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2322 parent_rate); 2323 2324 pll_params->flags |= TEGRA_PLL_BYPASS; 2325 pll_params->flags |= TEGRA_PLLMB; 2326 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2327 if (IS_ERR(pll)) 2328 return ERR_CAST(pll); 2329 2330 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2331 &tegra_clk_pll_ops); 2332 if (IS_ERR(clk)) 2333 kfree(pll); 2334 2335 return clk; 2336 } 2337 #endif 2338