1 /* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include "clk.h" 25 26 #define PLL_BASE_BYPASS BIT(31) 27 #define PLL_BASE_ENABLE BIT(30) 28 #define PLL_BASE_REF_ENABLE BIT(29) 29 #define PLL_BASE_OVERRIDE BIT(28) 30 31 #define PLL_BASE_DIVP_SHIFT 20 32 #define PLL_BASE_DIVP_WIDTH 3 33 #define PLL_BASE_DIVN_SHIFT 8 34 #define PLL_BASE_DIVN_WIDTH 10 35 #define PLL_BASE_DIVM_SHIFT 0 36 #define PLL_BASE_DIVM_WIDTH 5 37 #define PLLU_POST_DIVP_MASK 0x1 38 39 #define PLL_MISC_DCCON_SHIFT 20 40 #define PLL_MISC_CPCON_SHIFT 8 41 #define PLL_MISC_CPCON_WIDTH 4 42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43 #define PLL_MISC_LFCON_SHIFT 4 44 #define PLL_MISC_LFCON_WIDTH 4 45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46 #define PLL_MISC_VCOCON_SHIFT 0 47 #define PLL_MISC_VCOCON_WIDTH 4 48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50 #define OUT_OF_TABLE_CPCON 8 51 52 #define PMC_PLLP_WB0_OVERRIDE 0xf8 53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56 #define PLL_POST_LOCK_DELAY 50 57 58 #define PLLDU_LFCON_SET_DIVN 600 59 60 #define PLLE_BASE_DIVCML_SHIFT 24 61 #define PLLE_BASE_DIVCML_MASK 0xf 62 #define PLLE_BASE_DIVP_SHIFT 16 63 #define PLLE_BASE_DIVP_WIDTH 6 64 #define PLLE_BASE_DIVN_SHIFT 8 65 #define PLLE_BASE_DIVN_WIDTH 8 66 #define PLLE_BASE_DIVM_SHIFT 0 67 #define PLLE_BASE_DIVM_WIDTH 8 68 #define PLLE_BASE_ENABLE BIT(31) 69 70 #define PLLE_MISC_SETUP_BASE_SHIFT 16 71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 72 #define PLLE_MISC_LOCK_ENABLE BIT(9) 73 #define PLLE_MISC_READY BIT(15) 74 #define PLLE_MISC_SETUP_EX_SHIFT 2 75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 77 PLLE_MISC_SETUP_EX_MASK) 78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 79 80 #define PLLE_SS_CTRL 0x68 81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10) 82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11) 83 #define PLLE_SS_CNTL_SSC_BYP BIT(12) 84 #define PLLE_SS_CNTL_CENTER BIT(14) 85 #define PLLE_SS_CNTL_INVERT BIT(15) 86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 87 PLLE_SS_CNTL_SSC_BYP) 88 #define PLLE_SS_MAX_MASK 0x1ff 89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25 90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21 91 #define PLLE_SS_INC_MASK (0xff << 16) 92 #define PLLE_SS_INC_VAL (0x1 << 16) 93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24) 94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24) 95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24) 96 #define PLLE_SS_COEFFICIENTS_MASK \ 97 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \ 99 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\ 100 PLLE_SS_INCINTRV_VAL_TEGRA114) 101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \ 102 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\ 103 PLLE_SS_INCINTRV_VAL_TEGRA210) 104 105 #define PLLE_AUX_PLLP_SEL BIT(2) 106 #define PLLE_AUX_USE_LOCKDET BIT(3) 107 #define PLLE_AUX_ENABLE_SWCTL BIT(4) 108 #define PLLE_AUX_SS_SWCTL BIT(6) 109 #define PLLE_AUX_SEQ_ENABLE BIT(24) 110 #define PLLE_AUX_SEQ_START_STATE BIT(25) 111 #define PLLE_AUX_PLLRE_SEL BIT(28) 112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31) 113 114 #define XUSBIO_PLL_CFG0 0x51c 115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 120 121 #define SATA_PLL_CFG0 0x490 122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 124 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 125 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 126 127 #define PLLE_MISC_PLLE_PTS BIT(8) 128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 129 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 131 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 132 #define PLLE_MISC_VREG_CTRL_SHIFT 2 133 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 134 135 #define PLLCX_MISC_STROBE BIT(31) 136 #define PLLCX_MISC_RESET BIT(30) 137 #define PLLCX_MISC_SDM_DIV_SHIFT 28 138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 139 #define PLLCX_MISC_FILT_DIV_SHIFT 26 140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 141 #define PLLCX_MISC_ALPHA_SHIFT 18 142 #define PLLCX_MISC_DIV_LOW_RANGE \ 143 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 144 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 145 #define PLLCX_MISC_DIV_HIGH_RANGE \ 146 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 147 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 148 #define PLLCX_MISC_COEF_LOW_RANGE \ 149 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 150 #define PLLCX_MISC_KA_SHIFT 2 151 #define PLLCX_MISC_KB_SHIFT 9 152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 153 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 154 PLLCX_MISC_DIV_LOW_RANGE | \ 155 PLLCX_MISC_RESET) 156 #define PLLCX_MISC1_DEFAULT 0x000d2308 157 #define PLLCX_MISC2_DEFAULT 0x30211200 158 #define PLLCX_MISC3_DEFAULT 0x200 159 160 #define PMC_SATA_PWRGT 0x1ac 161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 163 164 #define PLLSS_MISC_KCP 0 165 #define PLLSS_MISC_KVCO 0 166 #define PLLSS_MISC_SETUP 0 167 #define PLLSS_EN_SDM 0 168 #define PLLSS_EN_SSC 0 169 #define PLLSS_EN_DITHER2 0 170 #define PLLSS_EN_DITHER 1 171 #define PLLSS_SDM_RESET 0 172 #define PLLSS_CLAMP 0 173 #define PLLSS_SDM_SSC_MAX 0 174 #define PLLSS_SDM_SSC_MIN 0 175 #define PLLSS_SDM_SSC_STEP 0 176 #define PLLSS_SDM_DIN 0 177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 178 (PLLSS_MISC_KVCO << 24) | \ 179 PLLSS_MISC_SETUP) 180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 181 (PLLSS_EN_SSC << 30) | \ 182 (PLLSS_EN_DITHER2 << 29) | \ 183 (PLLSS_EN_DITHER << 28) | \ 184 (PLLSS_SDM_RESET) << 27 | \ 185 (PLLSS_CLAMP << 22)) 186 #define PLLSS_CTRL1_DEFAULT \ 187 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 188 #define PLLSS_CTRL2_DEFAULT \ 189 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 190 #define PLLSS_LOCK_OVERRIDE BIT(24) 191 #define PLLSS_REF_SRC_SEL_SHIFT 25 192 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 193 194 #define UTMIP_PLL_CFG1 0x484 195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 202 203 #define UTMIP_PLL_CFG2 0x488 204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) 205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) 208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) 210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) 212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) 213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) 214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30) 215 216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c 217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 225 226 #define PLLU_HW_PWRDN_CFG0 0x530 227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) 228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) 231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) 233 234 #define XUSB_PLL_CFG0 0x534 235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff 236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14) 237 238 #define PLLU_BASE_CLKENABLE_USB BIT(21) 239 #define PLLU_BASE_OVERRIDE BIT(24) 240 241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p) 243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p) 246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p) 247 248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) 253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) 254 255 #define mask(w) ((1 << (w)) - 1) 256 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 257 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 259 mask(p->params->div_nmp->divp_width)) 260 #define sdm_din_mask(p) p->params->sdm_din_mask 261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask 262 263 #define divm_shift(p) (p)->params->div_nmp->divm_shift 264 #define divn_shift(p) (p)->params->div_nmp->divn_shift 265 #define divp_shift(p) (p)->params->div_nmp->divp_shift 266 267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 270 271 #define divm_max(p) (divm_mask(p)) 272 #define divn_max(p) (divn_mask(p)) 273 #define divp_max(p) (1 << (divp_mask(p))) 274 275 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 276 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 277 278 static struct div_nmp default_nmp = { 279 .divn_shift = PLL_BASE_DIVN_SHIFT, 280 .divn_width = PLL_BASE_DIVN_WIDTH, 281 .divm_shift = PLL_BASE_DIVM_SHIFT, 282 .divm_width = PLL_BASE_DIVM_WIDTH, 283 .divp_shift = PLL_BASE_DIVP_SHIFT, 284 .divp_width = PLL_BASE_DIVP_WIDTH, 285 }; 286 287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 288 { 289 u32 val; 290 291 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 292 return; 293 294 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 295 return; 296 297 val = pll_readl_misc(pll); 298 val |= BIT(pll->params->lock_enable_bit_idx); 299 pll_writel_misc(val, pll); 300 } 301 302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 303 { 304 int i; 305 u32 val, lock_mask; 306 void __iomem *lock_addr; 307 308 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 309 udelay(pll->params->lock_delay); 310 return 0; 311 } 312 313 lock_addr = pll->clk_base; 314 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 315 lock_addr += pll->params->misc_reg; 316 else 317 lock_addr += pll->params->base_reg; 318 319 lock_mask = pll->params->lock_mask; 320 321 for (i = 0; i < pll->params->lock_delay; i++) { 322 val = readl_relaxed(lock_addr); 323 if ((val & lock_mask) == lock_mask) { 324 udelay(PLL_POST_LOCK_DELAY); 325 return 0; 326 } 327 udelay(2); /* timeout = 2 * lock time */ 328 } 329 330 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 331 clk_hw_get_name(&pll->hw)); 332 333 return -1; 334 } 335 336 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 337 { 338 return clk_pll_wait_for_lock(pll); 339 } 340 341 static int clk_pll_is_enabled(struct clk_hw *hw) 342 { 343 struct tegra_clk_pll *pll = to_clk_pll(hw); 344 u32 val; 345 346 if (pll->params->flags & TEGRA_PLLM) { 347 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 348 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 349 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 350 } 351 352 val = pll_readl_base(pll); 353 354 return val & PLL_BASE_ENABLE ? 1 : 0; 355 } 356 357 static void _clk_pll_enable(struct clk_hw *hw) 358 { 359 struct tegra_clk_pll *pll = to_clk_pll(hw); 360 u32 val; 361 362 if (pll->params->iddq_reg) { 363 val = pll_readl(pll->params->iddq_reg, pll); 364 val &= ~BIT(pll->params->iddq_bit_idx); 365 pll_writel(val, pll->params->iddq_reg, pll); 366 udelay(5); 367 } 368 369 if (pll->params->reset_reg) { 370 val = pll_readl(pll->params->reset_reg, pll); 371 val &= ~BIT(pll->params->reset_bit_idx); 372 pll_writel(val, pll->params->reset_reg, pll); 373 } 374 375 clk_pll_enable_lock(pll); 376 377 val = pll_readl_base(pll); 378 if (pll->params->flags & TEGRA_PLL_BYPASS) 379 val &= ~PLL_BASE_BYPASS; 380 val |= PLL_BASE_ENABLE; 381 pll_writel_base(val, pll); 382 383 if (pll->params->flags & TEGRA_PLLM) { 384 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 385 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 386 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 387 } 388 } 389 390 static void _clk_pll_disable(struct clk_hw *hw) 391 { 392 struct tegra_clk_pll *pll = to_clk_pll(hw); 393 u32 val; 394 395 val = pll_readl_base(pll); 396 if (pll->params->flags & TEGRA_PLL_BYPASS) 397 val &= ~PLL_BASE_BYPASS; 398 val &= ~PLL_BASE_ENABLE; 399 pll_writel_base(val, pll); 400 401 if (pll->params->flags & TEGRA_PLLM) { 402 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 403 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 404 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 405 } 406 407 if (pll->params->reset_reg) { 408 val = pll_readl(pll->params->reset_reg, pll); 409 val |= BIT(pll->params->reset_bit_idx); 410 pll_writel(val, pll->params->reset_reg, pll); 411 } 412 413 if (pll->params->iddq_reg) { 414 val = pll_readl(pll->params->iddq_reg, pll); 415 val |= BIT(pll->params->iddq_bit_idx); 416 pll_writel(val, pll->params->iddq_reg, pll); 417 udelay(2); 418 } 419 } 420 421 static void pll_clk_start_ss(struct tegra_clk_pll *pll) 422 { 423 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { 424 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); 425 426 val |= pll->params->ssc_ctrl_en_mask; 427 pll_writel(val, pll->params->ssc_ctrl_reg, pll); 428 } 429 } 430 431 static void pll_clk_stop_ss(struct tegra_clk_pll *pll) 432 { 433 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { 434 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); 435 436 val &= ~pll->params->ssc_ctrl_en_mask; 437 pll_writel(val, pll->params->ssc_ctrl_reg, pll); 438 } 439 } 440 441 static int clk_pll_enable(struct clk_hw *hw) 442 { 443 struct tegra_clk_pll *pll = to_clk_pll(hw); 444 unsigned long flags = 0; 445 int ret; 446 447 if (clk_pll_is_enabled(hw)) 448 return 0; 449 450 if (pll->lock) 451 spin_lock_irqsave(pll->lock, flags); 452 453 _clk_pll_enable(hw); 454 455 ret = clk_pll_wait_for_lock(pll); 456 457 pll_clk_start_ss(pll); 458 459 if (pll->lock) 460 spin_unlock_irqrestore(pll->lock, flags); 461 462 return ret; 463 } 464 465 static void clk_pll_disable(struct clk_hw *hw) 466 { 467 struct tegra_clk_pll *pll = to_clk_pll(hw); 468 unsigned long flags = 0; 469 470 if (pll->lock) 471 spin_lock_irqsave(pll->lock, flags); 472 473 pll_clk_stop_ss(pll); 474 475 _clk_pll_disable(hw); 476 477 if (pll->lock) 478 spin_unlock_irqrestore(pll->lock, flags); 479 } 480 481 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 482 { 483 struct tegra_clk_pll *pll = to_clk_pll(hw); 484 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 485 486 if (p_tohw) { 487 while (p_tohw->pdiv) { 488 if (p_div <= p_tohw->pdiv) 489 return p_tohw->hw_val; 490 p_tohw++; 491 } 492 return -EINVAL; 493 } 494 return -EINVAL; 495 } 496 497 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div) 498 { 499 return _p_div_to_hw(&pll->hw, p_div); 500 } 501 502 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 503 { 504 struct tegra_clk_pll *pll = to_clk_pll(hw); 505 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 506 507 if (p_tohw) { 508 while (p_tohw->pdiv) { 509 if (p_div_hw == p_tohw->hw_val) 510 return p_tohw->pdiv; 511 p_tohw++; 512 } 513 return -EINVAL; 514 } 515 516 return 1 << p_div_hw; 517 } 518 519 static int _get_table_rate(struct clk_hw *hw, 520 struct tegra_clk_pll_freq_table *cfg, 521 unsigned long rate, unsigned long parent_rate) 522 { 523 struct tegra_clk_pll *pll = to_clk_pll(hw); 524 struct tegra_clk_pll_freq_table *sel; 525 int p; 526 527 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 528 if (sel->input_rate == parent_rate && 529 sel->output_rate == rate) 530 break; 531 532 if (sel->input_rate == 0) 533 return -EINVAL; 534 535 if (pll->params->pdiv_tohw) { 536 p = _p_div_to_hw(hw, sel->p); 537 if (p < 0) 538 return p; 539 } else { 540 p = ilog2(sel->p); 541 } 542 543 cfg->input_rate = sel->input_rate; 544 cfg->output_rate = sel->output_rate; 545 cfg->m = sel->m; 546 cfg->n = sel->n; 547 cfg->p = p; 548 cfg->cpcon = sel->cpcon; 549 cfg->sdm_data = sel->sdm_data; 550 551 return 0; 552 } 553 554 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 555 unsigned long rate, unsigned long parent_rate) 556 { 557 struct tegra_clk_pll *pll = to_clk_pll(hw); 558 unsigned long cfreq; 559 u32 p_div = 0; 560 int ret; 561 562 switch (parent_rate) { 563 case 12000000: 564 case 26000000: 565 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 566 break; 567 case 13000000: 568 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 569 break; 570 case 16800000: 571 case 19200000: 572 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 573 break; 574 case 9600000: 575 case 28800000: 576 /* 577 * PLL_P_OUT1 rate is not listed in PLLA table 578 */ 579 cfreq = parent_rate / (parent_rate / 1000000); 580 break; 581 default: 582 pr_err("%s Unexpected reference rate %lu\n", 583 __func__, parent_rate); 584 BUG(); 585 } 586 587 /* Raise VCO to guarantee 0.5% accuracy */ 588 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 589 cfg->output_rate <<= 1) 590 p_div++; 591 592 cfg->m = parent_rate / cfreq; 593 cfg->n = cfg->output_rate / cfreq; 594 cfg->cpcon = OUT_OF_TABLE_CPCON; 595 596 if (cfg->m == 0 || cfg->m > divm_max(pll) || 597 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || 598 cfg->output_rate > pll->params->vco_max) { 599 return -EINVAL; 600 } 601 602 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m); 603 cfg->output_rate >>= p_div; 604 605 if (pll->params->pdiv_tohw) { 606 ret = _p_div_to_hw(hw, 1 << p_div); 607 if (ret < 0) 608 return ret; 609 else 610 cfg->p = ret; 611 } else 612 cfg->p = p_div; 613 614 return 0; 615 } 616 617 /* 618 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number 619 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as 620 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used 621 * to indicate that SDM is disabled. 622 * 623 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 624 */ 625 static void clk_pll_set_sdm_data(struct clk_hw *hw, 626 struct tegra_clk_pll_freq_table *cfg) 627 { 628 struct tegra_clk_pll *pll = to_clk_pll(hw); 629 u32 val; 630 bool enabled; 631 632 if (!pll->params->sdm_din_reg) 633 return; 634 635 if (cfg->sdm_data) { 636 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); 637 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); 638 pll_writel_sdm_din(val, pll); 639 } 640 641 val = pll_readl_sdm_ctrl(pll); 642 enabled = (val & sdm_en_mask(pll)); 643 644 if (cfg->sdm_data == 0 && enabled) 645 val &= ~pll->params->sdm_ctrl_en_mask; 646 647 if (cfg->sdm_data != 0 && !enabled) 648 val |= pll->params->sdm_ctrl_en_mask; 649 650 pll_writel_sdm_ctrl(val, pll); 651 } 652 653 static void _update_pll_mnp(struct tegra_clk_pll *pll, 654 struct tegra_clk_pll_freq_table *cfg) 655 { 656 u32 val; 657 struct tegra_clk_pll_params *params = pll->params; 658 struct div_nmp *div_nmp = params->div_nmp; 659 660 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 661 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 662 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 663 val = pll_override_readl(params->pmc_divp_reg, pll); 664 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 665 val |= cfg->p << div_nmp->override_divp_shift; 666 pll_override_writel(val, params->pmc_divp_reg, pll); 667 668 val = pll_override_readl(params->pmc_divnm_reg, pll); 669 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | 670 (divn_mask(pll) << div_nmp->override_divn_shift)); 671 val |= (cfg->m << div_nmp->override_divm_shift) | 672 (cfg->n << div_nmp->override_divn_shift); 673 pll_override_writel(val, params->pmc_divnm_reg, pll); 674 } else { 675 val = pll_readl_base(pll); 676 677 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 678 divp_mask_shifted(pll)); 679 680 val |= (cfg->m << divm_shift(pll)) | 681 (cfg->n << divn_shift(pll)) | 682 (cfg->p << divp_shift(pll)); 683 684 pll_writel_base(val, pll); 685 686 clk_pll_set_sdm_data(&pll->hw, cfg); 687 } 688 } 689 690 static void _get_pll_mnp(struct tegra_clk_pll *pll, 691 struct tegra_clk_pll_freq_table *cfg) 692 { 693 u32 val; 694 struct tegra_clk_pll_params *params = pll->params; 695 struct div_nmp *div_nmp = params->div_nmp; 696 697 *cfg = (struct tegra_clk_pll_freq_table) { }; 698 699 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 700 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 701 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 702 val = pll_override_readl(params->pmc_divp_reg, pll); 703 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 704 705 val = pll_override_readl(params->pmc_divnm_reg, pll); 706 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 707 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 708 } else { 709 val = pll_readl_base(pll); 710 711 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 712 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 713 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 714 715 if (pll->params->sdm_din_reg) { 716 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { 717 val = pll_readl_sdm_din(pll); 718 val &= sdm_din_mask(pll); 719 cfg->sdm_data = sdin_din_to_data(val); 720 } 721 } 722 } 723 } 724 725 static void _update_pll_cpcon(struct tegra_clk_pll *pll, 726 struct tegra_clk_pll_freq_table *cfg, 727 unsigned long rate) 728 { 729 u32 val; 730 731 val = pll_readl_misc(pll); 732 733 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 734 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 735 736 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 737 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 738 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 739 val |= 1 << PLL_MISC_LFCON_SHIFT; 740 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 741 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 742 if (rate >= (pll->params->vco_max >> 1)) 743 val |= 1 << PLL_MISC_DCCON_SHIFT; 744 } 745 746 pll_writel_misc(val, pll); 747 } 748 749 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 750 unsigned long rate) 751 { 752 struct tegra_clk_pll *pll = to_clk_pll(hw); 753 struct tegra_clk_pll_freq_table old_cfg; 754 int state, ret = 0; 755 756 state = clk_pll_is_enabled(hw); 757 758 _get_pll_mnp(pll, &old_cfg); 759 760 if (state && pll->params->defaults_set && pll->params->dyn_ramp && 761 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { 762 ret = pll->params->dyn_ramp(pll, cfg); 763 if (!ret) 764 return 0; 765 } 766 767 if (state) { 768 pll_clk_stop_ss(pll); 769 _clk_pll_disable(hw); 770 } 771 772 if (!pll->params->defaults_set && pll->params->set_defaults) 773 pll->params->set_defaults(pll); 774 775 _update_pll_mnp(pll, cfg); 776 777 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 778 _update_pll_cpcon(pll, cfg, rate); 779 780 if (state) { 781 _clk_pll_enable(hw); 782 ret = clk_pll_wait_for_lock(pll); 783 pll_clk_start_ss(pll); 784 } 785 786 return ret; 787 } 788 789 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 790 unsigned long parent_rate) 791 { 792 struct tegra_clk_pll *pll = to_clk_pll(hw); 793 struct tegra_clk_pll_freq_table cfg, old_cfg; 794 unsigned long flags = 0; 795 int ret = 0; 796 797 if (pll->params->flags & TEGRA_PLL_FIXED) { 798 if (rate != pll->params->fixed_rate) { 799 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 800 __func__, clk_hw_get_name(hw), 801 pll->params->fixed_rate, rate); 802 return -EINVAL; 803 } 804 return 0; 805 } 806 807 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 808 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { 809 pr_err("%s: Failed to set %s rate %lu\n", __func__, 810 clk_hw_get_name(hw), rate); 811 WARN_ON(1); 812 return -EINVAL; 813 } 814 if (pll->lock) 815 spin_lock_irqsave(pll->lock, flags); 816 817 _get_pll_mnp(pll, &old_cfg); 818 if (pll->params->flags & TEGRA_PLL_VCO_OUT) 819 cfg.p = old_cfg.p; 820 821 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || 822 old_cfg.sdm_data != cfg.sdm_data) 823 ret = _program_pll(hw, &cfg, rate); 824 825 if (pll->lock) 826 spin_unlock_irqrestore(pll->lock, flags); 827 828 return ret; 829 } 830 831 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 832 unsigned long *prate) 833 { 834 struct tegra_clk_pll *pll = to_clk_pll(hw); 835 struct tegra_clk_pll_freq_table cfg; 836 837 if (pll->params->flags & TEGRA_PLL_FIXED) { 838 /* PLLM/MB are used for memory; we do not change rate */ 839 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) 840 return clk_hw_get_rate(hw); 841 return pll->params->fixed_rate; 842 } 843 844 if (_get_table_rate(hw, &cfg, rate, *prate) && 845 pll->params->calc_rate(hw, &cfg, rate, *prate)) 846 return -EINVAL; 847 848 return cfg.output_rate; 849 } 850 851 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 852 unsigned long parent_rate) 853 { 854 struct tegra_clk_pll *pll = to_clk_pll(hw); 855 struct tegra_clk_pll_freq_table cfg; 856 u32 val; 857 u64 rate = parent_rate; 858 int pdiv; 859 860 val = pll_readl_base(pll); 861 862 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 863 return parent_rate; 864 865 if ((pll->params->flags & TEGRA_PLL_FIXED) && 866 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 867 !(val & PLL_BASE_OVERRIDE)) { 868 struct tegra_clk_pll_freq_table sel; 869 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 870 parent_rate)) { 871 pr_err("Clock %s has unknown fixed frequency\n", 872 clk_hw_get_name(hw)); 873 BUG(); 874 } 875 return pll->params->fixed_rate; 876 } 877 878 _get_pll_mnp(pll, &cfg); 879 880 if (pll->params->flags & TEGRA_PLL_VCO_OUT) { 881 pdiv = 1; 882 } else { 883 pdiv = _hw_to_p_div(hw, cfg.p); 884 if (pdiv < 0) { 885 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 886 clk_hw_get_name(hw), cfg.p); 887 pdiv = 1; 888 } 889 } 890 891 if (pll->params->set_gain) 892 pll->params->set_gain(&cfg); 893 894 cfg.m *= pdiv; 895 896 rate *= cfg.n; 897 do_div(rate, cfg.m); 898 899 return rate; 900 } 901 902 static int clk_plle_training(struct tegra_clk_pll *pll) 903 { 904 u32 val; 905 unsigned long timeout; 906 907 if (!pll->pmc) 908 return -ENOSYS; 909 910 /* 911 * PLLE is already disabled, and setup cleared; 912 * create falling edge on PLLE IDDQ input. 913 */ 914 val = readl(pll->pmc + PMC_SATA_PWRGT); 915 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 916 writel(val, pll->pmc + PMC_SATA_PWRGT); 917 918 val = readl(pll->pmc + PMC_SATA_PWRGT); 919 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 920 writel(val, pll->pmc + PMC_SATA_PWRGT); 921 922 val = readl(pll->pmc + PMC_SATA_PWRGT); 923 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 924 writel(val, pll->pmc + PMC_SATA_PWRGT); 925 926 val = pll_readl_misc(pll); 927 928 timeout = jiffies + msecs_to_jiffies(100); 929 while (1) { 930 val = pll_readl_misc(pll); 931 if (val & PLLE_MISC_READY) 932 break; 933 if (time_after(jiffies, timeout)) { 934 pr_err("%s: timeout waiting for PLLE\n", __func__); 935 return -EBUSY; 936 } 937 udelay(300); 938 } 939 940 return 0; 941 } 942 943 static int clk_plle_enable(struct clk_hw *hw) 944 { 945 struct tegra_clk_pll *pll = to_clk_pll(hw); 946 struct tegra_clk_pll_freq_table sel; 947 unsigned long input_rate; 948 u32 val; 949 int err; 950 951 if (clk_pll_is_enabled(hw)) 952 return 0; 953 954 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 955 956 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 957 return -EINVAL; 958 959 clk_pll_disable(hw); 960 961 val = pll_readl_misc(pll); 962 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 963 pll_writel_misc(val, pll); 964 965 val = pll_readl_misc(pll); 966 if (!(val & PLLE_MISC_READY)) { 967 err = clk_plle_training(pll); 968 if (err) 969 return err; 970 } 971 972 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 973 /* configure dividers */ 974 val = pll_readl_base(pll); 975 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 976 divm_mask_shifted(pll)); 977 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 978 val |= sel.m << divm_shift(pll); 979 val |= sel.n << divn_shift(pll); 980 val |= sel.p << divp_shift(pll); 981 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 982 pll_writel_base(val, pll); 983 } 984 985 val = pll_readl_misc(pll); 986 val |= PLLE_MISC_SETUP_VALUE; 987 val |= PLLE_MISC_LOCK_ENABLE; 988 pll_writel_misc(val, pll); 989 990 val = readl(pll->clk_base + PLLE_SS_CTRL); 991 val &= ~PLLE_SS_COEFFICIENTS_MASK; 992 val |= PLLE_SS_DISABLE; 993 writel(val, pll->clk_base + PLLE_SS_CTRL); 994 995 val = pll_readl_base(pll); 996 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 997 pll_writel_base(val, pll); 998 999 clk_pll_wait_for_lock(pll); 1000 1001 return 0; 1002 } 1003 1004 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 1005 unsigned long parent_rate) 1006 { 1007 struct tegra_clk_pll *pll = to_clk_pll(hw); 1008 u32 val = pll_readl_base(pll); 1009 u32 divn = 0, divm = 0, divp = 0; 1010 u64 rate = parent_rate; 1011 1012 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 1013 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 1014 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 1015 divm *= divp; 1016 1017 rate *= divn; 1018 do_div(rate, divm); 1019 return rate; 1020 } 1021 1022 const struct clk_ops tegra_clk_pll_ops = { 1023 .is_enabled = clk_pll_is_enabled, 1024 .enable = clk_pll_enable, 1025 .disable = clk_pll_disable, 1026 .recalc_rate = clk_pll_recalc_rate, 1027 .round_rate = clk_pll_round_rate, 1028 .set_rate = clk_pll_set_rate, 1029 }; 1030 1031 const struct clk_ops tegra_clk_plle_ops = { 1032 .recalc_rate = clk_plle_recalc_rate, 1033 .is_enabled = clk_pll_is_enabled, 1034 .disable = clk_pll_disable, 1035 .enable = clk_plle_enable, 1036 }; 1037 1038 /* 1039 * Structure defining the fields for USB UTMI clocks Parameters. 1040 */ 1041 struct utmi_clk_param { 1042 /* Oscillator Frequency in Hz */ 1043 u32 osc_frequency; 1044 /* UTMIP PLL Enable Delay Count */ 1045 u8 enable_delay_count; 1046 /* UTMIP PLL Stable count */ 1047 u8 stable_count; 1048 /* UTMIP PLL Active delay count */ 1049 u8 active_delay_count; 1050 /* UTMIP PLL Xtal frequency count */ 1051 u8 xtal_freq_count; 1052 }; 1053 1054 static const struct utmi_clk_param utmi_parameters[] = { 1055 { 1056 .osc_frequency = 13000000, .enable_delay_count = 0x02, 1057 .stable_count = 0x33, .active_delay_count = 0x05, 1058 .xtal_freq_count = 0x7f 1059 }, { 1060 .osc_frequency = 19200000, .enable_delay_count = 0x03, 1061 .stable_count = 0x4b, .active_delay_count = 0x06, 1062 .xtal_freq_count = 0xbb 1063 }, { 1064 .osc_frequency = 12000000, .enable_delay_count = 0x02, 1065 .stable_count = 0x2f, .active_delay_count = 0x04, 1066 .xtal_freq_count = 0x76 1067 }, { 1068 .osc_frequency = 26000000, .enable_delay_count = 0x04, 1069 .stable_count = 0x66, .active_delay_count = 0x09, 1070 .xtal_freq_count = 0xfe 1071 }, { 1072 .osc_frequency = 16800000, .enable_delay_count = 0x03, 1073 .stable_count = 0x41, .active_delay_count = 0x0a, 1074 .xtal_freq_count = 0xa4 1075 }, { 1076 .osc_frequency = 38400000, .enable_delay_count = 0x0, 1077 .stable_count = 0x0, .active_delay_count = 0x6, 1078 .xtal_freq_count = 0x80 1079 }, 1080 }; 1081 1082 static int clk_pllu_enable(struct clk_hw *hw) 1083 { 1084 struct tegra_clk_pll *pll = to_clk_pll(hw); 1085 struct clk_hw *pll_ref = clk_hw_get_parent(hw); 1086 struct clk_hw *osc = clk_hw_get_parent(pll_ref); 1087 const struct utmi_clk_param *params = NULL; 1088 unsigned long flags = 0, input_rate; 1089 unsigned int i; 1090 int ret = 0; 1091 u32 value; 1092 1093 if (!osc) { 1094 pr_err("%s: failed to get OSC clock\n", __func__); 1095 return -EINVAL; 1096 } 1097 1098 input_rate = clk_hw_get_rate(osc); 1099 1100 if (pll->lock) 1101 spin_lock_irqsave(pll->lock, flags); 1102 1103 _clk_pll_enable(hw); 1104 1105 ret = clk_pll_wait_for_lock(pll); 1106 if (ret < 0) 1107 goto out; 1108 1109 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1110 if (input_rate == utmi_parameters[i].osc_frequency) { 1111 params = &utmi_parameters[i]; 1112 break; 1113 } 1114 } 1115 1116 if (!params) { 1117 pr_err("%s: unexpected input rate %lu Hz\n", __func__, 1118 input_rate); 1119 ret = -EINVAL; 1120 goto out; 1121 } 1122 1123 value = pll_readl_base(pll); 1124 value &= ~PLLU_BASE_OVERRIDE; 1125 pll_writel_base(value, pll); 1126 1127 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); 1128 /* Program UTMIP PLL stable and active counts */ 1129 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1130 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); 1131 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1132 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); 1133 /* Remove power downs from UTMIP PLL control bits */ 1134 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1135 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1136 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1137 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); 1138 1139 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); 1140 /* Program UTMIP PLL delay and oscillator frequency counts */ 1141 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1142 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); 1143 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1144 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); 1145 /* Remove power downs from UTMIP PLL control bits */ 1146 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1147 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1148 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1149 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); 1150 1151 out: 1152 if (pll->lock) 1153 spin_unlock_irqrestore(pll->lock, flags); 1154 1155 return ret; 1156 } 1157 1158 static const struct clk_ops tegra_clk_pllu_ops = { 1159 .is_enabled = clk_pll_is_enabled, 1160 .enable = clk_pllu_enable, 1161 .disable = clk_pll_disable, 1162 .recalc_rate = clk_pll_recalc_rate, 1163 .round_rate = clk_pll_round_rate, 1164 .set_rate = clk_pll_set_rate, 1165 }; 1166 1167 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 1168 unsigned long parent_rate) 1169 { 1170 u16 mdiv = parent_rate / pll_params->cf_min; 1171 1172 if (pll_params->flags & TEGRA_MDIV_NEW) 1173 return (!pll_params->mdiv_default ? mdiv : 1174 min(mdiv, pll_params->mdiv_default)); 1175 1176 if (pll_params->mdiv_default) 1177 return pll_params->mdiv_default; 1178 1179 if (parent_rate > pll_params->cf_max) 1180 return 2; 1181 else 1182 return 1; 1183 } 1184 1185 static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 1186 struct tegra_clk_pll_freq_table *cfg, 1187 unsigned long rate, unsigned long parent_rate) 1188 { 1189 struct tegra_clk_pll *pll = to_clk_pll(hw); 1190 unsigned int p; 1191 int p_div; 1192 1193 if (!rate) 1194 return -EINVAL; 1195 1196 p = DIV_ROUND_UP(pll->params->vco_min, rate); 1197 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 1198 cfg->output_rate = rate * p; 1199 cfg->n = cfg->output_rate * cfg->m / parent_rate; 1200 cfg->input_rate = parent_rate; 1201 1202 p_div = _p_div_to_hw(hw, p); 1203 if (p_div < 0) 1204 return p_div; 1205 1206 cfg->p = p_div; 1207 1208 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 1209 return -EINVAL; 1210 1211 return 0; 1212 } 1213 1214 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1215 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1216 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1217 defined(CONFIG_ARCH_TEGRA_210_SOC) 1218 1219 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) 1220 { 1221 struct tegra_clk_pll *pll = to_clk_pll(hw); 1222 1223 return (u16)_pll_fixed_mdiv(pll->params, input_rate); 1224 } 1225 1226 static unsigned long _clip_vco_min(unsigned long vco_min, 1227 unsigned long parent_rate) 1228 { 1229 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 1230 } 1231 1232 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1233 void __iomem *clk_base, 1234 unsigned long parent_rate) 1235 { 1236 u32 val; 1237 u32 step_a, step_b; 1238 1239 switch (parent_rate) { 1240 case 12000000: 1241 case 13000000: 1242 case 26000000: 1243 step_a = 0x2B; 1244 step_b = 0x0B; 1245 break; 1246 case 16800000: 1247 step_a = 0x1A; 1248 step_b = 0x09; 1249 break; 1250 case 19200000: 1251 step_a = 0x12; 1252 step_b = 0x08; 1253 break; 1254 default: 1255 pr_err("%s: Unexpected reference rate %lu\n", 1256 __func__, parent_rate); 1257 WARN_ON(1); 1258 return -EINVAL; 1259 } 1260 1261 val = step_a << pll_params->stepa_shift; 1262 val |= step_b << pll_params->stepb_shift; 1263 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1264 1265 return 0; 1266 } 1267 1268 static int _pll_ramp_calc_pll(struct clk_hw *hw, 1269 struct tegra_clk_pll_freq_table *cfg, 1270 unsigned long rate, unsigned long parent_rate) 1271 { 1272 struct tegra_clk_pll *pll = to_clk_pll(hw); 1273 int err = 0; 1274 1275 err = _get_table_rate(hw, cfg, rate, parent_rate); 1276 if (err < 0) 1277 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 1278 else { 1279 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 1280 WARN_ON(1); 1281 err = -EINVAL; 1282 goto out; 1283 } 1284 } 1285 1286 if (cfg->p > pll->params->max_p) 1287 err = -EINVAL; 1288 1289 out: 1290 return err; 1291 } 1292 1293 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 1294 unsigned long parent_rate) 1295 { 1296 struct tegra_clk_pll *pll = to_clk_pll(hw); 1297 struct tegra_clk_pll_freq_table cfg, old_cfg; 1298 unsigned long flags = 0; 1299 int ret; 1300 1301 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1302 if (ret < 0) 1303 return ret; 1304 1305 if (pll->lock) 1306 spin_lock_irqsave(pll->lock, flags); 1307 1308 _get_pll_mnp(pll, &old_cfg); 1309 if (pll->params->flags & TEGRA_PLL_VCO_OUT) 1310 cfg.p = old_cfg.p; 1311 1312 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1313 ret = _program_pll(hw, &cfg, rate); 1314 1315 if (pll->lock) 1316 spin_unlock_irqrestore(pll->lock, flags); 1317 1318 return ret; 1319 } 1320 1321 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 1322 unsigned long *prate) 1323 { 1324 struct tegra_clk_pll *pll = to_clk_pll(hw); 1325 struct tegra_clk_pll_freq_table cfg; 1326 int ret, p_div; 1327 u64 output_rate = *prate; 1328 1329 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1330 if (ret < 0) 1331 return ret; 1332 1333 p_div = _hw_to_p_div(hw, cfg.p); 1334 if (p_div < 0) 1335 return p_div; 1336 1337 if (pll->params->set_gain) 1338 pll->params->set_gain(&cfg); 1339 1340 output_rate *= cfg.n; 1341 do_div(output_rate, cfg.m * p_div); 1342 1343 return output_rate; 1344 } 1345 1346 static void _pllcx_strobe(struct tegra_clk_pll *pll) 1347 { 1348 u32 val; 1349 1350 val = pll_readl_misc(pll); 1351 val |= PLLCX_MISC_STROBE; 1352 pll_writel_misc(val, pll); 1353 udelay(2); 1354 1355 val &= ~PLLCX_MISC_STROBE; 1356 pll_writel_misc(val, pll); 1357 } 1358 1359 static int clk_pllc_enable(struct clk_hw *hw) 1360 { 1361 struct tegra_clk_pll *pll = to_clk_pll(hw); 1362 u32 val; 1363 int ret; 1364 unsigned long flags = 0; 1365 1366 if (clk_pll_is_enabled(hw)) 1367 return 0; 1368 1369 if (pll->lock) 1370 spin_lock_irqsave(pll->lock, flags); 1371 1372 _clk_pll_enable(hw); 1373 udelay(2); 1374 1375 val = pll_readl_misc(pll); 1376 val &= ~PLLCX_MISC_RESET; 1377 pll_writel_misc(val, pll); 1378 udelay(2); 1379 1380 _pllcx_strobe(pll); 1381 1382 ret = clk_pll_wait_for_lock(pll); 1383 1384 if (pll->lock) 1385 spin_unlock_irqrestore(pll->lock, flags); 1386 1387 return ret; 1388 } 1389 1390 static void _clk_pllc_disable(struct clk_hw *hw) 1391 { 1392 struct tegra_clk_pll *pll = to_clk_pll(hw); 1393 u32 val; 1394 1395 _clk_pll_disable(hw); 1396 1397 val = pll_readl_misc(pll); 1398 val |= PLLCX_MISC_RESET; 1399 pll_writel_misc(val, pll); 1400 udelay(2); 1401 } 1402 1403 static void clk_pllc_disable(struct clk_hw *hw) 1404 { 1405 struct tegra_clk_pll *pll = to_clk_pll(hw); 1406 unsigned long flags = 0; 1407 1408 if (pll->lock) 1409 spin_lock_irqsave(pll->lock, flags); 1410 1411 _clk_pllc_disable(hw); 1412 1413 if (pll->lock) 1414 spin_unlock_irqrestore(pll->lock, flags); 1415 } 1416 1417 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1418 unsigned long input_rate, u32 n) 1419 { 1420 u32 val, n_threshold; 1421 1422 switch (input_rate) { 1423 case 12000000: 1424 n_threshold = 70; 1425 break; 1426 case 13000000: 1427 case 26000000: 1428 n_threshold = 71; 1429 break; 1430 case 16800000: 1431 n_threshold = 55; 1432 break; 1433 case 19200000: 1434 n_threshold = 48; 1435 break; 1436 default: 1437 pr_err("%s: Unexpected reference rate %lu\n", 1438 __func__, input_rate); 1439 return -EINVAL; 1440 } 1441 1442 val = pll_readl_misc(pll); 1443 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1444 val |= n <= n_threshold ? 1445 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1446 pll_writel_misc(val, pll); 1447 1448 return 0; 1449 } 1450 1451 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1452 unsigned long parent_rate) 1453 { 1454 struct tegra_clk_pll_freq_table cfg, old_cfg; 1455 struct tegra_clk_pll *pll = to_clk_pll(hw); 1456 unsigned long flags = 0; 1457 int state, ret = 0; 1458 1459 if (pll->lock) 1460 spin_lock_irqsave(pll->lock, flags); 1461 1462 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1463 if (ret < 0) 1464 goto out; 1465 1466 _get_pll_mnp(pll, &old_cfg); 1467 1468 if (cfg.m != old_cfg.m) { 1469 WARN_ON(1); 1470 goto out; 1471 } 1472 1473 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1474 goto out; 1475 1476 state = clk_pll_is_enabled(hw); 1477 if (state) 1478 _clk_pllc_disable(hw); 1479 1480 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1481 if (ret < 0) 1482 goto out; 1483 1484 _update_pll_mnp(pll, &cfg); 1485 1486 if (state) 1487 ret = clk_pllc_enable(hw); 1488 1489 out: 1490 if (pll->lock) 1491 spin_unlock_irqrestore(pll->lock, flags); 1492 1493 return ret; 1494 } 1495 1496 static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1497 struct tegra_clk_pll_freq_table *cfg, 1498 unsigned long rate, unsigned long parent_rate) 1499 { 1500 u16 m, n; 1501 u64 output_rate = parent_rate; 1502 1503 m = _pll_fixed_mdiv(pll->params, parent_rate); 1504 n = rate * m / parent_rate; 1505 1506 output_rate *= n; 1507 do_div(output_rate, m); 1508 1509 if (cfg) { 1510 cfg->m = m; 1511 cfg->n = n; 1512 } 1513 1514 return output_rate; 1515 } 1516 1517 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1518 unsigned long parent_rate) 1519 { 1520 struct tegra_clk_pll_freq_table cfg, old_cfg; 1521 struct tegra_clk_pll *pll = to_clk_pll(hw); 1522 unsigned long flags = 0; 1523 int state, ret = 0; 1524 1525 if (pll->lock) 1526 spin_lock_irqsave(pll->lock, flags); 1527 1528 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1529 _get_pll_mnp(pll, &old_cfg); 1530 cfg.p = old_cfg.p; 1531 1532 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1533 state = clk_pll_is_enabled(hw); 1534 if (state) 1535 _clk_pll_disable(hw); 1536 1537 _update_pll_mnp(pll, &cfg); 1538 1539 if (state) { 1540 _clk_pll_enable(hw); 1541 ret = clk_pll_wait_for_lock(pll); 1542 } 1543 } 1544 1545 if (pll->lock) 1546 spin_unlock_irqrestore(pll->lock, flags); 1547 1548 return ret; 1549 } 1550 1551 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1552 unsigned long parent_rate) 1553 { 1554 struct tegra_clk_pll_freq_table cfg; 1555 struct tegra_clk_pll *pll = to_clk_pll(hw); 1556 u64 rate = parent_rate; 1557 1558 _get_pll_mnp(pll, &cfg); 1559 1560 rate *= cfg.n; 1561 do_div(rate, cfg.m); 1562 1563 return rate; 1564 } 1565 1566 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1567 unsigned long *prate) 1568 { 1569 struct tegra_clk_pll *pll = to_clk_pll(hw); 1570 1571 return _pllre_calc_rate(pll, NULL, rate, *prate); 1572 } 1573 1574 static int clk_plle_tegra114_enable(struct clk_hw *hw) 1575 { 1576 struct tegra_clk_pll *pll = to_clk_pll(hw); 1577 struct tegra_clk_pll_freq_table sel; 1578 u32 val; 1579 int ret; 1580 unsigned long flags = 0; 1581 unsigned long input_rate; 1582 1583 if (clk_pll_is_enabled(hw)) 1584 return 0; 1585 1586 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 1587 1588 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1589 return -EINVAL; 1590 1591 if (pll->lock) 1592 spin_lock_irqsave(pll->lock, flags); 1593 1594 val = pll_readl_base(pll); 1595 val &= ~BIT(29); /* Disable lock override */ 1596 pll_writel_base(val, pll); 1597 1598 val = pll_readl(pll->params->aux_reg, pll); 1599 val |= PLLE_AUX_ENABLE_SWCTL; 1600 val &= ~PLLE_AUX_SEQ_ENABLE; 1601 pll_writel(val, pll->params->aux_reg, pll); 1602 udelay(1); 1603 1604 val = pll_readl_misc(pll); 1605 val |= PLLE_MISC_LOCK_ENABLE; 1606 val |= PLLE_MISC_IDDQ_SW_CTRL; 1607 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1608 val |= PLLE_MISC_PLLE_PTS; 1609 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); 1610 pll_writel_misc(val, pll); 1611 udelay(5); 1612 1613 val = pll_readl(PLLE_SS_CTRL, pll); 1614 val |= PLLE_SS_DISABLE; 1615 pll_writel(val, PLLE_SS_CTRL, pll); 1616 1617 val = pll_readl_base(pll); 1618 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1619 divm_mask_shifted(pll)); 1620 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1621 val |= sel.m << divm_shift(pll); 1622 val |= sel.n << divn_shift(pll); 1623 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1624 pll_writel_base(val, pll); 1625 udelay(1); 1626 1627 _clk_pll_enable(hw); 1628 ret = clk_pll_wait_for_lock(pll); 1629 1630 if (ret < 0) 1631 goto out; 1632 1633 val = pll_readl(PLLE_SS_CTRL, pll); 1634 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1635 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1636 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114; 1637 pll_writel(val, PLLE_SS_CTRL, pll); 1638 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1639 pll_writel(val, PLLE_SS_CTRL, pll); 1640 udelay(1); 1641 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1642 pll_writel(val, PLLE_SS_CTRL, pll); 1643 udelay(1); 1644 1645 /* Enable hw control of xusb brick pll */ 1646 val = pll_readl_misc(pll); 1647 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1648 pll_writel_misc(val, pll); 1649 1650 val = pll_readl(pll->params->aux_reg, pll); 1651 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1652 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1653 pll_writel(val, pll->params->aux_reg, pll); 1654 udelay(1); 1655 val |= PLLE_AUX_SEQ_ENABLE; 1656 pll_writel(val, pll->params->aux_reg, pll); 1657 1658 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1659 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1660 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1661 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1662 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1663 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1664 udelay(1); 1665 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1666 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1667 1668 /* Enable hw control of SATA pll */ 1669 val = pll_readl(SATA_PLL_CFG0, pll); 1670 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1671 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1672 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1673 pll_writel(val, SATA_PLL_CFG0, pll); 1674 1675 udelay(1); 1676 1677 val = pll_readl(SATA_PLL_CFG0, pll); 1678 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1679 pll_writel(val, SATA_PLL_CFG0, pll); 1680 1681 out: 1682 if (pll->lock) 1683 spin_unlock_irqrestore(pll->lock, flags); 1684 1685 return ret; 1686 } 1687 1688 static void clk_plle_tegra114_disable(struct clk_hw *hw) 1689 { 1690 struct tegra_clk_pll *pll = to_clk_pll(hw); 1691 unsigned long flags = 0; 1692 u32 val; 1693 1694 if (pll->lock) 1695 spin_lock_irqsave(pll->lock, flags); 1696 1697 _clk_pll_disable(hw); 1698 1699 val = pll_readl_misc(pll); 1700 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1701 pll_writel_misc(val, pll); 1702 udelay(1); 1703 1704 if (pll->lock) 1705 spin_unlock_irqrestore(pll->lock, flags); 1706 } 1707 1708 static int clk_pllu_tegra114_enable(struct clk_hw *hw) 1709 { 1710 struct tegra_clk_pll *pll = to_clk_pll(hw); 1711 const struct utmi_clk_param *params = NULL; 1712 struct clk *osc = __clk_lookup("osc"); 1713 unsigned long flags = 0, input_rate; 1714 unsigned int i; 1715 int ret = 0; 1716 u32 value; 1717 1718 if (!osc) { 1719 pr_err("%s: failed to get OSC clock\n", __func__); 1720 return -EINVAL; 1721 } 1722 1723 if (clk_pll_is_enabled(hw)) 1724 return 0; 1725 1726 input_rate = clk_hw_get_rate(__clk_get_hw(osc)); 1727 1728 if (pll->lock) 1729 spin_lock_irqsave(pll->lock, flags); 1730 1731 _clk_pll_enable(hw); 1732 1733 ret = clk_pll_wait_for_lock(pll); 1734 if (ret < 0) 1735 goto out; 1736 1737 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1738 if (input_rate == utmi_parameters[i].osc_frequency) { 1739 params = &utmi_parameters[i]; 1740 break; 1741 } 1742 } 1743 1744 if (!params) { 1745 pr_err("%s: unexpected input rate %lu Hz\n", __func__, 1746 input_rate); 1747 ret = -EINVAL; 1748 goto out; 1749 } 1750 1751 value = pll_readl_base(pll); 1752 value &= ~PLLU_BASE_OVERRIDE; 1753 pll_writel_base(value, pll); 1754 1755 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); 1756 /* Program UTMIP PLL stable and active counts */ 1757 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1758 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); 1759 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1760 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); 1761 /* Remove power downs from UTMIP PLL control bits */ 1762 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1763 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1764 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1765 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); 1766 1767 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); 1768 /* Program UTMIP PLL delay and oscillator frequency counts */ 1769 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1770 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); 1771 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1772 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); 1773 /* Remove power downs from UTMIP PLL control bits */ 1774 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1775 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1776 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1777 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1778 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); 1779 1780 /* Setup HW control of UTMIPLL */ 1781 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1782 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1783 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1784 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1785 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1786 1787 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); 1788 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1789 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1790 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); 1791 1792 udelay(1); 1793 1794 /* 1795 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned 1796 * to USB2 1797 */ 1798 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1799 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1800 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1801 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1802 1803 udelay(1); 1804 1805 /* Enable HW control of UTMIPLL */ 1806 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1807 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1808 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1809 1810 out: 1811 if (pll->lock) 1812 spin_unlock_irqrestore(pll->lock, flags); 1813 1814 return ret; 1815 } 1816 #endif 1817 1818 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1819 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1820 spinlock_t *lock) 1821 { 1822 struct tegra_clk_pll *pll; 1823 1824 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1825 if (!pll) 1826 return ERR_PTR(-ENOMEM); 1827 1828 pll->clk_base = clk_base; 1829 pll->pmc = pmc; 1830 1831 pll->params = pll_params; 1832 pll->lock = lock; 1833 1834 if (!pll_params->div_nmp) 1835 pll_params->div_nmp = &default_nmp; 1836 1837 return pll; 1838 } 1839 1840 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1841 const char *name, const char *parent_name, unsigned long flags, 1842 const struct clk_ops *ops) 1843 { 1844 struct clk_init_data init; 1845 1846 init.name = name; 1847 init.ops = ops; 1848 init.flags = flags; 1849 init.parent_names = (parent_name ? &parent_name : NULL); 1850 init.num_parents = (parent_name ? 1 : 0); 1851 1852 /* Default to _calc_rate if unspecified */ 1853 if (!pll->params->calc_rate) { 1854 if (pll->params->flags & TEGRA_PLLM) 1855 pll->params->calc_rate = _calc_dynamic_ramp_rate; 1856 else 1857 pll->params->calc_rate = _calc_rate; 1858 } 1859 1860 if (pll->params->set_defaults) 1861 pll->params->set_defaults(pll); 1862 1863 /* Data in .init is copied by clk_register(), so stack variable OK */ 1864 pll->hw.init = &init; 1865 1866 return clk_register(NULL, &pll->hw); 1867 } 1868 1869 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1870 void __iomem *clk_base, void __iomem *pmc, 1871 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1872 spinlock_t *lock) 1873 { 1874 struct tegra_clk_pll *pll; 1875 struct clk *clk; 1876 1877 pll_params->flags |= TEGRA_PLL_BYPASS; 1878 1879 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1880 if (IS_ERR(pll)) 1881 return ERR_CAST(pll); 1882 1883 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1884 &tegra_clk_pll_ops); 1885 if (IS_ERR(clk)) 1886 kfree(pll); 1887 1888 return clk; 1889 } 1890 1891 static struct div_nmp pll_e_nmp = { 1892 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1893 .divn_width = PLLE_BASE_DIVN_WIDTH, 1894 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1895 .divm_width = PLLE_BASE_DIVM_WIDTH, 1896 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1897 .divp_width = PLLE_BASE_DIVP_WIDTH, 1898 }; 1899 1900 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1901 void __iomem *clk_base, void __iomem *pmc, 1902 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1903 spinlock_t *lock) 1904 { 1905 struct tegra_clk_pll *pll; 1906 struct clk *clk; 1907 1908 pll_params->flags |= TEGRA_PLL_BYPASS; 1909 1910 if (!pll_params->div_nmp) 1911 pll_params->div_nmp = &pll_e_nmp; 1912 1913 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1914 if (IS_ERR(pll)) 1915 return ERR_CAST(pll); 1916 1917 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1918 &tegra_clk_plle_ops); 1919 if (IS_ERR(clk)) 1920 kfree(pll); 1921 1922 return clk; 1923 } 1924 1925 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name, 1926 void __iomem *clk_base, unsigned long flags, 1927 struct tegra_clk_pll_params *pll_params, spinlock_t *lock) 1928 { 1929 struct tegra_clk_pll *pll; 1930 struct clk *clk; 1931 1932 pll_params->flags |= TEGRA_PLLU; 1933 1934 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1935 if (IS_ERR(pll)) 1936 return ERR_CAST(pll); 1937 1938 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1939 &tegra_clk_pllu_ops); 1940 if (IS_ERR(clk)) 1941 kfree(pll); 1942 1943 return clk; 1944 } 1945 1946 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1947 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1948 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1949 defined(CONFIG_ARCH_TEGRA_210_SOC) 1950 static const struct clk_ops tegra_clk_pllxc_ops = { 1951 .is_enabled = clk_pll_is_enabled, 1952 .enable = clk_pll_enable, 1953 .disable = clk_pll_disable, 1954 .recalc_rate = clk_pll_recalc_rate, 1955 .round_rate = clk_pll_ramp_round_rate, 1956 .set_rate = clk_pllxc_set_rate, 1957 }; 1958 1959 static const struct clk_ops tegra_clk_pllc_ops = { 1960 .is_enabled = clk_pll_is_enabled, 1961 .enable = clk_pllc_enable, 1962 .disable = clk_pllc_disable, 1963 .recalc_rate = clk_pll_recalc_rate, 1964 .round_rate = clk_pll_ramp_round_rate, 1965 .set_rate = clk_pllc_set_rate, 1966 }; 1967 1968 static const struct clk_ops tegra_clk_pllre_ops = { 1969 .is_enabled = clk_pll_is_enabled, 1970 .enable = clk_pll_enable, 1971 .disable = clk_pll_disable, 1972 .recalc_rate = clk_pllre_recalc_rate, 1973 .round_rate = clk_pllre_round_rate, 1974 .set_rate = clk_pllre_set_rate, 1975 }; 1976 1977 static const struct clk_ops tegra_clk_plle_tegra114_ops = { 1978 .is_enabled = clk_pll_is_enabled, 1979 .enable = clk_plle_tegra114_enable, 1980 .disable = clk_plle_tegra114_disable, 1981 .recalc_rate = clk_pll_recalc_rate, 1982 }; 1983 1984 static const struct clk_ops tegra_clk_pllu_tegra114_ops = { 1985 .is_enabled = clk_pll_is_enabled, 1986 .enable = clk_pllu_tegra114_enable, 1987 .disable = clk_pll_disable, 1988 .recalc_rate = clk_pll_recalc_rate, 1989 }; 1990 1991 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1992 void __iomem *clk_base, void __iomem *pmc, 1993 unsigned long flags, 1994 struct tegra_clk_pll_params *pll_params, 1995 spinlock_t *lock) 1996 { 1997 struct tegra_clk_pll *pll; 1998 struct clk *clk, *parent; 1999 unsigned long parent_rate; 2000 u32 val, val_iddq; 2001 2002 parent = __clk_lookup(parent_name); 2003 if (!parent) { 2004 WARN(1, "parent clk %s of %s must be registered first\n", 2005 parent_name, name); 2006 return ERR_PTR(-EINVAL); 2007 } 2008 2009 if (!pll_params->pdiv_tohw) 2010 return ERR_PTR(-EINVAL); 2011 2012 parent_rate = clk_get_rate(parent); 2013 2014 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2015 2016 if (pll_params->adjust_vco) 2017 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2018 parent_rate); 2019 2020 /* 2021 * If the pll has a set_defaults callback, it will take care of 2022 * configuring dynamic ramping and setting IDDQ in that path. 2023 */ 2024 if (!pll_params->set_defaults) { 2025 int err; 2026 2027 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 2028 if (err) 2029 return ERR_PTR(err); 2030 2031 val = readl_relaxed(clk_base + pll_params->base_reg); 2032 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 2033 2034 if (val & PLL_BASE_ENABLE) 2035 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 2036 else { 2037 val_iddq |= BIT(pll_params->iddq_bit_idx); 2038 writel_relaxed(val_iddq, 2039 clk_base + pll_params->iddq_reg); 2040 } 2041 } 2042 2043 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2044 if (IS_ERR(pll)) 2045 return ERR_CAST(pll); 2046 2047 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2048 &tegra_clk_pllxc_ops); 2049 if (IS_ERR(clk)) 2050 kfree(pll); 2051 2052 return clk; 2053 } 2054 2055 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 2056 void __iomem *clk_base, void __iomem *pmc, 2057 unsigned long flags, 2058 struct tegra_clk_pll_params *pll_params, 2059 spinlock_t *lock, unsigned long parent_rate) 2060 { 2061 u32 val; 2062 struct tegra_clk_pll *pll; 2063 struct clk *clk; 2064 2065 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2066 2067 if (pll_params->adjust_vco) 2068 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2069 parent_rate); 2070 2071 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2072 if (IS_ERR(pll)) 2073 return ERR_CAST(pll); 2074 2075 /* program minimum rate by default */ 2076 2077 val = pll_readl_base(pll); 2078 if (val & PLL_BASE_ENABLE) 2079 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & 2080 BIT(pll_params->iddq_bit_idx)); 2081 else { 2082 int m; 2083 2084 m = _pll_fixed_mdiv(pll_params, parent_rate); 2085 val = m << divm_shift(pll); 2086 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 2087 pll_writel_base(val, pll); 2088 } 2089 2090 /* disable lock override */ 2091 2092 val = pll_readl_misc(pll); 2093 val &= ~BIT(29); 2094 pll_writel_misc(val, pll); 2095 2096 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2097 &tegra_clk_pllre_ops); 2098 if (IS_ERR(clk)) 2099 kfree(pll); 2100 2101 return clk; 2102 } 2103 2104 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 2105 void __iomem *clk_base, void __iomem *pmc, 2106 unsigned long flags, 2107 struct tegra_clk_pll_params *pll_params, 2108 spinlock_t *lock) 2109 { 2110 struct tegra_clk_pll *pll; 2111 struct clk *clk, *parent; 2112 unsigned long parent_rate; 2113 2114 if (!pll_params->pdiv_tohw) 2115 return ERR_PTR(-EINVAL); 2116 2117 parent = __clk_lookup(parent_name); 2118 if (!parent) { 2119 WARN(1, "parent clk %s of %s must be registered first\n", 2120 parent_name, name); 2121 return ERR_PTR(-EINVAL); 2122 } 2123 2124 parent_rate = clk_get_rate(parent); 2125 2126 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2127 2128 if (pll_params->adjust_vco) 2129 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2130 parent_rate); 2131 2132 pll_params->flags |= TEGRA_PLL_BYPASS; 2133 pll_params->flags |= TEGRA_PLLM; 2134 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2135 if (IS_ERR(pll)) 2136 return ERR_CAST(pll); 2137 2138 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2139 &tegra_clk_pll_ops); 2140 if (IS_ERR(clk)) 2141 kfree(pll); 2142 2143 return clk; 2144 } 2145 2146 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 2147 void __iomem *clk_base, void __iomem *pmc, 2148 unsigned long flags, 2149 struct tegra_clk_pll_params *pll_params, 2150 spinlock_t *lock) 2151 { 2152 struct clk *parent, *clk; 2153 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 2154 struct tegra_clk_pll *pll; 2155 struct tegra_clk_pll_freq_table cfg; 2156 unsigned long parent_rate; 2157 2158 if (!p_tohw) 2159 return ERR_PTR(-EINVAL); 2160 2161 parent = __clk_lookup(parent_name); 2162 if (!parent) { 2163 WARN(1, "parent clk %s of %s must be registered first\n", 2164 parent_name, name); 2165 return ERR_PTR(-EINVAL); 2166 } 2167 2168 parent_rate = clk_get_rate(parent); 2169 2170 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2171 2172 pll_params->flags |= TEGRA_PLL_BYPASS; 2173 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2174 if (IS_ERR(pll)) 2175 return ERR_CAST(pll); 2176 2177 /* 2178 * Most of PLLC register fields are shadowed, and can not be read 2179 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 2180 * Initialize PLL to default state: disabled, reset; shadow registers 2181 * loaded with default parameters; dividers are preset for half of 2182 * minimum VCO rate (the latter assured that shadowed divider settings 2183 * are within supported range). 2184 */ 2185 2186 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 2187 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 2188 2189 while (p_tohw->pdiv) { 2190 if (p_tohw->pdiv == 2) { 2191 cfg.p = p_tohw->hw_val; 2192 break; 2193 } 2194 p_tohw++; 2195 } 2196 2197 if (!p_tohw->pdiv) { 2198 WARN_ON(1); 2199 return ERR_PTR(-EINVAL); 2200 } 2201 2202 pll_writel_base(0, pll); 2203 _update_pll_mnp(pll, &cfg); 2204 2205 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 2206 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 2207 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 2208 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 2209 2210 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 2211 2212 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2213 &tegra_clk_pllc_ops); 2214 if (IS_ERR(clk)) 2215 kfree(pll); 2216 2217 return clk; 2218 } 2219 2220 struct clk *tegra_clk_register_plle_tegra114(const char *name, 2221 const char *parent_name, 2222 void __iomem *clk_base, unsigned long flags, 2223 struct tegra_clk_pll_params *pll_params, 2224 spinlock_t *lock) 2225 { 2226 struct tegra_clk_pll *pll; 2227 struct clk *clk; 2228 u32 val, val_aux; 2229 2230 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2231 if (IS_ERR(pll)) 2232 return ERR_CAST(pll); 2233 2234 /* ensure parent is set to pll_re_vco */ 2235 2236 val = pll_readl_base(pll); 2237 val_aux = pll_readl(pll_params->aux_reg, pll); 2238 2239 if (val & PLL_BASE_ENABLE) { 2240 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 2241 (val_aux & PLLE_AUX_PLLP_SEL)) 2242 WARN(1, "pll_e enabled with unsupported parent %s\n", 2243 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 2244 "pll_re_vco"); 2245 } else { 2246 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 2247 pll_writel(val_aux, pll_params->aux_reg, pll); 2248 } 2249 2250 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2251 &tegra_clk_plle_tegra114_ops); 2252 if (IS_ERR(clk)) 2253 kfree(pll); 2254 2255 return clk; 2256 } 2257 2258 struct clk * 2259 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name, 2260 void __iomem *clk_base, unsigned long flags, 2261 struct tegra_clk_pll_params *pll_params, 2262 spinlock_t *lock) 2263 { 2264 struct tegra_clk_pll *pll; 2265 struct clk *clk; 2266 2267 pll_params->flags |= TEGRA_PLLU; 2268 2269 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2270 if (IS_ERR(pll)) 2271 return ERR_CAST(pll); 2272 2273 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2274 &tegra_clk_pllu_tegra114_ops); 2275 if (IS_ERR(clk)) 2276 kfree(pll); 2277 2278 return clk; 2279 } 2280 #endif 2281 2282 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC) 2283 static const struct clk_ops tegra_clk_pllss_ops = { 2284 .is_enabled = clk_pll_is_enabled, 2285 .enable = clk_pll_enable, 2286 .disable = clk_pll_disable, 2287 .recalc_rate = clk_pll_recalc_rate, 2288 .round_rate = clk_pll_ramp_round_rate, 2289 .set_rate = clk_pllxc_set_rate, 2290 }; 2291 2292 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 2293 void __iomem *clk_base, unsigned long flags, 2294 struct tegra_clk_pll_params *pll_params, 2295 spinlock_t *lock) 2296 { 2297 struct tegra_clk_pll *pll; 2298 struct clk *clk, *parent; 2299 struct tegra_clk_pll_freq_table cfg; 2300 unsigned long parent_rate; 2301 u32 val, val_iddq; 2302 int i; 2303 2304 if (!pll_params->div_nmp) 2305 return ERR_PTR(-EINVAL); 2306 2307 parent = __clk_lookup(parent_name); 2308 if (!parent) { 2309 WARN(1, "parent clk %s of %s must be registered first\n", 2310 parent_name, name); 2311 return ERR_PTR(-EINVAL); 2312 } 2313 2314 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2315 if (IS_ERR(pll)) 2316 return ERR_CAST(pll); 2317 2318 val = pll_readl_base(pll); 2319 val &= ~PLLSS_REF_SRC_SEL_MASK; 2320 pll_writel_base(val, pll); 2321 2322 parent_rate = clk_get_rate(parent); 2323 2324 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2325 2326 /* initialize PLL to minimum rate */ 2327 2328 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 2329 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 2330 2331 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 2332 ; 2333 if (!i) { 2334 kfree(pll); 2335 return ERR_PTR(-EINVAL); 2336 } 2337 2338 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 2339 2340 _update_pll_mnp(pll, &cfg); 2341 2342 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 2343 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 2344 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 2345 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 2346 2347 val = pll_readl_base(pll); 2348 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 2349 if (val & PLL_BASE_ENABLE) { 2350 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { 2351 WARN(1, "%s is on but IDDQ set\n", name); 2352 kfree(pll); 2353 return ERR_PTR(-EINVAL); 2354 } 2355 } else { 2356 val_iddq |= BIT(pll_params->iddq_bit_idx); 2357 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 2358 } 2359 2360 val &= ~PLLSS_LOCK_OVERRIDE; 2361 pll_writel_base(val, pll); 2362 2363 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2364 &tegra_clk_pllss_ops); 2365 2366 if (IS_ERR(clk)) 2367 kfree(pll); 2368 2369 return clk; 2370 } 2371 #endif 2372 2373 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 2374 struct clk *tegra_clk_register_pllre_tegra210(const char *name, 2375 const char *parent_name, void __iomem *clk_base, 2376 void __iomem *pmc, unsigned long flags, 2377 struct tegra_clk_pll_params *pll_params, 2378 spinlock_t *lock, unsigned long parent_rate) 2379 { 2380 struct tegra_clk_pll *pll; 2381 struct clk *clk; 2382 2383 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2384 2385 if (pll_params->adjust_vco) 2386 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2387 parent_rate); 2388 2389 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2390 if (IS_ERR(pll)) 2391 return ERR_CAST(pll); 2392 2393 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2394 &tegra_clk_pll_ops); 2395 if (IS_ERR(clk)) 2396 kfree(pll); 2397 2398 return clk; 2399 } 2400 2401 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw) 2402 { 2403 struct tegra_clk_pll *pll = to_clk_pll(hw); 2404 u32 val; 2405 2406 val = pll_readl_base(pll); 2407 2408 return val & PLLE_BASE_ENABLE ? 1 : 0; 2409 } 2410 2411 static int clk_plle_tegra210_enable(struct clk_hw *hw) 2412 { 2413 struct tegra_clk_pll *pll = to_clk_pll(hw); 2414 struct tegra_clk_pll_freq_table sel; 2415 u32 val; 2416 int ret = 0; 2417 unsigned long flags = 0; 2418 unsigned long input_rate; 2419 2420 if (clk_plle_tegra210_is_enabled(hw)) 2421 return 0; 2422 2423 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 2424 2425 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 2426 return -EINVAL; 2427 2428 if (pll->lock) 2429 spin_lock_irqsave(pll->lock, flags); 2430 2431 val = pll_readl(pll->params->aux_reg, pll); 2432 if (val & PLLE_AUX_SEQ_ENABLE) 2433 goto out; 2434 2435 val = pll_readl_base(pll); 2436 val &= ~BIT(30); /* Disable lock override */ 2437 pll_writel_base(val, pll); 2438 2439 val = pll_readl_misc(pll); 2440 val |= PLLE_MISC_LOCK_ENABLE; 2441 val |= PLLE_MISC_IDDQ_SW_CTRL; 2442 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 2443 val |= PLLE_MISC_PLLE_PTS; 2444 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); 2445 pll_writel_misc(val, pll); 2446 udelay(5); 2447 2448 val = pll_readl(PLLE_SS_CTRL, pll); 2449 val |= PLLE_SS_DISABLE; 2450 pll_writel(val, PLLE_SS_CTRL, pll); 2451 2452 val = pll_readl_base(pll); 2453 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 2454 divm_mask_shifted(pll)); 2455 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 2456 val |= sel.m << divm_shift(pll); 2457 val |= sel.n << divn_shift(pll); 2458 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 2459 pll_writel_base(val, pll); 2460 udelay(1); 2461 2462 val = pll_readl_base(pll); 2463 val |= PLLE_BASE_ENABLE; 2464 pll_writel_base(val, pll); 2465 2466 ret = clk_pll_wait_for_lock(pll); 2467 2468 if (ret < 0) 2469 goto out; 2470 2471 val = pll_readl(PLLE_SS_CTRL, pll); 2472 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 2473 val &= ~PLLE_SS_COEFFICIENTS_MASK; 2474 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210; 2475 pll_writel(val, PLLE_SS_CTRL, pll); 2476 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 2477 pll_writel(val, PLLE_SS_CTRL, pll); 2478 udelay(1); 2479 val &= ~PLLE_SS_CNTL_INTERP_RESET; 2480 pll_writel(val, PLLE_SS_CTRL, pll); 2481 udelay(1); 2482 2483 val = pll_readl_misc(pll); 2484 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 2485 pll_writel_misc(val, pll); 2486 2487 val = pll_readl(pll->params->aux_reg, pll); 2488 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); 2489 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 2490 pll_writel(val, pll->params->aux_reg, pll); 2491 udelay(1); 2492 val |= PLLE_AUX_SEQ_ENABLE; 2493 pll_writel(val, pll->params->aux_reg, pll); 2494 2495 out: 2496 if (pll->lock) 2497 spin_unlock_irqrestore(pll->lock, flags); 2498 2499 return ret; 2500 } 2501 2502 static void clk_plle_tegra210_disable(struct clk_hw *hw) 2503 { 2504 struct tegra_clk_pll *pll = to_clk_pll(hw); 2505 unsigned long flags = 0; 2506 u32 val; 2507 2508 if (pll->lock) 2509 spin_lock_irqsave(pll->lock, flags); 2510 2511 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */ 2512 val = pll_readl(pll->params->aux_reg, pll); 2513 if (val & PLLE_AUX_SEQ_ENABLE) 2514 goto out; 2515 2516 val = pll_readl_base(pll); 2517 val &= ~PLLE_BASE_ENABLE; 2518 pll_writel_base(val, pll); 2519 2520 val = pll_readl(pll->params->aux_reg, pll); 2521 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL; 2522 pll_writel(val, pll->params->aux_reg, pll); 2523 2524 val = pll_readl_misc(pll); 2525 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 2526 pll_writel_misc(val, pll); 2527 udelay(1); 2528 2529 out: 2530 if (pll->lock) 2531 spin_unlock_irqrestore(pll->lock, flags); 2532 } 2533 2534 static const struct clk_ops tegra_clk_plle_tegra210_ops = { 2535 .is_enabled = clk_plle_tegra210_is_enabled, 2536 .enable = clk_plle_tegra210_enable, 2537 .disable = clk_plle_tegra210_disable, 2538 .recalc_rate = clk_pll_recalc_rate, 2539 }; 2540 2541 struct clk *tegra_clk_register_plle_tegra210(const char *name, 2542 const char *parent_name, 2543 void __iomem *clk_base, unsigned long flags, 2544 struct tegra_clk_pll_params *pll_params, 2545 spinlock_t *lock) 2546 { 2547 struct tegra_clk_pll *pll; 2548 struct clk *clk; 2549 u32 val, val_aux; 2550 2551 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2552 if (IS_ERR(pll)) 2553 return ERR_CAST(pll); 2554 2555 /* ensure parent is set to pll_re_vco */ 2556 2557 val = pll_readl_base(pll); 2558 val_aux = pll_readl(pll_params->aux_reg, pll); 2559 2560 if (val & PLLE_BASE_ENABLE) { 2561 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 2562 (val_aux & PLLE_AUX_PLLP_SEL)) 2563 WARN(1, "pll_e enabled with unsupported parent %s\n", 2564 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 2565 "pll_re_vco"); 2566 } else { 2567 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 2568 pll_writel(val_aux, pll_params->aux_reg, pll); 2569 } 2570 2571 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2572 &tegra_clk_plle_tegra210_ops); 2573 if (IS_ERR(clk)) 2574 kfree(pll); 2575 2576 return clk; 2577 } 2578 2579 struct clk *tegra_clk_register_pllc_tegra210(const char *name, 2580 const char *parent_name, void __iomem *clk_base, 2581 void __iomem *pmc, unsigned long flags, 2582 struct tegra_clk_pll_params *pll_params, 2583 spinlock_t *lock) 2584 { 2585 struct clk *parent, *clk; 2586 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 2587 struct tegra_clk_pll *pll; 2588 unsigned long parent_rate; 2589 2590 if (!p_tohw) 2591 return ERR_PTR(-EINVAL); 2592 2593 parent = __clk_lookup(parent_name); 2594 if (!parent) { 2595 WARN(1, "parent clk %s of %s must be registered first\n", 2596 name, parent_name); 2597 return ERR_PTR(-EINVAL); 2598 } 2599 2600 parent_rate = clk_get_rate(parent); 2601 2602 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2603 2604 if (pll_params->adjust_vco) 2605 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2606 parent_rate); 2607 2608 pll_params->flags |= TEGRA_PLL_BYPASS; 2609 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2610 if (IS_ERR(pll)) 2611 return ERR_CAST(pll); 2612 2613 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2614 &tegra_clk_pll_ops); 2615 if (IS_ERR(clk)) 2616 kfree(pll); 2617 2618 return clk; 2619 } 2620 2621 struct clk *tegra_clk_register_pllss_tegra210(const char *name, 2622 const char *parent_name, void __iomem *clk_base, 2623 unsigned long flags, 2624 struct tegra_clk_pll_params *pll_params, 2625 spinlock_t *lock) 2626 { 2627 struct tegra_clk_pll *pll; 2628 struct clk *clk, *parent; 2629 unsigned long parent_rate; 2630 u32 val; 2631 2632 if (!pll_params->div_nmp) 2633 return ERR_PTR(-EINVAL); 2634 2635 parent = __clk_lookup(parent_name); 2636 if (!parent) { 2637 WARN(1, "parent clk %s of %s must be registered first\n", 2638 name, parent_name); 2639 return ERR_PTR(-EINVAL); 2640 } 2641 2642 val = readl_relaxed(clk_base + pll_params->base_reg); 2643 if (val & PLLSS_REF_SRC_SEL_MASK) { 2644 WARN(1, "not supported reference clock for %s\n", name); 2645 return ERR_PTR(-EINVAL); 2646 } 2647 2648 parent_rate = clk_get_rate(parent); 2649 2650 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2651 2652 if (pll_params->adjust_vco) 2653 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2654 parent_rate); 2655 2656 pll_params->flags |= TEGRA_PLL_BYPASS; 2657 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2658 if (IS_ERR(pll)) 2659 return ERR_CAST(pll); 2660 2661 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2662 &tegra_clk_pll_ops); 2663 2664 if (IS_ERR(clk)) 2665 kfree(pll); 2666 2667 return clk; 2668 } 2669 2670 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 2671 void __iomem *clk_base, void __iomem *pmc, 2672 unsigned long flags, 2673 struct tegra_clk_pll_params *pll_params, 2674 spinlock_t *lock) 2675 { 2676 struct tegra_clk_pll *pll; 2677 struct clk *clk, *parent; 2678 unsigned long parent_rate; 2679 2680 if (!pll_params->pdiv_tohw) 2681 return ERR_PTR(-EINVAL); 2682 2683 parent = __clk_lookup(parent_name); 2684 if (!parent) { 2685 WARN(1, "parent clk %s of %s must be registered first\n", 2686 parent_name, name); 2687 return ERR_PTR(-EINVAL); 2688 } 2689 2690 parent_rate = clk_get_rate(parent); 2691 2692 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2693 2694 if (pll_params->adjust_vco) 2695 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2696 parent_rate); 2697 2698 pll_params->flags |= TEGRA_PLL_BYPASS; 2699 pll_params->flags |= TEGRA_PLLMB; 2700 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2701 if (IS_ERR(pll)) 2702 return ERR_CAST(pll); 2703 2704 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2705 &tegra_clk_pll_ops); 2706 if (IS_ERR(clk)) 2707 kfree(pll); 2708 2709 return clk; 2710 } 2711 2712 #endif 2713