1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/io.h> 8 #include <linux/err.h> 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/clk-provider.h> 12 13 #include "clk.h" 14 15 #define pll_out_enb(p) (BIT(p->enb_bit_idx)) 16 #define pll_out_rst(p) (BIT(p->rst_bit_idx)) 17 18 static int clk_pll_out_is_enabled(struct clk_hw *hw) 19 { 20 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); 21 u32 val = readl_relaxed(pll_out->reg); 22 int state; 23 24 state = (val & pll_out_enb(pll_out)) ? 1 : 0; 25 if (!(val & (pll_out_rst(pll_out)))) 26 state = 0; 27 return state; 28 } 29 30 static int clk_pll_out_enable(struct clk_hw *hw) 31 { 32 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); 33 unsigned long flags = 0; 34 u32 val; 35 36 if (pll_out->lock) 37 spin_lock_irqsave(pll_out->lock, flags); 38 39 val = readl_relaxed(pll_out->reg); 40 41 val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out)); 42 43 writel_relaxed(val, pll_out->reg); 44 udelay(2); 45 46 if (pll_out->lock) 47 spin_unlock_irqrestore(pll_out->lock, flags); 48 49 return 0; 50 } 51 52 static void clk_pll_out_disable(struct clk_hw *hw) 53 { 54 struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw); 55 unsigned long flags = 0; 56 u32 val; 57 58 if (pll_out->lock) 59 spin_lock_irqsave(pll_out->lock, flags); 60 61 val = readl_relaxed(pll_out->reg); 62 63 val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out)); 64 65 writel_relaxed(val, pll_out->reg); 66 udelay(2); 67 68 if (pll_out->lock) 69 spin_unlock_irqrestore(pll_out->lock, flags); 70 } 71 72 const struct clk_ops tegra_clk_pll_out_ops = { 73 .is_enabled = clk_pll_out_is_enabled, 74 .enable = clk_pll_out_enable, 75 .disable = clk_pll_out_disable, 76 }; 77 78 struct clk *tegra_clk_register_pll_out(const char *name, 79 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 80 u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags, 81 spinlock_t *lock) 82 { 83 struct tegra_clk_pll_out *pll_out; 84 struct clk *clk; 85 struct clk_init_data init; 86 87 pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL); 88 if (!pll_out) 89 return ERR_PTR(-ENOMEM); 90 91 init.name = name; 92 init.ops = &tegra_clk_pll_out_ops; 93 init.parent_names = (parent_name ? &parent_name : NULL); 94 init.num_parents = (parent_name ? 1 : 0); 95 init.flags = flags; 96 97 pll_out->reg = reg; 98 pll_out->enb_bit_idx = enb_bit_idx; 99 pll_out->rst_bit_idx = rst_bit_idx; 100 pll_out->flags = pll_out_flags; 101 pll_out->lock = lock; 102 103 /* Data in .init is copied by clk_register(), so stack variable OK */ 104 pll_out->hw.init = &init; 105 106 clk = clk_register(NULL, &pll_out->hw); 107 if (IS_ERR(clk)) 108 kfree(pll_out); 109 110 return clk; 111 } 112