1 /*
2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/io.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 
24 #include <soc/tegra/fuse.h>
25 
26 #include "clk.h"
27 
28 static DEFINE_SPINLOCK(periph_ref_lock);
29 
30 /* Macros to assist peripheral gate clock */
31 #define read_enb(gate) \
32 	readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
33 #define write_enb_set(val, gate) \
34 	writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
35 #define write_enb_clr(val, gate) \
36 	writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
37 
38 #define read_rst(gate) \
39 	readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
40 #define write_rst_clr(val, gate) \
41 	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
42 
43 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
44 
45 #define LVL2_CLK_GATE_OVRE 0x554
46 
47 /* Peripheral gate clock ops */
48 static int clk_periph_is_enabled(struct clk_hw *hw)
49 {
50 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
51 	int state = 1;
52 
53 	if (!(read_enb(gate) & periph_clk_to_bit(gate)))
54 		state = 0;
55 
56 	if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
57 		if (read_rst(gate) & periph_clk_to_bit(gate))
58 			state = 0;
59 
60 	return state;
61 }
62 
63 static int clk_periph_enable(struct clk_hw *hw)
64 {
65 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
66 	unsigned long flags = 0;
67 
68 	spin_lock_irqsave(&periph_ref_lock, flags);
69 
70 	gate->enable_refcnt[gate->clk_num]++;
71 	if (gate->enable_refcnt[gate->clk_num] > 1) {
72 		spin_unlock_irqrestore(&periph_ref_lock, flags);
73 		return 0;
74 	}
75 
76 	write_enb_set(periph_clk_to_bit(gate), gate);
77 	udelay(2);
78 
79 	if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
80 	    !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
81 		if (read_rst(gate) & periph_clk_to_bit(gate)) {
82 			udelay(5); /* reset propogation delay */
83 			write_rst_clr(periph_clk_to_bit(gate), gate);
84 		}
85 	}
86 
87 	if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
88 		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
89 		writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
90 		udelay(1);
91 		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
92 	}
93 
94 	spin_unlock_irqrestore(&periph_ref_lock, flags);
95 
96 	return 0;
97 }
98 
99 static void clk_periph_disable(struct clk_hw *hw)
100 {
101 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
102 	unsigned long flags = 0;
103 
104 	spin_lock_irqsave(&periph_ref_lock, flags);
105 
106 	gate->enable_refcnt[gate->clk_num]--;
107 	if (gate->enable_refcnt[gate->clk_num] > 0) {
108 		spin_unlock_irqrestore(&periph_ref_lock, flags);
109 		return;
110 	}
111 
112 	/*
113 	 * If peripheral is in the APB bus then read the APB bus to
114 	 * flush the write operation in apb bus. This will avoid the
115 	 * peripheral access after disabling clock
116 	 */
117 	if (gate->flags & TEGRA_PERIPH_ON_APB)
118 		tegra_read_chipid();
119 
120 	write_enb_clr(periph_clk_to_bit(gate), gate);
121 
122 	spin_unlock_irqrestore(&periph_ref_lock, flags);
123 }
124 
125 const struct clk_ops tegra_clk_periph_gate_ops = {
126 	.is_enabled = clk_periph_is_enabled,
127 	.enable = clk_periph_enable,
128 	.disable = clk_periph_disable,
129 };
130 
131 struct clk *tegra_clk_register_periph_gate(const char *name,
132 		const char *parent_name, u8 gate_flags, void __iomem *clk_base,
133 		unsigned long flags, int clk_num, int *enable_refcnt)
134 {
135 	struct tegra_clk_periph_gate *gate;
136 	struct clk *clk;
137 	struct clk_init_data init;
138 	struct tegra_clk_periph_regs *pregs;
139 
140 	pregs = get_reg_bank(clk_num);
141 	if (!pregs)
142 		return ERR_PTR(-EINVAL);
143 
144 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
145 	if (!gate) {
146 		pr_err("%s: could not allocate periph gate clk\n", __func__);
147 		return ERR_PTR(-ENOMEM);
148 	}
149 
150 	init.name = name;
151 	init.flags = flags;
152 	init.parent_names = parent_name ? &parent_name : NULL;
153 	init.num_parents = parent_name ? 1 : 0;
154 	init.ops = &tegra_clk_periph_gate_ops;
155 
156 	gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
157 	gate->clk_base = clk_base;
158 	gate->clk_num = clk_num;
159 	gate->flags = gate_flags;
160 	gate->enable_refcnt = enable_refcnt;
161 	gate->regs = pregs;
162 
163 	/* Data in .init is copied by clk_register(), so stack variable OK */
164 	gate->hw.init = &init;
165 
166 	clk = clk_register(NULL, &gate->hw);
167 	if (IS_ERR(clk))
168 		kfree(gate);
169 
170 	return clk;
171 }
172