1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/io.h> 19 #include <linux/err.h> 20 #include <linux/slab.h> 21 #include <linux/clk-provider.h> 22 23 #include "clk.h" 24 25 #define pll_out_override(p) (BIT((p->shift - 6))) 26 #define div_mask(d) ((1 << (d->width)) - 1) 27 #define get_mul(d) (1 << d->frac_width) 28 #define get_max_div(d) div_mask(d) 29 30 #define PERIPH_CLK_UART_DIV_ENB BIT(24) 31 32 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, 33 unsigned long parent_rate) 34 { 35 int div; 36 37 div = div_frac_get(rate, parent_rate, divider->width, 38 divider->frac_width, divider->flags); 39 40 if (div < 0) 41 return 0; 42 43 return div; 44 } 45 46 static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, 47 unsigned long parent_rate) 48 { 49 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); 50 u32 reg; 51 int div, mul; 52 u64 rate = parent_rate; 53 54 reg = readl_relaxed(divider->reg) >> divider->shift; 55 div = reg & div_mask(divider); 56 57 mul = get_mul(divider); 58 div += mul; 59 60 rate *= mul; 61 rate += div - 1; 62 do_div(rate, div); 63 64 return rate; 65 } 66 67 static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate, 68 unsigned long *prate) 69 { 70 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); 71 int div, mul; 72 unsigned long output_rate = *prate; 73 74 if (!rate) 75 return output_rate; 76 77 div = get_div(divider, rate, output_rate); 78 if (div < 0) 79 return *prate; 80 81 mul = get_mul(divider); 82 83 return DIV_ROUND_UP(output_rate * mul, div + mul); 84 } 85 86 static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, 87 unsigned long parent_rate) 88 { 89 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); 90 int div; 91 unsigned long flags = 0; 92 u32 val; 93 94 div = get_div(divider, rate, parent_rate); 95 if (div < 0) 96 return div; 97 98 if (divider->lock) 99 spin_lock_irqsave(divider->lock, flags); 100 101 val = readl_relaxed(divider->reg); 102 val &= ~(div_mask(divider) << divider->shift); 103 val |= div << divider->shift; 104 105 if (divider->flags & TEGRA_DIVIDER_UART) { 106 if (div) 107 val |= PERIPH_CLK_UART_DIV_ENB; 108 else 109 val &= ~PERIPH_CLK_UART_DIV_ENB; 110 } 111 112 if (divider->flags & TEGRA_DIVIDER_FIXED) 113 val |= pll_out_override(divider); 114 115 writel_relaxed(val, divider->reg); 116 117 if (divider->lock) 118 spin_unlock_irqrestore(divider->lock, flags); 119 120 return 0; 121 } 122 123 const struct clk_ops tegra_clk_frac_div_ops = { 124 .recalc_rate = clk_frac_div_recalc_rate, 125 .set_rate = clk_frac_div_set_rate, 126 .round_rate = clk_frac_div_round_rate, 127 }; 128 129 struct clk *tegra_clk_register_divider(const char *name, 130 const char *parent_name, void __iomem *reg, 131 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 132 u8 frac_width, spinlock_t *lock) 133 { 134 struct tegra_clk_frac_div *divider; 135 struct clk *clk; 136 struct clk_init_data init; 137 138 divider = kzalloc(sizeof(*divider), GFP_KERNEL); 139 if (!divider) { 140 pr_err("%s: could not allocate fractional divider clk\n", 141 __func__); 142 return ERR_PTR(-ENOMEM); 143 } 144 145 init.name = name; 146 init.ops = &tegra_clk_frac_div_ops; 147 init.flags = flags; 148 init.parent_names = parent_name ? &parent_name : NULL; 149 init.num_parents = parent_name ? 1 : 0; 150 151 divider->reg = reg; 152 divider->shift = shift; 153 divider->width = width; 154 divider->frac_width = frac_width; 155 divider->lock = lock; 156 divider->flags = clk_divider_flags; 157 158 /* Data in .init is copied by clk_register(), so stack variable OK */ 159 divider->hw.init = &init; 160 161 clk = clk_register(NULL, ÷r->hw); 162 if (IS_ERR(clk)) 163 kfree(divider); 164 165 return clk; 166 } 167 168 static const struct clk_div_table mc_div_table[] = { 169 { .val = 0, .div = 2 }, 170 { .val = 1, .div = 1 }, 171 { .val = 0, .div = 0 }, 172 }; 173 174 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, 175 void __iomem *reg, spinlock_t *lock) 176 { 177 return clk_register_divider_table(NULL, name, parent_name, 178 CLK_IS_CRITICAL, reg, 16, 1, 0, 179 mc_div_table, lock); 180 } 181