1 /* 2 * clk-dfll.c - Tegra DFLL clock source common code 3 * 4 * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. 5 * 6 * Aleksandr Frid <afrid@nvidia.com> 7 * Paul Walmsley <pwalmsley@nvidia.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * This library is for the DVCO and DFLL IP blocks on the Tegra124 19 * SoC. These IP blocks together are also known at NVIDIA as 20 * "CL-DVFS". To try to avoid confusion, this code refers to them 21 * collectively as the "DFLL." 22 * 23 * The DFLL is a root clocksource which tolerates some amount of 24 * supply voltage noise. Tegra124 uses it to clock the fast CPU 25 * complex when the target CPU speed is above a particular rate. The 26 * DFLL can be operated in either open-loop mode or closed-loop mode. 27 * In open-loop mode, the DFLL generates an output clock appropriate 28 * to the supply voltage. In closed-loop mode, when configured with a 29 * target frequency, the DFLL minimizes supply voltage while 30 * delivering an average frequency equal to the target. 31 * 32 * Devices clocked by the DFLL must be able to tolerate frequency 33 * variation. In the case of the CPU, it's important to note that the 34 * CPU cycle time will vary. This has implications for 35 * performance-measurement code and any code that relies on the CPU 36 * cycle time to delay for a certain length of time. 37 * 38 */ 39 40 #include <linux/clk.h> 41 #include <linux/clk-provider.h> 42 #include <linux/debugfs.h> 43 #include <linux/device.h> 44 #include <linux/err.h> 45 #include <linux/i2c.h> 46 #include <linux/io.h> 47 #include <linux/kernel.h> 48 #include <linux/module.h> 49 #include <linux/of.h> 50 #include <linux/pm_opp.h> 51 #include <linux/pm_runtime.h> 52 #include <linux/regmap.h> 53 #include <linux/regulator/consumer.h> 54 #include <linux/reset.h> 55 #include <linux/seq_file.h> 56 57 #include "clk-dfll.h" 58 59 /* 60 * DFLL control registers - access via dfll_{readl,writel} 61 */ 62 63 /* DFLL_CTRL: DFLL control register */ 64 #define DFLL_CTRL 0x00 65 #define DFLL_CTRL_MODE_MASK 0x03 66 67 /* DFLL_CONFIG: DFLL sample rate control */ 68 #define DFLL_CONFIG 0x04 69 #define DFLL_CONFIG_DIV_MASK 0xff 70 #define DFLL_CONFIG_DIV_PRESCALE 32 71 72 /* DFLL_PARAMS: tuning coefficients for closed loop integrator */ 73 #define DFLL_PARAMS 0x08 74 #define DFLL_PARAMS_CG_SCALE (0x1 << 24) 75 #define DFLL_PARAMS_FORCE_MODE_SHIFT 22 76 #define DFLL_PARAMS_FORCE_MODE_MASK (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT) 77 #define DFLL_PARAMS_CF_PARAM_SHIFT 16 78 #define DFLL_PARAMS_CF_PARAM_MASK (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT) 79 #define DFLL_PARAMS_CI_PARAM_SHIFT 8 80 #define DFLL_PARAMS_CI_PARAM_MASK (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT) 81 #define DFLL_PARAMS_CG_PARAM_SHIFT 0 82 #define DFLL_PARAMS_CG_PARAM_MASK (0xff << DFLL_PARAMS_CG_PARAM_SHIFT) 83 84 /* DFLL_TUNE0: delay line configuration register 0 */ 85 #define DFLL_TUNE0 0x0c 86 87 /* DFLL_TUNE1: delay line configuration register 1 */ 88 #define DFLL_TUNE1 0x10 89 90 /* DFLL_FREQ_REQ: target DFLL frequency control */ 91 #define DFLL_FREQ_REQ 0x14 92 #define DFLL_FREQ_REQ_FORCE_ENABLE (0x1 << 28) 93 #define DFLL_FREQ_REQ_FORCE_SHIFT 16 94 #define DFLL_FREQ_REQ_FORCE_MASK (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT) 95 #define FORCE_MAX 2047 96 #define FORCE_MIN -2048 97 #define DFLL_FREQ_REQ_SCALE_SHIFT 8 98 #define DFLL_FREQ_REQ_SCALE_MASK (0xff << DFLL_FREQ_REQ_SCALE_SHIFT) 99 #define DFLL_FREQ_REQ_SCALE_MAX 256 100 #define DFLL_FREQ_REQ_FREQ_VALID (0x1 << 7) 101 #define DFLL_FREQ_REQ_MULT_SHIFT 0 102 #define DFLL_FREQ_REG_MULT_MASK (0x7f << DFLL_FREQ_REQ_MULT_SHIFT) 103 #define FREQ_MAX 127 104 105 /* DFLL_DROOP_CTRL: droop prevention control */ 106 #define DFLL_DROOP_CTRL 0x1c 107 108 /* DFLL_OUTPUT_CFG: closed loop mode control registers */ 109 /* NOTE: access via dfll_i2c_{readl,writel} */ 110 #define DFLL_OUTPUT_CFG 0x20 111 #define DFLL_OUTPUT_CFG_I2C_ENABLE (0x1 << 30) 112 #define OUT_MASK 0x3f 113 #define DFLL_OUTPUT_CFG_SAFE_SHIFT 24 114 #define DFLL_OUTPUT_CFG_SAFE_MASK \ 115 (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT) 116 #define DFLL_OUTPUT_CFG_MAX_SHIFT 16 117 #define DFLL_OUTPUT_CFG_MAX_MASK \ 118 (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT) 119 #define DFLL_OUTPUT_CFG_MIN_SHIFT 8 120 #define DFLL_OUTPUT_CFG_MIN_MASK \ 121 (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT) 122 #define DFLL_OUTPUT_CFG_PWM_DELTA (0x1 << 7) 123 #define DFLL_OUTPUT_CFG_PWM_ENABLE (0x1 << 6) 124 #define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT 0 125 #define DFLL_OUTPUT_CFG_PWM_DIV_MASK \ 126 (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT) 127 128 /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */ 129 #define DFLL_OUTPUT_FORCE 0x24 130 #define DFLL_OUTPUT_FORCE_ENABLE (0x1 << 6) 131 #define DFLL_OUTPUT_FORCE_VALUE_SHIFT 0 132 #define DFLL_OUTPUT_FORCE_VALUE_MASK \ 133 (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT) 134 135 /* DFLL_MONITOR_CTRL: internal monitor data source control */ 136 #define DFLL_MONITOR_CTRL 0x28 137 #define DFLL_MONITOR_CTRL_FREQ 6 138 139 /* DFLL_MONITOR_DATA: internal monitor data output */ 140 #define DFLL_MONITOR_DATA 0x2c 141 #define DFLL_MONITOR_DATA_NEW_MASK (0x1 << 16) 142 #define DFLL_MONITOR_DATA_VAL_SHIFT 0 143 #define DFLL_MONITOR_DATA_VAL_MASK (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT) 144 145 /* 146 * I2C output control registers - access via dfll_i2c_{readl,writel} 147 */ 148 149 /* DFLL_I2C_CFG: I2C controller configuration register */ 150 #define DFLL_I2C_CFG 0x40 151 #define DFLL_I2C_CFG_ARB_ENABLE (0x1 << 20) 152 #define DFLL_I2C_CFG_HS_CODE_SHIFT 16 153 #define DFLL_I2C_CFG_HS_CODE_MASK (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT) 154 #define DFLL_I2C_CFG_PACKET_ENABLE (0x1 << 15) 155 #define DFLL_I2C_CFG_SIZE_SHIFT 12 156 #define DFLL_I2C_CFG_SIZE_MASK (0x7 << DFLL_I2C_CFG_SIZE_SHIFT) 157 #define DFLL_I2C_CFG_SLAVE_ADDR_10 (0x1 << 10) 158 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT 1 159 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT 0 160 161 /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */ 162 #define DFLL_I2C_VDD_REG_ADDR 0x44 163 164 /* DFLL_I2C_STS: I2C controller status */ 165 #define DFLL_I2C_STS 0x48 166 #define DFLL_I2C_STS_I2C_LAST_SHIFT 1 167 #define DFLL_I2C_STS_I2C_REQ_PENDING 0x1 168 169 /* DFLL_INTR_STS: DFLL interrupt status register */ 170 #define DFLL_INTR_STS 0x5c 171 172 /* DFLL_INTR_EN: DFLL interrupt enable register */ 173 #define DFLL_INTR_EN 0x60 174 #define DFLL_INTR_MIN_MASK 0x1 175 #define DFLL_INTR_MAX_MASK 0x2 176 177 /* 178 * Integrated I2C controller registers - relative to td->i2c_controller_base 179 */ 180 181 /* DFLL_I2C_CLK_DIVISOR: I2C controller clock divisor */ 182 #define DFLL_I2C_CLK_DIVISOR 0x6c 183 #define DFLL_I2C_CLK_DIVISOR_MASK 0xffff 184 #define DFLL_I2C_CLK_DIVISOR_FS_SHIFT 16 185 #define DFLL_I2C_CLK_DIVISOR_HS_SHIFT 0 186 #define DFLL_I2C_CLK_DIVISOR_PREDIV 8 187 #define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV 12 188 189 /* 190 * Other constants 191 */ 192 193 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */ 194 #define MAX_DFLL_VOLTAGES 33 195 196 /* 197 * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware 198 * integrates the DVCO counter over - used for debug rate monitoring and 199 * droop control 200 */ 201 #define REF_CLK_CYC_PER_DVCO_SAMPLE 4 202 203 /* 204 * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this 205 * driver, in Hz 206 */ 207 #define REF_CLOCK_RATE 51000000UL 208 209 #define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2)) 210 #define MULT_TO_DVCO_RATE(mult, ref_rate) ((mult) * ((ref_rate) / 2)) 211 212 /** 213 * enum dfll_ctrl_mode - DFLL hardware operating mode 214 * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield) 215 * @DFLL_DISABLED: DFLL not generating an output clock 216 * @DFLL_OPEN_LOOP: DVCO running, but DFLL not adjusting voltage 217 * @DFLL_CLOSED_LOOP: DVCO running, and DFLL adjusting voltage to match 218 * the requested rate 219 * 220 * The integer corresponding to the last two states, minus one, is 221 * written to the DFLL hardware to change operating modes. 222 */ 223 enum dfll_ctrl_mode { 224 DFLL_UNINITIALIZED = 0, 225 DFLL_DISABLED = 1, 226 DFLL_OPEN_LOOP = 2, 227 DFLL_CLOSED_LOOP = 3, 228 }; 229 230 /** 231 * enum dfll_tune_range - voltage range that the driver believes it's in 232 * @DFLL_TUNE_UNINITIALIZED: DFLL tuning not yet programmed 233 * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode) 234 * 235 * Some DFLL tuning parameters may need to change depending on the 236 * DVCO's voltage; these states represent the ranges that the driver 237 * supports. These are software states; these values are never 238 * written into registers. 239 */ 240 enum dfll_tune_range { 241 DFLL_TUNE_UNINITIALIZED = 0, 242 DFLL_TUNE_LOW = 1, 243 }; 244 245 /** 246 * struct dfll_rate_req - target DFLL rate request data 247 * @rate: target frequency, after the postscaling 248 * @dvco_target_rate: target frequency, after the postscaling 249 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached 250 * @mult_bits: value to program to the MULT bits of the DFLL_FREQ_REQ register 251 * @scale_bits: value to program to the SCALE bits of the DFLL_FREQ_REQ register 252 */ 253 struct dfll_rate_req { 254 unsigned long rate; 255 unsigned long dvco_target_rate; 256 int lut_index; 257 u8 mult_bits; 258 u8 scale_bits; 259 }; 260 261 struct tegra_dfll { 262 struct device *dev; 263 struct tegra_dfll_soc_data *soc; 264 265 void __iomem *base; 266 void __iomem *i2c_base; 267 void __iomem *i2c_controller_base; 268 void __iomem *lut_base; 269 270 struct regulator *vdd_reg; 271 struct clk *soc_clk; 272 struct clk *ref_clk; 273 struct clk *i2c_clk; 274 struct clk *dfll_clk; 275 struct reset_control *dvco_rst; 276 unsigned long ref_rate; 277 unsigned long i2c_clk_rate; 278 unsigned long dvco_rate_min; 279 280 enum dfll_ctrl_mode mode; 281 enum dfll_tune_range tune_range; 282 struct dentry *debugfs_dir; 283 struct clk_hw dfll_clk_hw; 284 const char *output_clock_name; 285 struct dfll_rate_req last_req; 286 unsigned long last_unrounded_rate; 287 288 /* Parameters from DT */ 289 u32 droop_ctrl; 290 u32 sample_rate; 291 u32 force_mode; 292 u32 cf; 293 u32 ci; 294 u32 cg; 295 bool cg_scale; 296 297 /* I2C interface parameters */ 298 u32 i2c_fs_rate; 299 u32 i2c_reg; 300 u32 i2c_slave_addr; 301 302 /* i2c_lut array entries are regulator framework selectors */ 303 unsigned i2c_lut[MAX_DFLL_VOLTAGES]; 304 int i2c_lut_size; 305 u8 lut_min, lut_max, lut_safe; 306 }; 307 308 #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw) 309 310 /* mode_name: map numeric DFLL modes to names for friendly console messages */ 311 static const char * const mode_name[] = { 312 [DFLL_UNINITIALIZED] = "uninitialized", 313 [DFLL_DISABLED] = "disabled", 314 [DFLL_OPEN_LOOP] = "open_loop", 315 [DFLL_CLOSED_LOOP] = "closed_loop", 316 }; 317 318 /* 319 * Register accessors 320 */ 321 322 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs) 323 { 324 return __raw_readl(td->base + offs); 325 } 326 327 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs) 328 { 329 WARN_ON(offs >= DFLL_I2C_CFG); 330 __raw_writel(val, td->base + offs); 331 } 332 333 static inline void dfll_wmb(struct tegra_dfll *td) 334 { 335 dfll_readl(td, DFLL_CTRL); 336 } 337 338 /* I2C output control registers - for addresses above DFLL_I2C_CFG */ 339 340 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs) 341 { 342 return __raw_readl(td->i2c_base + offs); 343 } 344 345 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs) 346 { 347 __raw_writel(val, td->i2c_base + offs); 348 } 349 350 static inline void dfll_i2c_wmb(struct tegra_dfll *td) 351 { 352 dfll_i2c_readl(td, DFLL_I2C_CFG); 353 } 354 355 /** 356 * dfll_is_running - is the DFLL currently generating a clock? 357 * @td: DFLL instance 358 * 359 * If the DFLL is currently generating an output clock signal, return 360 * true; otherwise return false. 361 */ 362 static bool dfll_is_running(struct tegra_dfll *td) 363 { 364 return td->mode >= DFLL_OPEN_LOOP; 365 } 366 367 /* 368 * Runtime PM suspend/resume callbacks 369 */ 370 371 /** 372 * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL 373 * @dev: DFLL device * 374 * 375 * Enable all clocks needed by the DFLL. Assumes that clk_prepare() 376 * has already been called on all the clocks. 377 * 378 * XXX Should also handle context restore when returning from off. 379 */ 380 int tegra_dfll_runtime_resume(struct device *dev) 381 { 382 struct tegra_dfll *td = dev_get_drvdata(dev); 383 int ret; 384 385 ret = clk_enable(td->ref_clk); 386 if (ret) { 387 dev_err(dev, "could not enable ref clock: %d\n", ret); 388 return ret; 389 } 390 391 ret = clk_enable(td->soc_clk); 392 if (ret) { 393 dev_err(dev, "could not enable register clock: %d\n", ret); 394 clk_disable(td->ref_clk); 395 return ret; 396 } 397 398 ret = clk_enable(td->i2c_clk); 399 if (ret) { 400 dev_err(dev, "could not enable i2c clock: %d\n", ret); 401 clk_disable(td->soc_clk); 402 clk_disable(td->ref_clk); 403 return ret; 404 } 405 406 return 0; 407 } 408 EXPORT_SYMBOL(tegra_dfll_runtime_resume); 409 410 /** 411 * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL 412 * @dev: DFLL device * 413 * 414 * Disable all clocks needed by the DFLL. Assumes that other code 415 * will later call clk_unprepare(). 416 */ 417 int tegra_dfll_runtime_suspend(struct device *dev) 418 { 419 struct tegra_dfll *td = dev_get_drvdata(dev); 420 421 clk_disable(td->ref_clk); 422 clk_disable(td->soc_clk); 423 clk_disable(td->i2c_clk); 424 425 return 0; 426 } 427 EXPORT_SYMBOL(tegra_dfll_runtime_suspend); 428 429 /* 430 * DFLL tuning operations (per-voltage-range tuning settings) 431 */ 432 433 /** 434 * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage 435 * @td: DFLL instance 436 * 437 * Tune the DFLL oscillator parameters and the CPU clock shaper for 438 * the low-voltage range. These settings are valid for any voltage, 439 * but may not be optimal. 440 */ 441 static void dfll_tune_low(struct tegra_dfll *td) 442 { 443 td->tune_range = DFLL_TUNE_LOW; 444 445 dfll_writel(td, td->soc->tune0_low, DFLL_TUNE0); 446 dfll_writel(td, td->soc->tune1, DFLL_TUNE1); 447 dfll_wmb(td); 448 449 if (td->soc->set_clock_trimmers_low) 450 td->soc->set_clock_trimmers_low(); 451 } 452 453 /* 454 * Output clock scaler helpers 455 */ 456 457 /** 458 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate 459 * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field) 460 * @dvco_rate: the DVCO rate 461 * 462 * Apply the same scaling formula that the DFLL hardware uses to scale 463 * the DVCO rate. 464 */ 465 static unsigned long dfll_scale_dvco_rate(int scale_bits, 466 unsigned long dvco_rate) 467 { 468 return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX; 469 } 470 471 /* 472 * Monitor control 473 */ 474 475 /** 476 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq 477 * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield 478 * @ref_rate: DFLL reference clock rate 479 * 480 * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles 481 * per second. Returns the converted value. 482 */ 483 static u64 dfll_calc_monitored_rate(u32 monitor_data, 484 unsigned long ref_rate) 485 { 486 return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE); 487 } 488 489 /** 490 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor 491 * @td: DFLL instance 492 * 493 * If the DFLL is enabled, return the last rate reported by the DFLL's 494 * internal monitoring hardware. This works in both open-loop and 495 * closed-loop mode, and takes the output scaler setting into account. 496 * Assumes that the monitor was programmed to monitor frequency before 497 * the sample period started. If the driver believes that the DFLL is 498 * currently uninitialized or disabled, it will return 0, since 499 * otherwise the DFLL monitor data register will return the last 500 * measured rate from when the DFLL was active. 501 */ 502 static u64 dfll_read_monitor_rate(struct tegra_dfll *td) 503 { 504 u32 v, s; 505 u64 pre_scaler_rate, post_scaler_rate; 506 507 if (!dfll_is_running(td)) 508 return 0; 509 510 v = dfll_readl(td, DFLL_MONITOR_DATA); 511 v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT; 512 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate); 513 514 s = dfll_readl(td, DFLL_FREQ_REQ); 515 s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT; 516 post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate); 517 518 return post_scaler_rate; 519 } 520 521 /* 522 * DFLL mode switching 523 */ 524 525 /** 526 * dfll_set_mode - change the DFLL control mode 527 * @td: DFLL instance 528 * @mode: DFLL control mode (see enum dfll_ctrl_mode) 529 * 530 * Change the DFLL's operating mode between disabled, open-loop mode, 531 * and closed-loop mode, or vice versa. 532 */ 533 static void dfll_set_mode(struct tegra_dfll *td, 534 enum dfll_ctrl_mode mode) 535 { 536 td->mode = mode; 537 dfll_writel(td, mode - 1, DFLL_CTRL); 538 dfll_wmb(td); 539 } 540 541 /* 542 * DFLL-to-I2C controller interface 543 */ 544 545 /** 546 * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests 547 * @td: DFLL instance 548 * @enable: whether to enable or disable the I2C voltage requests 549 * 550 * Set the master enable control for I2C control value updates. If disabled, 551 * then I2C control messages are inhibited, regardless of the DFLL mode. 552 */ 553 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable) 554 { 555 u32 val; 556 557 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG); 558 559 if (enable) 560 val |= DFLL_OUTPUT_CFG_I2C_ENABLE; 561 else 562 val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE; 563 564 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); 565 dfll_i2c_wmb(td); 566 567 return 0; 568 } 569 570 /** 571 * dfll_load_lut - load the voltage lookup table 572 * @td: struct tegra_dfll * 573 * 574 * Load the voltage-to-PMIC register value lookup table into the DFLL 575 * IP block memory. Look-up tables can be loaded at any time. 576 */ 577 static void dfll_load_i2c_lut(struct tegra_dfll *td) 578 { 579 int i, lut_index; 580 u32 val; 581 582 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) { 583 if (i < td->lut_min) 584 lut_index = td->lut_min; 585 else if (i > td->lut_max) 586 lut_index = td->lut_max; 587 else 588 lut_index = i; 589 590 val = regulator_list_hardware_vsel(td->vdd_reg, 591 td->i2c_lut[lut_index]); 592 __raw_writel(val, td->lut_base + i * 4); 593 } 594 595 dfll_i2c_wmb(td); 596 } 597 598 /** 599 * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface 600 * @td: DFLL instance 601 * 602 * During DFLL driver initialization, program the DFLL-I2C interface 603 * with the PMU slave address, vdd register offset, and transfer mode. 604 * This data is used by the DFLL to automatically construct I2C 605 * voltage-set commands, which are then passed to the DFLL's internal 606 * I2C controller. 607 */ 608 static void dfll_init_i2c_if(struct tegra_dfll *td) 609 { 610 u32 val; 611 612 if (td->i2c_slave_addr > 0x7f) { 613 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; 614 val |= DFLL_I2C_CFG_SLAVE_ADDR_10; 615 } else { 616 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; 617 } 618 val |= DFLL_I2C_CFG_SIZE_MASK; 619 val |= DFLL_I2C_CFG_ARB_ENABLE; 620 dfll_i2c_writel(td, val, DFLL_I2C_CFG); 621 622 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR); 623 624 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); 625 BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK)); 626 val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT; 627 628 /* default hs divisor just in case */ 629 val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT; 630 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); 631 dfll_i2c_wmb(td); 632 } 633 634 /** 635 * dfll_init_out_if - prepare DFLL-to-PMIC interface 636 * @td: DFLL instance 637 * 638 * During DFLL driver initialization or resume from context loss, 639 * disable the I2C command output to the PMIC, set safe voltage and 640 * output limits, and disable and clear limit interrupts. 641 */ 642 static void dfll_init_out_if(struct tegra_dfll *td) 643 { 644 u32 val; 645 646 td->lut_min = 0; 647 td->lut_max = td->i2c_lut_size - 1; 648 td->lut_safe = td->lut_min + 1; 649 650 dfll_i2c_writel(td, 0, DFLL_OUTPUT_CFG); 651 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | 652 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | 653 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); 654 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); 655 dfll_i2c_wmb(td); 656 657 dfll_writel(td, 0, DFLL_OUTPUT_FORCE); 658 dfll_i2c_writel(td, 0, DFLL_INTR_EN); 659 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK, 660 DFLL_INTR_STS); 661 662 dfll_load_i2c_lut(td); 663 dfll_init_i2c_if(td); 664 } 665 666 /* 667 * Set/get the DFLL's targeted output clock rate 668 */ 669 670 /** 671 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate 672 * @td: DFLL instance 673 * @rate: clock rate 674 * 675 * Determines the index of a I2C LUT entry for a voltage that approximately 676 * produces the given DFLL clock rate. This is used when forcing a value 677 * to the integrator during rate changes. Returns -ENOENT if a suitable 678 * LUT index is not found. 679 */ 680 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) 681 { 682 struct dev_pm_opp *opp; 683 int i, uv; 684 685 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); 686 if (IS_ERR(opp)) 687 return PTR_ERR(opp); 688 uv = dev_pm_opp_get_voltage(opp); 689 690 for (i = 0; i < td->i2c_lut_size; i++) { 691 if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv) 692 return i; 693 } 694 695 return -ENOENT; 696 } 697 698 /** 699 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate 700 * @td: DFLL instance 701 * @req: DFLL-rate-request structure 702 * @rate: the desired DFLL rate 703 * 704 * Populate the DFLL-rate-request record @req fields with the scale_bits 705 * and mult_bits fields, based on the target input rate. Returns 0 upon 706 * success, or -EINVAL if the requested rate in req->rate is too high 707 * or low for the DFLL to generate. 708 */ 709 static int dfll_calculate_rate_request(struct tegra_dfll *td, 710 struct dfll_rate_req *req, 711 unsigned long rate) 712 { 713 u32 val; 714 715 /* 716 * If requested rate is below the minimum DVCO rate, active the scaler. 717 * In the future the DVCO minimum voltage should be selected based on 718 * chip temperature and the actual minimum rate should be calibrated 719 * at runtime. 720 */ 721 req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1; 722 if (rate < td->dvco_rate_min) { 723 int scale; 724 725 scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX, 726 td->dvco_rate_min / 1000); 727 if (!scale) { 728 dev_err(td->dev, "%s: Rate %lu is too low\n", 729 __func__, rate); 730 return -EINVAL; 731 } 732 req->scale_bits = scale - 1; 733 rate = td->dvco_rate_min; 734 } 735 736 /* Convert requested rate into frequency request and scale settings */ 737 val = DVCO_RATE_TO_MULT(rate, td->ref_rate); 738 if (val > FREQ_MAX) { 739 dev_err(td->dev, "%s: Rate %lu is above dfll range\n", 740 __func__, rate); 741 return -EINVAL; 742 } 743 req->mult_bits = val; 744 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate); 745 req->rate = dfll_scale_dvco_rate(req->scale_bits, 746 req->dvco_target_rate); 747 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate); 748 if (req->lut_index < 0) 749 return req->lut_index; 750 751 return 0; 752 } 753 754 /** 755 * dfll_set_frequency_request - start the frequency change operation 756 * @td: DFLL instance 757 * @req: rate request structure 758 * 759 * Tell the DFLL to try to change its output frequency to the 760 * frequency represented by @req. DFLL must be in closed-loop mode. 761 */ 762 static void dfll_set_frequency_request(struct tegra_dfll *td, 763 struct dfll_rate_req *req) 764 { 765 u32 val = 0; 766 int force_val; 767 int coef = 128; /* FIXME: td->cg_scale? */; 768 769 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; 770 force_val = clamp(force_val, FORCE_MIN, FORCE_MAX); 771 772 val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT; 773 val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT; 774 val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) & 775 DFLL_FREQ_REQ_FORCE_MASK; 776 val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE; 777 778 dfll_writel(td, val, DFLL_FREQ_REQ); 779 dfll_wmb(td); 780 } 781 782 /** 783 * tegra_dfll_request_rate - set the next rate for the DFLL to tune to 784 * @td: DFLL instance 785 * @rate: clock rate to target 786 * 787 * Convert the requested clock rate @rate into the DFLL control logic 788 * settings. In closed-loop mode, update new settings immediately to 789 * adjust DFLL output rate accordingly. Otherwise, just save them 790 * until the next switch to closed loop. Returns 0 upon success, 791 * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL 792 * if @rate is outside the DFLL's tunable range. 793 */ 794 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate) 795 { 796 int ret; 797 struct dfll_rate_req req; 798 799 if (td->mode == DFLL_UNINITIALIZED) { 800 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n", 801 __func__, mode_name[td->mode]); 802 return -EPERM; 803 } 804 805 ret = dfll_calculate_rate_request(td, &req, rate); 806 if (ret) 807 return ret; 808 809 td->last_unrounded_rate = rate; 810 td->last_req = req; 811 812 if (td->mode == DFLL_CLOSED_LOOP) 813 dfll_set_frequency_request(td, &td->last_req); 814 815 return 0; 816 } 817 818 /* 819 * DFLL enable/disable & open-loop <-> closed-loop transitions 820 */ 821 822 /** 823 * dfll_disable - switch from open-loop mode to disabled mode 824 * @td: DFLL instance 825 * 826 * Switch from OPEN_LOOP state to DISABLED state. Returns 0 upon success 827 * or -EPERM if the DFLL is not currently in open-loop mode. 828 */ 829 static int dfll_disable(struct tegra_dfll *td) 830 { 831 if (td->mode != DFLL_OPEN_LOOP) { 832 dev_err(td->dev, "cannot disable DFLL in %s mode\n", 833 mode_name[td->mode]); 834 return -EINVAL; 835 } 836 837 dfll_set_mode(td, DFLL_DISABLED); 838 pm_runtime_put_sync(td->dev); 839 840 return 0; 841 } 842 843 /** 844 * dfll_enable - switch a disabled DFLL to open-loop mode 845 * @td: DFLL instance 846 * 847 * Switch from DISABLED state to OPEN_LOOP state. Returns 0 upon success 848 * or -EPERM if the DFLL is not currently disabled. 849 */ 850 static int dfll_enable(struct tegra_dfll *td) 851 { 852 if (td->mode != DFLL_DISABLED) { 853 dev_err(td->dev, "cannot enable DFLL in %s mode\n", 854 mode_name[td->mode]); 855 return -EPERM; 856 } 857 858 pm_runtime_get_sync(td->dev); 859 dfll_set_mode(td, DFLL_OPEN_LOOP); 860 861 return 0; 862 } 863 864 /** 865 * dfll_set_open_loop_config - prepare to switch to open-loop mode 866 * @td: DFLL instance 867 * 868 * Prepare to switch the DFLL to open-loop mode. This switches the 869 * DFLL to the low-voltage tuning range, ensures that I2C output 870 * forcing is disabled, and disables the output clock rate scaler. 871 * The DFLL's low-voltage tuning range parameters must be 872 * characterized to keep the downstream device stable at any DVCO 873 * input voltage. No return value. 874 */ 875 static void dfll_set_open_loop_config(struct tegra_dfll *td) 876 { 877 u32 val; 878 879 /* always tune low (safe) in open loop */ 880 if (td->tune_range != DFLL_TUNE_LOW) 881 dfll_tune_low(td); 882 883 val = dfll_readl(td, DFLL_FREQ_REQ); 884 val |= DFLL_FREQ_REQ_SCALE_MASK; 885 val &= ~DFLL_FREQ_REQ_FORCE_ENABLE; 886 dfll_writel(td, val, DFLL_FREQ_REQ); 887 dfll_wmb(td); 888 } 889 890 /** 891 * tegra_dfll_lock - switch from open-loop to closed-loop mode 892 * @td: DFLL instance 893 * 894 * Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success, 895 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the 896 * DFLL is not currently in open-loop mode. 897 */ 898 static int dfll_lock(struct tegra_dfll *td) 899 { 900 struct dfll_rate_req *req = &td->last_req; 901 902 switch (td->mode) { 903 case DFLL_CLOSED_LOOP: 904 return 0; 905 906 case DFLL_OPEN_LOOP: 907 if (req->rate == 0) { 908 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n", 909 __func__); 910 return -EINVAL; 911 } 912 913 dfll_i2c_set_output_enabled(td, true); 914 dfll_set_mode(td, DFLL_CLOSED_LOOP); 915 dfll_set_frequency_request(td, req); 916 return 0; 917 918 default: 919 BUG_ON(td->mode > DFLL_CLOSED_LOOP); 920 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n", 921 __func__, mode_name[td->mode]); 922 return -EPERM; 923 } 924 } 925 926 /** 927 * tegra_dfll_unlock - switch from closed-loop to open-loop mode 928 * @td: DFLL instance 929 * 930 * Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success, 931 * or -EPERM if the DFLL is not currently in open-loop mode. 932 */ 933 static int dfll_unlock(struct tegra_dfll *td) 934 { 935 switch (td->mode) { 936 case DFLL_CLOSED_LOOP: 937 dfll_set_open_loop_config(td); 938 dfll_set_mode(td, DFLL_OPEN_LOOP); 939 dfll_i2c_set_output_enabled(td, false); 940 return 0; 941 942 case DFLL_OPEN_LOOP: 943 return 0; 944 945 default: 946 BUG_ON(td->mode > DFLL_CLOSED_LOOP); 947 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n", 948 __func__, mode_name[td->mode]); 949 return -EPERM; 950 } 951 } 952 953 /* 954 * Clock framework integration 955 * 956 * When the DFLL is being controlled by the CCF, always enter closed loop 957 * mode when the clk is enabled. This requires that a DFLL rate request 958 * has been set beforehand, which implies that a clk_set_rate() call is 959 * always required before a clk_enable(). 960 */ 961 962 static int dfll_clk_is_enabled(struct clk_hw *hw) 963 { 964 struct tegra_dfll *td = clk_hw_to_dfll(hw); 965 966 return dfll_is_running(td); 967 } 968 969 static int dfll_clk_enable(struct clk_hw *hw) 970 { 971 struct tegra_dfll *td = clk_hw_to_dfll(hw); 972 int ret; 973 974 ret = dfll_enable(td); 975 if (ret) 976 return ret; 977 978 ret = dfll_lock(td); 979 if (ret) 980 dfll_disable(td); 981 982 return ret; 983 } 984 985 static void dfll_clk_disable(struct clk_hw *hw) 986 { 987 struct tegra_dfll *td = clk_hw_to_dfll(hw); 988 int ret; 989 990 ret = dfll_unlock(td); 991 if (!ret) 992 dfll_disable(td); 993 } 994 995 static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw, 996 unsigned long parent_rate) 997 { 998 struct tegra_dfll *td = clk_hw_to_dfll(hw); 999 1000 return td->last_unrounded_rate; 1001 } 1002 1003 static long dfll_clk_round_rate(struct clk_hw *hw, 1004 unsigned long rate, 1005 unsigned long *parent_rate) 1006 { 1007 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1008 struct dfll_rate_req req; 1009 int ret; 1010 1011 ret = dfll_calculate_rate_request(td, &req, rate); 1012 if (ret) 1013 return ret; 1014 1015 /* 1016 * Don't return the rounded rate, since it doesn't really matter as 1017 * the output rate will be voltage controlled anyway, and cpufreq 1018 * freaks out if any rounding happens. 1019 */ 1020 return rate; 1021 } 1022 1023 static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate, 1024 unsigned long parent_rate) 1025 { 1026 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1027 1028 return dfll_request_rate(td, rate); 1029 } 1030 1031 static const struct clk_ops dfll_clk_ops = { 1032 .is_enabled = dfll_clk_is_enabled, 1033 .enable = dfll_clk_enable, 1034 .disable = dfll_clk_disable, 1035 .recalc_rate = dfll_clk_recalc_rate, 1036 .round_rate = dfll_clk_round_rate, 1037 .set_rate = dfll_clk_set_rate, 1038 }; 1039 1040 static struct clk_init_data dfll_clk_init_data = { 1041 .flags = CLK_IS_ROOT, 1042 .ops = &dfll_clk_ops, 1043 .num_parents = 0, 1044 }; 1045 1046 /** 1047 * dfll_register_clk - register the DFLL output clock with the clock framework 1048 * @td: DFLL instance 1049 * 1050 * Register the DFLL's output clock with the Linux clock framework and register 1051 * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL 1052 * or -ENOMEM upon failure. 1053 */ 1054 static int dfll_register_clk(struct tegra_dfll *td) 1055 { 1056 int ret; 1057 1058 dfll_clk_init_data.name = td->output_clock_name; 1059 td->dfll_clk_hw.init = &dfll_clk_init_data; 1060 1061 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw); 1062 if (IS_ERR(td->dfll_clk)) { 1063 dev_err(td->dev, "DFLL clock registration error\n"); 1064 return -EINVAL; 1065 } 1066 1067 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get, 1068 td->dfll_clk); 1069 if (ret) { 1070 dev_err(td->dev, "of_clk_add_provider() failed\n"); 1071 1072 clk_unregister(td->dfll_clk); 1073 return ret; 1074 } 1075 1076 return 0; 1077 } 1078 1079 /** 1080 * dfll_unregister_clk - unregister the DFLL output clock 1081 * @td: DFLL instance 1082 * 1083 * Unregister the DFLL's output clock from the Linux clock framework 1084 * and from clkdev. No return value. 1085 */ 1086 static void dfll_unregister_clk(struct tegra_dfll *td) 1087 { 1088 of_clk_del_provider(td->dev->of_node); 1089 clk_unregister(td->dfll_clk); 1090 td->dfll_clk = NULL; 1091 } 1092 1093 /* 1094 * Debugfs interface 1095 */ 1096 1097 #ifdef CONFIG_DEBUG_FS 1098 1099 static int attr_enable_get(void *data, u64 *val) 1100 { 1101 struct tegra_dfll *td = data; 1102 1103 *val = dfll_is_running(td); 1104 1105 return 0; 1106 } 1107 static int attr_enable_set(void *data, u64 val) 1108 { 1109 struct tegra_dfll *td = data; 1110 1111 return val ? dfll_enable(td) : dfll_disable(td); 1112 } 1113 DEFINE_SIMPLE_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set, 1114 "%llu\n"); 1115 1116 static int attr_lock_get(void *data, u64 *val) 1117 { 1118 struct tegra_dfll *td = data; 1119 1120 *val = (td->mode == DFLL_CLOSED_LOOP); 1121 1122 return 0; 1123 } 1124 static int attr_lock_set(void *data, u64 val) 1125 { 1126 struct tegra_dfll *td = data; 1127 1128 return val ? dfll_lock(td) : dfll_unlock(td); 1129 } 1130 DEFINE_SIMPLE_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set, 1131 "%llu\n"); 1132 1133 static int attr_rate_get(void *data, u64 *val) 1134 { 1135 struct tegra_dfll *td = data; 1136 1137 *val = dfll_read_monitor_rate(td); 1138 1139 return 0; 1140 } 1141 1142 static int attr_rate_set(void *data, u64 val) 1143 { 1144 struct tegra_dfll *td = data; 1145 1146 return dfll_request_rate(td, val); 1147 } 1148 DEFINE_SIMPLE_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n"); 1149 1150 static int attr_registers_show(struct seq_file *s, void *data) 1151 { 1152 u32 val, offs; 1153 struct tegra_dfll *td = s->private; 1154 1155 seq_puts(s, "CONTROL REGISTERS:\n"); 1156 for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) { 1157 if (offs == DFLL_OUTPUT_CFG) 1158 val = dfll_i2c_readl(td, offs); 1159 else 1160 val = dfll_readl(td, offs); 1161 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val); 1162 } 1163 1164 seq_puts(s, "\nI2C and INTR REGISTERS:\n"); 1165 for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4) 1166 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1167 dfll_i2c_readl(td, offs)); 1168 for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4) 1169 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1170 dfll_i2c_readl(td, offs)); 1171 1172 seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n"); 1173 offs = DFLL_I2C_CLK_DIVISOR; 1174 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1175 __raw_readl(td->i2c_controller_base + offs)); 1176 1177 seq_puts(s, "\nLUT:\n"); 1178 for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4) 1179 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1180 __raw_readl(td->lut_base + offs)); 1181 1182 return 0; 1183 } 1184 1185 static int attr_registers_open(struct inode *inode, struct file *file) 1186 { 1187 return single_open(file, attr_registers_show, inode->i_private); 1188 } 1189 1190 static const struct file_operations attr_registers_fops = { 1191 .open = attr_registers_open, 1192 .read = seq_read, 1193 .llseek = seq_lseek, 1194 .release = single_release, 1195 }; 1196 1197 static int dfll_debug_init(struct tegra_dfll *td) 1198 { 1199 int ret; 1200 1201 if (!td || (td->mode == DFLL_UNINITIALIZED)) 1202 return 0; 1203 1204 td->debugfs_dir = debugfs_create_dir("tegra_dfll_fcpu", NULL); 1205 if (!td->debugfs_dir) 1206 return -ENOMEM; 1207 1208 ret = -ENOMEM; 1209 1210 if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, 1211 td->debugfs_dir, td, &enable_fops)) 1212 goto err_out; 1213 1214 if (!debugfs_create_file("lock", S_IRUGO, 1215 td->debugfs_dir, td, &lock_fops)) 1216 goto err_out; 1217 1218 if (!debugfs_create_file("rate", S_IRUGO, 1219 td->debugfs_dir, td, &rate_fops)) 1220 goto err_out; 1221 1222 if (!debugfs_create_file("registers", S_IRUGO, 1223 td->debugfs_dir, td, &attr_registers_fops)) 1224 goto err_out; 1225 1226 return 0; 1227 1228 err_out: 1229 debugfs_remove_recursive(td->debugfs_dir); 1230 return ret; 1231 } 1232 1233 #endif /* CONFIG_DEBUG_FS */ 1234 1235 /* 1236 * DFLL initialization 1237 */ 1238 1239 /** 1240 * dfll_set_default_params - program non-output related DFLL parameters 1241 * @td: DFLL instance 1242 * 1243 * During DFLL driver initialization or resume from context loss, 1244 * program parameters for the closed loop integrator, DVCO tuning, 1245 * voltage droop control and monitor control. 1246 */ 1247 static void dfll_set_default_params(struct tegra_dfll *td) 1248 { 1249 u32 val; 1250 1251 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); 1252 BUG_ON(val > DFLL_CONFIG_DIV_MASK); 1253 dfll_writel(td, val, DFLL_CONFIG); 1254 1255 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | 1256 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) | 1257 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) | 1258 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | 1259 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0); 1260 dfll_writel(td, val, DFLL_PARAMS); 1261 1262 dfll_tune_low(td); 1263 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL); 1264 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL); 1265 } 1266 1267 /** 1268 * dfll_init_clks - clk_get() the DFLL source clocks 1269 * @td: DFLL instance 1270 * 1271 * Call clk_get() on the DFLL source clocks and save the pointers for later 1272 * use. Returns 0 upon success or error (see devm_clk_get) if one or more 1273 * of the clocks couldn't be looked up. 1274 */ 1275 static int dfll_init_clks(struct tegra_dfll *td) 1276 { 1277 td->ref_clk = devm_clk_get(td->dev, "ref"); 1278 if (IS_ERR(td->ref_clk)) { 1279 dev_err(td->dev, "missing ref clock\n"); 1280 return PTR_ERR(td->ref_clk); 1281 } 1282 1283 td->soc_clk = devm_clk_get(td->dev, "soc"); 1284 if (IS_ERR(td->soc_clk)) { 1285 dev_err(td->dev, "missing soc clock\n"); 1286 return PTR_ERR(td->soc_clk); 1287 } 1288 1289 td->i2c_clk = devm_clk_get(td->dev, "i2c"); 1290 if (IS_ERR(td->i2c_clk)) { 1291 dev_err(td->dev, "missing i2c clock\n"); 1292 return PTR_ERR(td->i2c_clk); 1293 } 1294 td->i2c_clk_rate = clk_get_rate(td->i2c_clk); 1295 1296 return 0; 1297 } 1298 1299 /** 1300 * dfll_init - Prepare the DFLL IP block for use 1301 * @td: DFLL instance 1302 * 1303 * Do everything necessary to prepare the DFLL IP block for use. The 1304 * DFLL will be left in DISABLED state. Called by dfll_probe(). 1305 * Returns 0 upon success, or passes along the error from whatever 1306 * function returned it. 1307 */ 1308 static int dfll_init(struct tegra_dfll *td) 1309 { 1310 int ret; 1311 1312 td->ref_rate = clk_get_rate(td->ref_clk); 1313 if (td->ref_rate != REF_CLOCK_RATE) { 1314 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu", 1315 td->ref_rate, REF_CLOCK_RATE); 1316 return -EINVAL; 1317 } 1318 1319 reset_control_deassert(td->dvco_rst); 1320 1321 ret = clk_prepare(td->ref_clk); 1322 if (ret) { 1323 dev_err(td->dev, "failed to prepare ref_clk\n"); 1324 return ret; 1325 } 1326 1327 ret = clk_prepare(td->soc_clk); 1328 if (ret) { 1329 dev_err(td->dev, "failed to prepare soc_clk\n"); 1330 goto di_err1; 1331 } 1332 1333 ret = clk_prepare(td->i2c_clk); 1334 if (ret) { 1335 dev_err(td->dev, "failed to prepare i2c_clk\n"); 1336 goto di_err2; 1337 } 1338 1339 td->last_unrounded_rate = 0; 1340 1341 pm_runtime_enable(td->dev); 1342 pm_runtime_get_sync(td->dev); 1343 1344 dfll_set_mode(td, DFLL_DISABLED); 1345 dfll_set_default_params(td); 1346 1347 if (td->soc->init_clock_trimmers) 1348 td->soc->init_clock_trimmers(); 1349 1350 dfll_set_open_loop_config(td); 1351 1352 dfll_init_out_if(td); 1353 1354 pm_runtime_put_sync(td->dev); 1355 1356 return 0; 1357 1358 di_err2: 1359 clk_unprepare(td->soc_clk); 1360 di_err1: 1361 clk_unprepare(td->ref_clk); 1362 1363 reset_control_assert(td->dvco_rst); 1364 1365 return ret; 1366 } 1367 1368 /* 1369 * DT data fetch 1370 */ 1371 1372 /* 1373 * Find a PMIC voltage register-to-voltage mapping for the given voltage. 1374 * An exact voltage match is required. 1375 */ 1376 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) 1377 { 1378 int i, n_voltages, reg_uV; 1379 1380 n_voltages = regulator_count_voltages(td->vdd_reg); 1381 for (i = 0; i < n_voltages; i++) { 1382 reg_uV = regulator_list_voltage(td->vdd_reg, i); 1383 if (reg_uV < 0) 1384 break; 1385 1386 if (uV == reg_uV) 1387 return i; 1388 } 1389 1390 dev_err(td->dev, "no voltage map entry for %d uV\n", uV); 1391 return -EINVAL; 1392 } 1393 1394 /* 1395 * Find a PMIC voltage register-to-voltage mapping for the given voltage, 1396 * rounding up to the closest supported voltage. 1397 * */ 1398 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) 1399 { 1400 int i, n_voltages, reg_uV; 1401 1402 n_voltages = regulator_count_voltages(td->vdd_reg); 1403 for (i = 0; i < n_voltages; i++) { 1404 reg_uV = regulator_list_voltage(td->vdd_reg, i); 1405 if (reg_uV < 0) 1406 break; 1407 1408 if (uV <= reg_uV) 1409 return i; 1410 } 1411 1412 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV); 1413 return -EINVAL; 1414 } 1415 1416 /** 1417 * dfll_build_i2c_lut - build the I2C voltage register lookup table 1418 * @td: DFLL instance 1419 * 1420 * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with 1421 * PMIC voltage register values that span the entire DFLL operating range. 1422 * This function builds the look-up table based on the OPP table provided by 1423 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC 1424 * register-to-voltage mapping queried from the regulator framework. 1425 * 1426 * On success, fills in td->i2c_lut and returns 0, or -err on failure. 1427 */ 1428 static int dfll_build_i2c_lut(struct tegra_dfll *td) 1429 { 1430 int ret = -EINVAL; 1431 int j, v, v_max, v_opp; 1432 int selector; 1433 unsigned long rate; 1434 struct dev_pm_opp *opp; 1435 int lut; 1436 1437 rcu_read_lock(); 1438 1439 rate = ULONG_MAX; 1440 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); 1441 if (IS_ERR(opp)) { 1442 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); 1443 goto out; 1444 } 1445 v_max = dev_pm_opp_get_voltage(opp); 1446 1447 v = td->soc->min_millivolts * 1000; 1448 lut = find_vdd_map_entry_exact(td, v); 1449 if (lut < 0) 1450 goto out; 1451 td->i2c_lut[0] = lut; 1452 1453 for (j = 1, rate = 0; ; rate++) { 1454 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); 1455 if (IS_ERR(opp)) 1456 break; 1457 v_opp = dev_pm_opp_get_voltage(opp); 1458 1459 if (v_opp <= td->soc->min_millivolts * 1000) 1460 td->dvco_rate_min = dev_pm_opp_get_freq(opp); 1461 1462 for (;;) { 1463 v += max(1, (v_max - v) / (MAX_DFLL_VOLTAGES - j)); 1464 if (v >= v_opp) 1465 break; 1466 1467 selector = find_vdd_map_entry_min(td, v); 1468 if (selector < 0) 1469 goto out; 1470 if (selector != td->i2c_lut[j - 1]) 1471 td->i2c_lut[j++] = selector; 1472 } 1473 1474 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp; 1475 selector = find_vdd_map_entry_exact(td, v); 1476 if (selector < 0) 1477 goto out; 1478 if (selector != td->i2c_lut[j - 1]) 1479 td->i2c_lut[j++] = selector; 1480 1481 if (v >= v_max) 1482 break; 1483 } 1484 td->i2c_lut_size = j; 1485 1486 if (!td->dvco_rate_min) 1487 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", 1488 td->soc->min_millivolts); 1489 else 1490 ret = 0; 1491 1492 out: 1493 rcu_read_unlock(); 1494 1495 return ret; 1496 } 1497 1498 /** 1499 * read_dt_param - helper function for reading required parameters from the DT 1500 * @td: DFLL instance 1501 * @param: DT property name 1502 * @dest: output pointer for the value read 1503 * 1504 * Read a required numeric parameter from the DFLL device node, or complain 1505 * if the property doesn't exist. Returns a boolean indicating success for 1506 * easy chaining of multiple calls to this function. 1507 */ 1508 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest) 1509 { 1510 int err = of_property_read_u32(td->dev->of_node, param, dest); 1511 1512 if (err < 0) { 1513 dev_err(td->dev, "failed to read DT parameter %s: %d\n", 1514 param, err); 1515 return false; 1516 } 1517 1518 return true; 1519 } 1520 1521 /** 1522 * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem 1523 * @td: DFLL instance 1524 * 1525 * Read all the parameters required for operation in I2C mode. The parameters 1526 * can originate from the device tree or the regulator subsystem. 1527 * Returns 0 on success or -err on failure. 1528 */ 1529 static int dfll_fetch_i2c_params(struct tegra_dfll *td) 1530 { 1531 struct regmap *regmap; 1532 struct device *i2c_dev; 1533 struct i2c_client *i2c_client; 1534 int vsel_reg, vsel_mask; 1535 int ret; 1536 1537 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate)) 1538 return -EINVAL; 1539 1540 regmap = regulator_get_regmap(td->vdd_reg); 1541 i2c_dev = regmap_get_device(regmap); 1542 i2c_client = to_i2c_client(i2c_dev); 1543 1544 td->i2c_slave_addr = i2c_client->addr; 1545 1546 ret = regulator_get_hardware_vsel_register(td->vdd_reg, 1547 &vsel_reg, 1548 &vsel_mask); 1549 if (ret < 0) { 1550 dev_err(td->dev, 1551 "regulator unsuitable for DFLL I2C operation\n"); 1552 return -EINVAL; 1553 } 1554 td->i2c_reg = vsel_reg; 1555 1556 ret = dfll_build_i2c_lut(td); 1557 if (ret) { 1558 dev_err(td->dev, "couldn't build I2C LUT\n"); 1559 return ret; 1560 } 1561 1562 return 0; 1563 } 1564 1565 /** 1566 * dfll_fetch_common_params - read DFLL parameters from the device tree 1567 * @td: DFLL instance 1568 * 1569 * Read all the DT parameters that are common to both I2C and PWM operation. 1570 * Returns 0 on success or -EINVAL on any failure. 1571 */ 1572 static int dfll_fetch_common_params(struct tegra_dfll *td) 1573 { 1574 bool ok = true; 1575 1576 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl); 1577 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate); 1578 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode); 1579 ok &= read_dt_param(td, "nvidia,cf", &td->cf); 1580 ok &= read_dt_param(td, "nvidia,ci", &td->ci); 1581 ok &= read_dt_param(td, "nvidia,cg", &td->cg); 1582 td->cg_scale = of_property_read_bool(td->dev->of_node, 1583 "nvidia,cg-scale"); 1584 1585 if (of_property_read_string(td->dev->of_node, "clock-output-names", 1586 &td->output_clock_name)) { 1587 dev_err(td->dev, "missing clock-output-names property\n"); 1588 ok = false; 1589 } 1590 1591 return ok ? 0 : -EINVAL; 1592 } 1593 1594 /* 1595 * API exported to per-SoC platform drivers 1596 */ 1597 1598 /** 1599 * tegra_dfll_register - probe a Tegra DFLL device 1600 * @pdev: DFLL platform_device * 1601 * @soc: Per-SoC integration and characterization data for this DFLL instance 1602 * 1603 * Probe and initialize a DFLL device instance. Intended to be called 1604 * by a SoC-specific shim driver that passes in per-SoC integration 1605 * and configuration data via @soc. Returns 0 on success or -err on failure. 1606 */ 1607 int tegra_dfll_register(struct platform_device *pdev, 1608 struct tegra_dfll_soc_data *soc) 1609 { 1610 struct resource *mem; 1611 struct tegra_dfll *td; 1612 int ret; 1613 1614 if (!soc) { 1615 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n"); 1616 return -EINVAL; 1617 } 1618 1619 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL); 1620 if (!td) 1621 return -ENOMEM; 1622 td->dev = &pdev->dev; 1623 platform_set_drvdata(pdev, td); 1624 1625 td->soc = soc; 1626 1627 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); 1628 if (IS_ERR(td->vdd_reg)) { 1629 dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); 1630 return PTR_ERR(td->vdd_reg); 1631 } 1632 1633 td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); 1634 if (IS_ERR(td->dvco_rst)) { 1635 dev_err(td->dev, "couldn't get dvco reset\n"); 1636 return PTR_ERR(td->dvco_rst); 1637 } 1638 1639 ret = dfll_fetch_common_params(td); 1640 if (ret) { 1641 dev_err(td->dev, "couldn't parse device tree parameters\n"); 1642 return ret; 1643 } 1644 1645 ret = dfll_fetch_i2c_params(td); 1646 if (ret) 1647 return ret; 1648 1649 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1650 if (!mem) { 1651 dev_err(td->dev, "no control register resource\n"); 1652 return -ENODEV; 1653 } 1654 1655 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); 1656 if (!td->base) { 1657 dev_err(td->dev, "couldn't ioremap DFLL control registers\n"); 1658 return -ENODEV; 1659 } 1660 1661 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1662 if (!mem) { 1663 dev_err(td->dev, "no i2c_base resource\n"); 1664 return -ENODEV; 1665 } 1666 1667 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); 1668 if (!td->i2c_base) { 1669 dev_err(td->dev, "couldn't ioremap i2c_base resource\n"); 1670 return -ENODEV; 1671 } 1672 1673 mem = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1674 if (!mem) { 1675 dev_err(td->dev, "no i2c_controller_base resource\n"); 1676 return -ENODEV; 1677 } 1678 1679 td->i2c_controller_base = devm_ioremap(td->dev, mem->start, 1680 resource_size(mem)); 1681 if (!td->i2c_controller_base) { 1682 dev_err(td->dev, 1683 "couldn't ioremap i2c_controller_base resource\n"); 1684 return -ENODEV; 1685 } 1686 1687 mem = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1688 if (!mem) { 1689 dev_err(td->dev, "no lut_base resource\n"); 1690 return -ENODEV; 1691 } 1692 1693 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); 1694 if (!td->lut_base) { 1695 dev_err(td->dev, 1696 "couldn't ioremap lut_base resource\n"); 1697 return -ENODEV; 1698 } 1699 1700 ret = dfll_init_clks(td); 1701 if (ret) { 1702 dev_err(&pdev->dev, "DFLL clock init error\n"); 1703 return ret; 1704 } 1705 1706 /* Enable the clocks and set the device up */ 1707 ret = dfll_init(td); 1708 if (ret) 1709 return ret; 1710 1711 ret = dfll_register_clk(td); 1712 if (ret) { 1713 dev_err(&pdev->dev, "DFLL clk registration failed\n"); 1714 return ret; 1715 } 1716 1717 #ifdef CONFIG_DEBUG_FS 1718 dfll_debug_init(td); 1719 #endif 1720 1721 return 0; 1722 } 1723 EXPORT_SYMBOL(tegra_dfll_register); 1724 1725 /** 1726 * tegra_dfll_unregister - release all of the DFLL driver resources for a device 1727 * @pdev: DFLL platform_device * 1728 * 1729 * Unbind this driver from the DFLL hardware device represented by 1730 * @pdev. The DFLL must be disabled for this to succeed. Returns 0 1731 * upon success or -EBUSY if the DFLL is still active. 1732 */ 1733 int tegra_dfll_unregister(struct platform_device *pdev) 1734 { 1735 struct tegra_dfll *td = platform_get_drvdata(pdev); 1736 1737 /* Try to prevent removal while the DFLL is active */ 1738 if (td->mode != DFLL_DISABLED) { 1739 dev_err(&pdev->dev, 1740 "must disable DFLL before removing driver\n"); 1741 return -EBUSY; 1742 } 1743 1744 debugfs_remove_recursive(td->debugfs_dir); 1745 1746 dfll_unregister_clk(td); 1747 pm_runtime_disable(&pdev->dev); 1748 1749 clk_unprepare(td->ref_clk); 1750 clk_unprepare(td->soc_clk); 1751 clk_unprepare(td->i2c_clk); 1752 1753 reset_control_assert(td->dvco_rst); 1754 1755 return 0; 1756 } 1757 EXPORT_SYMBOL(tegra_dfll_unregister); 1758