1 /* 2 * clk-dfll.c - Tegra DFLL clock source common code 3 * 4 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved. 5 * 6 * Aleksandr Frid <afrid@nvidia.com> 7 * Paul Walmsley <pwalmsley@nvidia.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * This library is for the DVCO and DFLL IP blocks on the Tegra124 19 * SoC. These IP blocks together are also known at NVIDIA as 20 * "CL-DVFS". To try to avoid confusion, this code refers to them 21 * collectively as the "DFLL." 22 * 23 * The DFLL is a root clocksource which tolerates some amount of 24 * supply voltage noise. Tegra124 uses it to clock the fast CPU 25 * complex when the target CPU speed is above a particular rate. The 26 * DFLL can be operated in either open-loop mode or closed-loop mode. 27 * In open-loop mode, the DFLL generates an output clock appropriate 28 * to the supply voltage. In closed-loop mode, when configured with a 29 * target frequency, the DFLL minimizes supply voltage while 30 * delivering an average frequency equal to the target. 31 * 32 * Devices clocked by the DFLL must be able to tolerate frequency 33 * variation. In the case of the CPU, it's important to note that the 34 * CPU cycle time will vary. This has implications for 35 * performance-measurement code and any code that relies on the CPU 36 * cycle time to delay for a certain length of time. 37 * 38 */ 39 40 #include <linux/clk.h> 41 #include <linux/clk-provider.h> 42 #include <linux/debugfs.h> 43 #include <linux/device.h> 44 #include <linux/err.h> 45 #include <linux/i2c.h> 46 #include <linux/io.h> 47 #include <linux/kernel.h> 48 #include <linux/module.h> 49 #include <linux/of.h> 50 #include <linux/pinctrl/consumer.h> 51 #include <linux/pm_opp.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/regmap.h> 54 #include <linux/regulator/consumer.h> 55 #include <linux/reset.h> 56 #include <linux/seq_file.h> 57 58 #include "clk-dfll.h" 59 #include "cvb.h" 60 61 /* 62 * DFLL control registers - access via dfll_{readl,writel} 63 */ 64 65 /* DFLL_CTRL: DFLL control register */ 66 #define DFLL_CTRL 0x00 67 #define DFLL_CTRL_MODE_MASK 0x03 68 69 /* DFLL_CONFIG: DFLL sample rate control */ 70 #define DFLL_CONFIG 0x04 71 #define DFLL_CONFIG_DIV_MASK 0xff 72 #define DFLL_CONFIG_DIV_PRESCALE 32 73 74 /* DFLL_PARAMS: tuning coefficients for closed loop integrator */ 75 #define DFLL_PARAMS 0x08 76 #define DFLL_PARAMS_CG_SCALE (0x1 << 24) 77 #define DFLL_PARAMS_FORCE_MODE_SHIFT 22 78 #define DFLL_PARAMS_FORCE_MODE_MASK (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT) 79 #define DFLL_PARAMS_CF_PARAM_SHIFT 16 80 #define DFLL_PARAMS_CF_PARAM_MASK (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT) 81 #define DFLL_PARAMS_CI_PARAM_SHIFT 8 82 #define DFLL_PARAMS_CI_PARAM_MASK (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT) 83 #define DFLL_PARAMS_CG_PARAM_SHIFT 0 84 #define DFLL_PARAMS_CG_PARAM_MASK (0xff << DFLL_PARAMS_CG_PARAM_SHIFT) 85 86 /* DFLL_TUNE0: delay line configuration register 0 */ 87 #define DFLL_TUNE0 0x0c 88 89 /* DFLL_TUNE1: delay line configuration register 1 */ 90 #define DFLL_TUNE1 0x10 91 92 /* DFLL_FREQ_REQ: target DFLL frequency control */ 93 #define DFLL_FREQ_REQ 0x14 94 #define DFLL_FREQ_REQ_FORCE_ENABLE (0x1 << 28) 95 #define DFLL_FREQ_REQ_FORCE_SHIFT 16 96 #define DFLL_FREQ_REQ_FORCE_MASK (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT) 97 #define FORCE_MAX 2047 98 #define FORCE_MIN -2048 99 #define DFLL_FREQ_REQ_SCALE_SHIFT 8 100 #define DFLL_FREQ_REQ_SCALE_MASK (0xff << DFLL_FREQ_REQ_SCALE_SHIFT) 101 #define DFLL_FREQ_REQ_SCALE_MAX 256 102 #define DFLL_FREQ_REQ_FREQ_VALID (0x1 << 7) 103 #define DFLL_FREQ_REQ_MULT_SHIFT 0 104 #define DFLL_FREQ_REG_MULT_MASK (0x7f << DFLL_FREQ_REQ_MULT_SHIFT) 105 #define FREQ_MAX 127 106 107 /* DFLL_DROOP_CTRL: droop prevention control */ 108 #define DFLL_DROOP_CTRL 0x1c 109 110 /* DFLL_OUTPUT_CFG: closed loop mode control registers */ 111 /* NOTE: access via dfll_i2c_{readl,writel} */ 112 #define DFLL_OUTPUT_CFG 0x20 113 #define DFLL_OUTPUT_CFG_I2C_ENABLE (0x1 << 30) 114 #define OUT_MASK 0x3f 115 #define DFLL_OUTPUT_CFG_SAFE_SHIFT 24 116 #define DFLL_OUTPUT_CFG_SAFE_MASK \ 117 (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT) 118 #define DFLL_OUTPUT_CFG_MAX_SHIFT 16 119 #define DFLL_OUTPUT_CFG_MAX_MASK \ 120 (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT) 121 #define DFLL_OUTPUT_CFG_MIN_SHIFT 8 122 #define DFLL_OUTPUT_CFG_MIN_MASK \ 123 (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT) 124 #define DFLL_OUTPUT_CFG_PWM_DELTA (0x1 << 7) 125 #define DFLL_OUTPUT_CFG_PWM_ENABLE (0x1 << 6) 126 #define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT 0 127 #define DFLL_OUTPUT_CFG_PWM_DIV_MASK \ 128 (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT) 129 130 /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */ 131 #define DFLL_OUTPUT_FORCE 0x24 132 #define DFLL_OUTPUT_FORCE_ENABLE (0x1 << 6) 133 #define DFLL_OUTPUT_FORCE_VALUE_SHIFT 0 134 #define DFLL_OUTPUT_FORCE_VALUE_MASK \ 135 (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT) 136 137 /* DFLL_MONITOR_CTRL: internal monitor data source control */ 138 #define DFLL_MONITOR_CTRL 0x28 139 #define DFLL_MONITOR_CTRL_FREQ 6 140 141 /* DFLL_MONITOR_DATA: internal monitor data output */ 142 #define DFLL_MONITOR_DATA 0x2c 143 #define DFLL_MONITOR_DATA_NEW_MASK (0x1 << 16) 144 #define DFLL_MONITOR_DATA_VAL_SHIFT 0 145 #define DFLL_MONITOR_DATA_VAL_MASK (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT) 146 147 /* 148 * I2C output control registers - access via dfll_i2c_{readl,writel} 149 */ 150 151 /* DFLL_I2C_CFG: I2C controller configuration register */ 152 #define DFLL_I2C_CFG 0x40 153 #define DFLL_I2C_CFG_ARB_ENABLE (0x1 << 20) 154 #define DFLL_I2C_CFG_HS_CODE_SHIFT 16 155 #define DFLL_I2C_CFG_HS_CODE_MASK (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT) 156 #define DFLL_I2C_CFG_PACKET_ENABLE (0x1 << 15) 157 #define DFLL_I2C_CFG_SIZE_SHIFT 12 158 #define DFLL_I2C_CFG_SIZE_MASK (0x7 << DFLL_I2C_CFG_SIZE_SHIFT) 159 #define DFLL_I2C_CFG_SLAVE_ADDR_10 (0x1 << 10) 160 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT 1 161 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT 0 162 163 /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */ 164 #define DFLL_I2C_VDD_REG_ADDR 0x44 165 166 /* DFLL_I2C_STS: I2C controller status */ 167 #define DFLL_I2C_STS 0x48 168 #define DFLL_I2C_STS_I2C_LAST_SHIFT 1 169 #define DFLL_I2C_STS_I2C_REQ_PENDING 0x1 170 171 /* DFLL_INTR_STS: DFLL interrupt status register */ 172 #define DFLL_INTR_STS 0x5c 173 174 /* DFLL_INTR_EN: DFLL interrupt enable register */ 175 #define DFLL_INTR_EN 0x60 176 #define DFLL_INTR_MIN_MASK 0x1 177 #define DFLL_INTR_MAX_MASK 0x2 178 179 /* 180 * Integrated I2C controller registers - relative to td->i2c_controller_base 181 */ 182 183 /* DFLL_I2C_CLK_DIVISOR: I2C controller clock divisor */ 184 #define DFLL_I2C_CLK_DIVISOR 0x6c 185 #define DFLL_I2C_CLK_DIVISOR_MASK 0xffff 186 #define DFLL_I2C_CLK_DIVISOR_FS_SHIFT 16 187 #define DFLL_I2C_CLK_DIVISOR_HS_SHIFT 0 188 #define DFLL_I2C_CLK_DIVISOR_PREDIV 8 189 #define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV 12 190 191 /* 192 * Other constants 193 */ 194 195 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */ 196 #define MAX_DFLL_VOLTAGES 33 197 198 /* 199 * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware 200 * integrates the DVCO counter over - used for debug rate monitoring and 201 * droop control 202 */ 203 #define REF_CLK_CYC_PER_DVCO_SAMPLE 4 204 205 /* 206 * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this 207 * driver, in Hz 208 */ 209 #define REF_CLOCK_RATE 51000000UL 210 211 #define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2)) 212 #define MULT_TO_DVCO_RATE(mult, ref_rate) ((mult) * ((ref_rate) / 2)) 213 214 /** 215 * enum dfll_ctrl_mode - DFLL hardware operating mode 216 * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield) 217 * @DFLL_DISABLED: DFLL not generating an output clock 218 * @DFLL_OPEN_LOOP: DVCO running, but DFLL not adjusting voltage 219 * @DFLL_CLOSED_LOOP: DVCO running, and DFLL adjusting voltage to match 220 * the requested rate 221 * 222 * The integer corresponding to the last two states, minus one, is 223 * written to the DFLL hardware to change operating modes. 224 */ 225 enum dfll_ctrl_mode { 226 DFLL_UNINITIALIZED = 0, 227 DFLL_DISABLED = 1, 228 DFLL_OPEN_LOOP = 2, 229 DFLL_CLOSED_LOOP = 3, 230 }; 231 232 /** 233 * enum dfll_tune_range - voltage range that the driver believes it's in 234 * @DFLL_TUNE_UNINITIALIZED: DFLL tuning not yet programmed 235 * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode) 236 * 237 * Some DFLL tuning parameters may need to change depending on the 238 * DVCO's voltage; these states represent the ranges that the driver 239 * supports. These are software states; these values are never 240 * written into registers. 241 */ 242 enum dfll_tune_range { 243 DFLL_TUNE_UNINITIALIZED = 0, 244 DFLL_TUNE_LOW = 1, 245 }; 246 247 248 enum tegra_dfll_pmu_if { 249 TEGRA_DFLL_PMU_I2C = 0, 250 TEGRA_DFLL_PMU_PWM = 1, 251 }; 252 253 /** 254 * struct dfll_rate_req - target DFLL rate request data 255 * @rate: target frequency, after the postscaling 256 * @dvco_target_rate: target frequency, after the postscaling 257 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached 258 * @mult_bits: value to program to the MULT bits of the DFLL_FREQ_REQ register 259 * @scale_bits: value to program to the SCALE bits of the DFLL_FREQ_REQ register 260 */ 261 struct dfll_rate_req { 262 unsigned long rate; 263 unsigned long dvco_target_rate; 264 int lut_index; 265 u8 mult_bits; 266 u8 scale_bits; 267 }; 268 269 struct tegra_dfll { 270 struct device *dev; 271 struct tegra_dfll_soc_data *soc; 272 273 void __iomem *base; 274 void __iomem *i2c_base; 275 void __iomem *i2c_controller_base; 276 void __iomem *lut_base; 277 278 struct regulator *vdd_reg; 279 struct clk *soc_clk; 280 struct clk *ref_clk; 281 struct clk *i2c_clk; 282 struct clk *dfll_clk; 283 struct reset_control *dvco_rst; 284 unsigned long ref_rate; 285 unsigned long i2c_clk_rate; 286 unsigned long dvco_rate_min; 287 288 enum dfll_ctrl_mode mode; 289 enum dfll_tune_range tune_range; 290 struct dentry *debugfs_dir; 291 struct clk_hw dfll_clk_hw; 292 const char *output_clock_name; 293 struct dfll_rate_req last_req; 294 unsigned long last_unrounded_rate; 295 296 /* Parameters from DT */ 297 u32 droop_ctrl; 298 u32 sample_rate; 299 u32 force_mode; 300 u32 cf; 301 u32 ci; 302 u32 cg; 303 bool cg_scale; 304 305 /* I2C interface parameters */ 306 u32 i2c_fs_rate; 307 u32 i2c_reg; 308 u32 i2c_slave_addr; 309 310 /* lut array entries are regulator framework selectors or PWM values*/ 311 unsigned lut[MAX_DFLL_VOLTAGES]; 312 unsigned long lut_uv[MAX_DFLL_VOLTAGES]; 313 int lut_size; 314 u8 lut_bottom, lut_min, lut_max, lut_safe; 315 316 /* PWM interface */ 317 enum tegra_dfll_pmu_if pmu_if; 318 unsigned long pwm_rate; 319 struct pinctrl *pwm_pin; 320 struct pinctrl_state *pwm_enable_state; 321 struct pinctrl_state *pwm_disable_state; 322 u32 reg_init_uV; 323 }; 324 325 #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw) 326 327 /* mode_name: map numeric DFLL modes to names for friendly console messages */ 328 static const char * const mode_name[] = { 329 [DFLL_UNINITIALIZED] = "uninitialized", 330 [DFLL_DISABLED] = "disabled", 331 [DFLL_OPEN_LOOP] = "open_loop", 332 [DFLL_CLOSED_LOOP] = "closed_loop", 333 }; 334 335 /* 336 * Register accessors 337 */ 338 339 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs) 340 { 341 return __raw_readl(td->base + offs); 342 } 343 344 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs) 345 { 346 WARN_ON(offs >= DFLL_I2C_CFG); 347 __raw_writel(val, td->base + offs); 348 } 349 350 static inline void dfll_wmb(struct tegra_dfll *td) 351 { 352 dfll_readl(td, DFLL_CTRL); 353 } 354 355 /* I2C output control registers - for addresses above DFLL_I2C_CFG */ 356 357 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs) 358 { 359 return __raw_readl(td->i2c_base + offs); 360 } 361 362 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs) 363 { 364 __raw_writel(val, td->i2c_base + offs); 365 } 366 367 static inline void dfll_i2c_wmb(struct tegra_dfll *td) 368 { 369 dfll_i2c_readl(td, DFLL_I2C_CFG); 370 } 371 372 /** 373 * dfll_is_running - is the DFLL currently generating a clock? 374 * @td: DFLL instance 375 * 376 * If the DFLL is currently generating an output clock signal, return 377 * true; otherwise return false. 378 */ 379 static bool dfll_is_running(struct tegra_dfll *td) 380 { 381 return td->mode >= DFLL_OPEN_LOOP; 382 } 383 384 /* 385 * Runtime PM suspend/resume callbacks 386 */ 387 388 /** 389 * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL 390 * @dev: DFLL device * 391 * 392 * Enable all clocks needed by the DFLL. Assumes that clk_prepare() 393 * has already been called on all the clocks. 394 * 395 * XXX Should also handle context restore when returning from off. 396 */ 397 int tegra_dfll_runtime_resume(struct device *dev) 398 { 399 struct tegra_dfll *td = dev_get_drvdata(dev); 400 int ret; 401 402 ret = clk_enable(td->ref_clk); 403 if (ret) { 404 dev_err(dev, "could not enable ref clock: %d\n", ret); 405 return ret; 406 } 407 408 ret = clk_enable(td->soc_clk); 409 if (ret) { 410 dev_err(dev, "could not enable register clock: %d\n", ret); 411 clk_disable(td->ref_clk); 412 return ret; 413 } 414 415 ret = clk_enable(td->i2c_clk); 416 if (ret) { 417 dev_err(dev, "could not enable i2c clock: %d\n", ret); 418 clk_disable(td->soc_clk); 419 clk_disable(td->ref_clk); 420 return ret; 421 } 422 423 return 0; 424 } 425 EXPORT_SYMBOL(tegra_dfll_runtime_resume); 426 427 /** 428 * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL 429 * @dev: DFLL device * 430 * 431 * Disable all clocks needed by the DFLL. Assumes that other code 432 * will later call clk_unprepare(). 433 */ 434 int tegra_dfll_runtime_suspend(struct device *dev) 435 { 436 struct tegra_dfll *td = dev_get_drvdata(dev); 437 438 clk_disable(td->ref_clk); 439 clk_disable(td->soc_clk); 440 clk_disable(td->i2c_clk); 441 442 return 0; 443 } 444 EXPORT_SYMBOL(tegra_dfll_runtime_suspend); 445 446 /* 447 * DFLL tuning operations (per-voltage-range tuning settings) 448 */ 449 450 /** 451 * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage 452 * @td: DFLL instance 453 * 454 * Tune the DFLL oscillator parameters and the CPU clock shaper for 455 * the low-voltage range. These settings are valid for any voltage, 456 * but may not be optimal. 457 */ 458 static void dfll_tune_low(struct tegra_dfll *td) 459 { 460 td->tune_range = DFLL_TUNE_LOW; 461 462 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0); 463 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1); 464 dfll_wmb(td); 465 466 if (td->soc->set_clock_trimmers_low) 467 td->soc->set_clock_trimmers_low(); 468 } 469 470 /* 471 * Output clock scaler helpers 472 */ 473 474 /** 475 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate 476 * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field) 477 * @dvco_rate: the DVCO rate 478 * 479 * Apply the same scaling formula that the DFLL hardware uses to scale 480 * the DVCO rate. 481 */ 482 static unsigned long dfll_scale_dvco_rate(int scale_bits, 483 unsigned long dvco_rate) 484 { 485 return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX; 486 } 487 488 /* 489 * DFLL mode switching 490 */ 491 492 /** 493 * dfll_set_mode - change the DFLL control mode 494 * @td: DFLL instance 495 * @mode: DFLL control mode (see enum dfll_ctrl_mode) 496 * 497 * Change the DFLL's operating mode between disabled, open-loop mode, 498 * and closed-loop mode, or vice versa. 499 */ 500 static void dfll_set_mode(struct tegra_dfll *td, 501 enum dfll_ctrl_mode mode) 502 { 503 td->mode = mode; 504 dfll_writel(td, mode - 1, DFLL_CTRL); 505 dfll_wmb(td); 506 } 507 508 /* 509 * DVCO rate control 510 */ 511 512 static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min) 513 { 514 struct dev_pm_opp *opp; 515 unsigned long rate, prev_rate; 516 unsigned long uv, min_uv; 517 518 min_uv = td->lut_uv[out_min]; 519 for (rate = 0, prev_rate = 0; ; rate++) { 520 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); 521 if (IS_ERR(opp)) 522 break; 523 524 uv = dev_pm_opp_get_voltage(opp); 525 dev_pm_opp_put(opp); 526 527 if (uv && uv > min_uv) 528 return prev_rate; 529 530 prev_rate = rate; 531 } 532 533 return prev_rate; 534 } 535 536 /* 537 * DFLL-to-I2C controller interface 538 */ 539 540 /** 541 * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests 542 * @td: DFLL instance 543 * @enable: whether to enable or disable the I2C voltage requests 544 * 545 * Set the master enable control for I2C control value updates. If disabled, 546 * then I2C control messages are inhibited, regardless of the DFLL mode. 547 */ 548 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable) 549 { 550 u32 val; 551 552 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG); 553 554 if (enable) 555 val |= DFLL_OUTPUT_CFG_I2C_ENABLE; 556 else 557 val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE; 558 559 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); 560 dfll_i2c_wmb(td); 561 562 return 0; 563 } 564 565 566 /* 567 * DFLL-to-PWM controller interface 568 */ 569 570 /** 571 * dfll_pwm_set_output_enabled - enable/disable PWM voltage requests 572 * @td: DFLL instance 573 * @enable: whether to enable or disable the PWM voltage requests 574 * 575 * Set the master enable control for PWM control value updates. If disabled, 576 * then the PWM signal is not driven. Also configure the PWM output pad 577 * to the appropriate state. 578 */ 579 static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable) 580 { 581 int ret; 582 u32 val, div; 583 584 if (enable) { 585 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state); 586 if (ret < 0) { 587 dev_err(td->dev, "setting enable state failed\n"); 588 return -EINVAL; 589 } 590 val = dfll_readl(td, DFLL_OUTPUT_CFG); 591 val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK; 592 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate); 593 val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT) 594 & DFLL_OUTPUT_CFG_PWM_DIV_MASK; 595 dfll_writel(td, val, DFLL_OUTPUT_CFG); 596 dfll_wmb(td); 597 598 val |= DFLL_OUTPUT_CFG_PWM_ENABLE; 599 dfll_writel(td, val, DFLL_OUTPUT_CFG); 600 dfll_wmb(td); 601 } else { 602 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state); 603 if (ret < 0) 604 dev_warn(td->dev, "setting disable state failed\n"); 605 606 val = dfll_readl(td, DFLL_OUTPUT_CFG); 607 val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE; 608 dfll_writel(td, val, DFLL_OUTPUT_CFG); 609 dfll_wmb(td); 610 } 611 612 return 0; 613 } 614 615 /** 616 * dfll_set_force_output_value - set fixed value for force output 617 * @td: DFLL instance 618 * @out_val: value to force output 619 * 620 * Set the fixed value for force output, DFLL will output this value when 621 * force output is enabled. 622 */ 623 static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val) 624 { 625 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); 626 627 val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK); 628 dfll_writel(td, val, DFLL_OUTPUT_FORCE); 629 dfll_wmb(td); 630 631 return dfll_readl(td, DFLL_OUTPUT_FORCE); 632 } 633 634 /** 635 * dfll_set_force_output_enabled - enable/disable force output 636 * @td: DFLL instance 637 * @enable: whether to enable or disable the force output 638 * 639 * Set the enable control for fouce output with fixed value. 640 */ 641 static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable) 642 { 643 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); 644 645 if (enable) 646 val |= DFLL_OUTPUT_FORCE_ENABLE; 647 else 648 val &= ~DFLL_OUTPUT_FORCE_ENABLE; 649 650 dfll_writel(td, val, DFLL_OUTPUT_FORCE); 651 dfll_wmb(td); 652 } 653 654 /** 655 * dfll_force_output - force output a fixed value 656 * @td: DFLL instance 657 * @out_sel: value to force output 658 * 659 * Set the fixed value for force output, DFLL will output this value. 660 */ 661 static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel) 662 { 663 u32 val; 664 665 if (out_sel > OUT_MASK) 666 return -EINVAL; 667 668 val = dfll_set_force_output_value(td, out_sel); 669 if ((td->mode < DFLL_CLOSED_LOOP) && 670 !(val & DFLL_OUTPUT_FORCE_ENABLE)) { 671 dfll_set_force_output_enabled(td, true); 672 } 673 674 return 0; 675 } 676 677 /** 678 * dfll_load_lut - load the voltage lookup table 679 * @td: struct tegra_dfll * 680 * 681 * Load the voltage-to-PMIC register value lookup table into the DFLL 682 * IP block memory. Look-up tables can be loaded at any time. 683 */ 684 static void dfll_load_i2c_lut(struct tegra_dfll *td) 685 { 686 int i, lut_index; 687 u32 val; 688 689 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) { 690 if (i < td->lut_min) 691 lut_index = td->lut_min; 692 else if (i > td->lut_max) 693 lut_index = td->lut_max; 694 else 695 lut_index = i; 696 697 val = regulator_list_hardware_vsel(td->vdd_reg, 698 td->lut[lut_index]); 699 __raw_writel(val, td->lut_base + i * 4); 700 } 701 702 dfll_i2c_wmb(td); 703 } 704 705 /** 706 * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface 707 * @td: DFLL instance 708 * 709 * During DFLL driver initialization, program the DFLL-I2C interface 710 * with the PMU slave address, vdd register offset, and transfer mode. 711 * This data is used by the DFLL to automatically construct I2C 712 * voltage-set commands, which are then passed to the DFLL's internal 713 * I2C controller. 714 */ 715 static void dfll_init_i2c_if(struct tegra_dfll *td) 716 { 717 u32 val; 718 719 if (td->i2c_slave_addr > 0x7f) { 720 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; 721 val |= DFLL_I2C_CFG_SLAVE_ADDR_10; 722 } else { 723 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; 724 } 725 val |= DFLL_I2C_CFG_SIZE_MASK; 726 val |= DFLL_I2C_CFG_ARB_ENABLE; 727 dfll_i2c_writel(td, val, DFLL_I2C_CFG); 728 729 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR); 730 731 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); 732 BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK)); 733 val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT; 734 735 /* default hs divisor just in case */ 736 val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT; 737 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); 738 dfll_i2c_wmb(td); 739 } 740 741 /** 742 * dfll_init_out_if - prepare DFLL-to-PMIC interface 743 * @td: DFLL instance 744 * 745 * During DFLL driver initialization or resume from context loss, 746 * disable the I2C command output to the PMIC, set safe voltage and 747 * output limits, and disable and clear limit interrupts. 748 */ 749 static void dfll_init_out_if(struct tegra_dfll *td) 750 { 751 u32 val; 752 753 td->lut_min = td->lut_bottom; 754 td->lut_max = td->lut_size - 1; 755 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0); 756 757 /* clear DFLL_OUTPUT_CFG before setting new value */ 758 dfll_writel(td, 0, DFLL_OUTPUT_CFG); 759 dfll_wmb(td); 760 761 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | 762 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | 763 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); 764 dfll_writel(td, val, DFLL_OUTPUT_CFG); 765 dfll_wmb(td); 766 767 dfll_writel(td, 0, DFLL_OUTPUT_FORCE); 768 dfll_i2c_writel(td, 0, DFLL_INTR_EN); 769 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK, 770 DFLL_INTR_STS); 771 772 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) { 773 u32 vinit = td->reg_init_uV; 774 int vstep = td->soc->alignment.step_uv; 775 unsigned long vmin = td->lut_uv[0]; 776 777 /* set initial voltage */ 778 if ((vinit >= vmin) && vstep) { 779 unsigned int vsel; 780 781 vsel = DIV_ROUND_UP((vinit - vmin), vstep); 782 dfll_force_output(td, vsel); 783 } 784 } else { 785 dfll_load_i2c_lut(td); 786 dfll_init_i2c_if(td); 787 } 788 } 789 790 /* 791 * Set/get the DFLL's targeted output clock rate 792 */ 793 794 /** 795 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate 796 * @td: DFLL instance 797 * @rate: clock rate 798 * 799 * Determines the index of a I2C LUT entry for a voltage that approximately 800 * produces the given DFLL clock rate. This is used when forcing a value 801 * to the integrator during rate changes. Returns -ENOENT if a suitable 802 * LUT index is not found. 803 */ 804 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) 805 { 806 struct dev_pm_opp *opp; 807 unsigned long uv; 808 int i; 809 810 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); 811 if (IS_ERR(opp)) 812 return PTR_ERR(opp); 813 814 uv = dev_pm_opp_get_voltage(opp); 815 dev_pm_opp_put(opp); 816 817 for (i = td->lut_bottom; i < td->lut_size; i++) { 818 if (td->lut_uv[i] >= uv) 819 return i; 820 } 821 822 return -ENOENT; 823 } 824 825 /** 826 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate 827 * @td: DFLL instance 828 * @req: DFLL-rate-request structure 829 * @rate: the desired DFLL rate 830 * 831 * Populate the DFLL-rate-request record @req fields with the scale_bits 832 * and mult_bits fields, based on the target input rate. Returns 0 upon 833 * success, or -EINVAL if the requested rate in req->rate is too high 834 * or low for the DFLL to generate. 835 */ 836 static int dfll_calculate_rate_request(struct tegra_dfll *td, 837 struct dfll_rate_req *req, 838 unsigned long rate) 839 { 840 u32 val; 841 842 /* 843 * If requested rate is below the minimum DVCO rate, active the scaler. 844 * In the future the DVCO minimum voltage should be selected based on 845 * chip temperature and the actual minimum rate should be calibrated 846 * at runtime. 847 */ 848 req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1; 849 if (rate < td->dvco_rate_min) { 850 int scale; 851 852 scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX, 853 td->dvco_rate_min / 1000); 854 if (!scale) { 855 dev_err(td->dev, "%s: Rate %lu is too low\n", 856 __func__, rate); 857 return -EINVAL; 858 } 859 req->scale_bits = scale - 1; 860 rate = td->dvco_rate_min; 861 } 862 863 /* Convert requested rate into frequency request and scale settings */ 864 val = DVCO_RATE_TO_MULT(rate, td->ref_rate); 865 if (val > FREQ_MAX) { 866 dev_err(td->dev, "%s: Rate %lu is above dfll range\n", 867 __func__, rate); 868 return -EINVAL; 869 } 870 req->mult_bits = val; 871 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate); 872 req->rate = dfll_scale_dvco_rate(req->scale_bits, 873 req->dvco_target_rate); 874 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate); 875 if (req->lut_index < 0) 876 return req->lut_index; 877 878 return 0; 879 } 880 881 /** 882 * dfll_set_frequency_request - start the frequency change operation 883 * @td: DFLL instance 884 * @req: rate request structure 885 * 886 * Tell the DFLL to try to change its output frequency to the 887 * frequency represented by @req. DFLL must be in closed-loop mode. 888 */ 889 static void dfll_set_frequency_request(struct tegra_dfll *td, 890 struct dfll_rate_req *req) 891 { 892 u32 val = 0; 893 int force_val; 894 int coef = 128; /* FIXME: td->cg_scale? */; 895 896 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; 897 force_val = clamp(force_val, FORCE_MIN, FORCE_MAX); 898 899 val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT; 900 val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT; 901 val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) & 902 DFLL_FREQ_REQ_FORCE_MASK; 903 val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE; 904 905 dfll_writel(td, val, DFLL_FREQ_REQ); 906 dfll_wmb(td); 907 } 908 909 /** 910 * tegra_dfll_request_rate - set the next rate for the DFLL to tune to 911 * @td: DFLL instance 912 * @rate: clock rate to target 913 * 914 * Convert the requested clock rate @rate into the DFLL control logic 915 * settings. In closed-loop mode, update new settings immediately to 916 * adjust DFLL output rate accordingly. Otherwise, just save them 917 * until the next switch to closed loop. Returns 0 upon success, 918 * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL 919 * if @rate is outside the DFLL's tunable range. 920 */ 921 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate) 922 { 923 int ret; 924 struct dfll_rate_req req; 925 926 if (td->mode == DFLL_UNINITIALIZED) { 927 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n", 928 __func__, mode_name[td->mode]); 929 return -EPERM; 930 } 931 932 ret = dfll_calculate_rate_request(td, &req, rate); 933 if (ret) 934 return ret; 935 936 td->last_unrounded_rate = rate; 937 td->last_req = req; 938 939 if (td->mode == DFLL_CLOSED_LOOP) 940 dfll_set_frequency_request(td, &td->last_req); 941 942 return 0; 943 } 944 945 /* 946 * DFLL enable/disable & open-loop <-> closed-loop transitions 947 */ 948 949 /** 950 * dfll_disable - switch from open-loop mode to disabled mode 951 * @td: DFLL instance 952 * 953 * Switch from OPEN_LOOP state to DISABLED state. Returns 0 upon success 954 * or -EPERM if the DFLL is not currently in open-loop mode. 955 */ 956 static int dfll_disable(struct tegra_dfll *td) 957 { 958 if (td->mode != DFLL_OPEN_LOOP) { 959 dev_err(td->dev, "cannot disable DFLL in %s mode\n", 960 mode_name[td->mode]); 961 return -EINVAL; 962 } 963 964 dfll_set_mode(td, DFLL_DISABLED); 965 pm_runtime_put_sync(td->dev); 966 967 return 0; 968 } 969 970 /** 971 * dfll_enable - switch a disabled DFLL to open-loop mode 972 * @td: DFLL instance 973 * 974 * Switch from DISABLED state to OPEN_LOOP state. Returns 0 upon success 975 * or -EPERM if the DFLL is not currently disabled. 976 */ 977 static int dfll_enable(struct tegra_dfll *td) 978 { 979 if (td->mode != DFLL_DISABLED) { 980 dev_err(td->dev, "cannot enable DFLL in %s mode\n", 981 mode_name[td->mode]); 982 return -EPERM; 983 } 984 985 pm_runtime_get_sync(td->dev); 986 dfll_set_mode(td, DFLL_OPEN_LOOP); 987 988 return 0; 989 } 990 991 /** 992 * dfll_set_open_loop_config - prepare to switch to open-loop mode 993 * @td: DFLL instance 994 * 995 * Prepare to switch the DFLL to open-loop mode. This switches the 996 * DFLL to the low-voltage tuning range, ensures that I2C output 997 * forcing is disabled, and disables the output clock rate scaler. 998 * The DFLL's low-voltage tuning range parameters must be 999 * characterized to keep the downstream device stable at any DVCO 1000 * input voltage. No return value. 1001 */ 1002 static void dfll_set_open_loop_config(struct tegra_dfll *td) 1003 { 1004 u32 val; 1005 1006 /* always tune low (safe) in open loop */ 1007 if (td->tune_range != DFLL_TUNE_LOW) 1008 dfll_tune_low(td); 1009 1010 val = dfll_readl(td, DFLL_FREQ_REQ); 1011 val |= DFLL_FREQ_REQ_SCALE_MASK; 1012 val &= ~DFLL_FREQ_REQ_FORCE_ENABLE; 1013 dfll_writel(td, val, DFLL_FREQ_REQ); 1014 dfll_wmb(td); 1015 } 1016 1017 /** 1018 * tegra_dfll_lock - switch from open-loop to closed-loop mode 1019 * @td: DFLL instance 1020 * 1021 * Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success, 1022 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the 1023 * DFLL is not currently in open-loop mode. 1024 */ 1025 static int dfll_lock(struct tegra_dfll *td) 1026 { 1027 struct dfll_rate_req *req = &td->last_req; 1028 1029 switch (td->mode) { 1030 case DFLL_CLOSED_LOOP: 1031 return 0; 1032 1033 case DFLL_OPEN_LOOP: 1034 if (req->rate == 0) { 1035 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n", 1036 __func__); 1037 return -EINVAL; 1038 } 1039 1040 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) 1041 dfll_pwm_set_output_enabled(td, true); 1042 else 1043 dfll_i2c_set_output_enabled(td, true); 1044 1045 dfll_set_mode(td, DFLL_CLOSED_LOOP); 1046 dfll_set_frequency_request(td, req); 1047 dfll_set_force_output_enabled(td, false); 1048 return 0; 1049 1050 default: 1051 BUG_ON(td->mode > DFLL_CLOSED_LOOP); 1052 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n", 1053 __func__, mode_name[td->mode]); 1054 return -EPERM; 1055 } 1056 } 1057 1058 /** 1059 * tegra_dfll_unlock - switch from closed-loop to open-loop mode 1060 * @td: DFLL instance 1061 * 1062 * Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success, 1063 * or -EPERM if the DFLL is not currently in open-loop mode. 1064 */ 1065 static int dfll_unlock(struct tegra_dfll *td) 1066 { 1067 switch (td->mode) { 1068 case DFLL_CLOSED_LOOP: 1069 dfll_set_open_loop_config(td); 1070 dfll_set_mode(td, DFLL_OPEN_LOOP); 1071 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) 1072 dfll_pwm_set_output_enabled(td, false); 1073 else 1074 dfll_i2c_set_output_enabled(td, false); 1075 return 0; 1076 1077 case DFLL_OPEN_LOOP: 1078 return 0; 1079 1080 default: 1081 BUG_ON(td->mode > DFLL_CLOSED_LOOP); 1082 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n", 1083 __func__, mode_name[td->mode]); 1084 return -EPERM; 1085 } 1086 } 1087 1088 /* 1089 * Clock framework integration 1090 * 1091 * When the DFLL is being controlled by the CCF, always enter closed loop 1092 * mode when the clk is enabled. This requires that a DFLL rate request 1093 * has been set beforehand, which implies that a clk_set_rate() call is 1094 * always required before a clk_enable(). 1095 */ 1096 1097 static int dfll_clk_is_enabled(struct clk_hw *hw) 1098 { 1099 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1100 1101 return dfll_is_running(td); 1102 } 1103 1104 static int dfll_clk_enable(struct clk_hw *hw) 1105 { 1106 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1107 int ret; 1108 1109 ret = dfll_enable(td); 1110 if (ret) 1111 return ret; 1112 1113 ret = dfll_lock(td); 1114 if (ret) 1115 dfll_disable(td); 1116 1117 return ret; 1118 } 1119 1120 static void dfll_clk_disable(struct clk_hw *hw) 1121 { 1122 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1123 int ret; 1124 1125 ret = dfll_unlock(td); 1126 if (!ret) 1127 dfll_disable(td); 1128 } 1129 1130 static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw, 1131 unsigned long parent_rate) 1132 { 1133 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1134 1135 return td->last_unrounded_rate; 1136 } 1137 1138 /* Must use determine_rate since it allows for rates exceeding 2^31-1 */ 1139 static int dfll_clk_determine_rate(struct clk_hw *hw, 1140 struct clk_rate_request *clk_req) 1141 { 1142 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1143 struct dfll_rate_req req; 1144 int ret; 1145 1146 ret = dfll_calculate_rate_request(td, &req, clk_req->rate); 1147 if (ret) 1148 return ret; 1149 1150 /* 1151 * Don't set the rounded rate, since it doesn't really matter as 1152 * the output rate will be voltage controlled anyway, and cpufreq 1153 * freaks out if any rounding happens. 1154 */ 1155 1156 return 0; 1157 } 1158 1159 static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate, 1160 unsigned long parent_rate) 1161 { 1162 struct tegra_dfll *td = clk_hw_to_dfll(hw); 1163 1164 return dfll_request_rate(td, rate); 1165 } 1166 1167 static const struct clk_ops dfll_clk_ops = { 1168 .is_enabled = dfll_clk_is_enabled, 1169 .enable = dfll_clk_enable, 1170 .disable = dfll_clk_disable, 1171 .recalc_rate = dfll_clk_recalc_rate, 1172 .determine_rate = dfll_clk_determine_rate, 1173 .set_rate = dfll_clk_set_rate, 1174 }; 1175 1176 static struct clk_init_data dfll_clk_init_data = { 1177 .ops = &dfll_clk_ops, 1178 .num_parents = 0, 1179 }; 1180 1181 /** 1182 * dfll_register_clk - register the DFLL output clock with the clock framework 1183 * @td: DFLL instance 1184 * 1185 * Register the DFLL's output clock with the Linux clock framework and register 1186 * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL 1187 * or -ENOMEM upon failure. 1188 */ 1189 static int dfll_register_clk(struct tegra_dfll *td) 1190 { 1191 int ret; 1192 1193 dfll_clk_init_data.name = td->output_clock_name; 1194 td->dfll_clk_hw.init = &dfll_clk_init_data; 1195 1196 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw); 1197 if (IS_ERR(td->dfll_clk)) { 1198 dev_err(td->dev, "DFLL clock registration error\n"); 1199 return -EINVAL; 1200 } 1201 1202 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get, 1203 td->dfll_clk); 1204 if (ret) { 1205 dev_err(td->dev, "of_clk_add_provider() failed\n"); 1206 1207 clk_unregister(td->dfll_clk); 1208 return ret; 1209 } 1210 1211 return 0; 1212 } 1213 1214 /** 1215 * dfll_unregister_clk - unregister the DFLL output clock 1216 * @td: DFLL instance 1217 * 1218 * Unregister the DFLL's output clock from the Linux clock framework 1219 * and from clkdev. No return value. 1220 */ 1221 static void dfll_unregister_clk(struct tegra_dfll *td) 1222 { 1223 of_clk_del_provider(td->dev->of_node); 1224 clk_unregister(td->dfll_clk); 1225 td->dfll_clk = NULL; 1226 } 1227 1228 /* 1229 * Debugfs interface 1230 */ 1231 1232 #ifdef CONFIG_DEBUG_FS 1233 /* 1234 * Monitor control 1235 */ 1236 1237 /** 1238 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq 1239 * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield 1240 * @ref_rate: DFLL reference clock rate 1241 * 1242 * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles 1243 * per second. Returns the converted value. 1244 */ 1245 static u64 dfll_calc_monitored_rate(u32 monitor_data, 1246 unsigned long ref_rate) 1247 { 1248 return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE); 1249 } 1250 1251 /** 1252 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor 1253 * @td: DFLL instance 1254 * 1255 * If the DFLL is enabled, return the last rate reported by the DFLL's 1256 * internal monitoring hardware. This works in both open-loop and 1257 * closed-loop mode, and takes the output scaler setting into account. 1258 * Assumes that the monitor was programmed to monitor frequency before 1259 * the sample period started. If the driver believes that the DFLL is 1260 * currently uninitialized or disabled, it will return 0, since 1261 * otherwise the DFLL monitor data register will return the last 1262 * measured rate from when the DFLL was active. 1263 */ 1264 static u64 dfll_read_monitor_rate(struct tegra_dfll *td) 1265 { 1266 u32 v, s; 1267 u64 pre_scaler_rate, post_scaler_rate; 1268 1269 if (!dfll_is_running(td)) 1270 return 0; 1271 1272 v = dfll_readl(td, DFLL_MONITOR_DATA); 1273 v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT; 1274 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate); 1275 1276 s = dfll_readl(td, DFLL_FREQ_REQ); 1277 s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT; 1278 post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate); 1279 1280 return post_scaler_rate; 1281 } 1282 1283 static int attr_enable_get(void *data, u64 *val) 1284 { 1285 struct tegra_dfll *td = data; 1286 1287 *val = dfll_is_running(td); 1288 1289 return 0; 1290 } 1291 static int attr_enable_set(void *data, u64 val) 1292 { 1293 struct tegra_dfll *td = data; 1294 1295 return val ? dfll_enable(td) : dfll_disable(td); 1296 } 1297 DEFINE_SIMPLE_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set, 1298 "%llu\n"); 1299 1300 static int attr_lock_get(void *data, u64 *val) 1301 { 1302 struct tegra_dfll *td = data; 1303 1304 *val = (td->mode == DFLL_CLOSED_LOOP); 1305 1306 return 0; 1307 } 1308 static int attr_lock_set(void *data, u64 val) 1309 { 1310 struct tegra_dfll *td = data; 1311 1312 return val ? dfll_lock(td) : dfll_unlock(td); 1313 } 1314 DEFINE_SIMPLE_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set, 1315 "%llu\n"); 1316 1317 static int attr_rate_get(void *data, u64 *val) 1318 { 1319 struct tegra_dfll *td = data; 1320 1321 *val = dfll_read_monitor_rate(td); 1322 1323 return 0; 1324 } 1325 1326 static int attr_rate_set(void *data, u64 val) 1327 { 1328 struct tegra_dfll *td = data; 1329 1330 return dfll_request_rate(td, val); 1331 } 1332 DEFINE_SIMPLE_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n"); 1333 1334 static int attr_registers_show(struct seq_file *s, void *data) 1335 { 1336 u32 val, offs; 1337 struct tegra_dfll *td = s->private; 1338 1339 seq_puts(s, "CONTROL REGISTERS:\n"); 1340 for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) { 1341 if (offs == DFLL_OUTPUT_CFG) 1342 val = dfll_i2c_readl(td, offs); 1343 else 1344 val = dfll_readl(td, offs); 1345 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val); 1346 } 1347 1348 seq_puts(s, "\nI2C and INTR REGISTERS:\n"); 1349 for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4) 1350 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1351 dfll_i2c_readl(td, offs)); 1352 for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4) 1353 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1354 dfll_i2c_readl(td, offs)); 1355 1356 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) { 1357 seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n"); 1358 offs = DFLL_I2C_CLK_DIVISOR; 1359 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1360 __raw_readl(td->i2c_controller_base + offs)); 1361 1362 seq_puts(s, "\nLUT:\n"); 1363 for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4) 1364 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, 1365 __raw_readl(td->lut_base + offs)); 1366 } 1367 1368 return 0; 1369 } 1370 1371 DEFINE_SHOW_ATTRIBUTE(attr_registers); 1372 1373 static void dfll_debug_init(struct tegra_dfll *td) 1374 { 1375 struct dentry *root; 1376 1377 if (!td || (td->mode == DFLL_UNINITIALIZED)) 1378 return; 1379 1380 root = debugfs_create_dir("tegra_dfll_fcpu", NULL); 1381 td->debugfs_dir = root; 1382 1383 debugfs_create_file("enable", S_IRUGO | S_IWUSR, root, td, &enable_fops); 1384 debugfs_create_file("lock", S_IRUGO, root, td, &lock_fops); 1385 debugfs_create_file("rate", S_IRUGO, root, td, &rate_fops); 1386 debugfs_create_file("registers", S_IRUGO, root, td, &attr_registers_fops); 1387 } 1388 1389 #else 1390 static void inline dfll_debug_init(struct tegra_dfll *td) { } 1391 #endif /* CONFIG_DEBUG_FS */ 1392 1393 /* 1394 * DFLL initialization 1395 */ 1396 1397 /** 1398 * dfll_set_default_params - program non-output related DFLL parameters 1399 * @td: DFLL instance 1400 * 1401 * During DFLL driver initialization or resume from context loss, 1402 * program parameters for the closed loop integrator, DVCO tuning, 1403 * voltage droop control and monitor control. 1404 */ 1405 static void dfll_set_default_params(struct tegra_dfll *td) 1406 { 1407 u32 val; 1408 1409 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); 1410 BUG_ON(val > DFLL_CONFIG_DIV_MASK); 1411 dfll_writel(td, val, DFLL_CONFIG); 1412 1413 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | 1414 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) | 1415 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) | 1416 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | 1417 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0); 1418 dfll_writel(td, val, DFLL_PARAMS); 1419 1420 dfll_tune_low(td); 1421 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL); 1422 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL); 1423 } 1424 1425 /** 1426 * dfll_init_clks - clk_get() the DFLL source clocks 1427 * @td: DFLL instance 1428 * 1429 * Call clk_get() on the DFLL source clocks and save the pointers for later 1430 * use. Returns 0 upon success or error (see devm_clk_get) if one or more 1431 * of the clocks couldn't be looked up. 1432 */ 1433 static int dfll_init_clks(struct tegra_dfll *td) 1434 { 1435 td->ref_clk = devm_clk_get(td->dev, "ref"); 1436 if (IS_ERR(td->ref_clk)) { 1437 dev_err(td->dev, "missing ref clock\n"); 1438 return PTR_ERR(td->ref_clk); 1439 } 1440 1441 td->soc_clk = devm_clk_get(td->dev, "soc"); 1442 if (IS_ERR(td->soc_clk)) { 1443 dev_err(td->dev, "missing soc clock\n"); 1444 return PTR_ERR(td->soc_clk); 1445 } 1446 1447 td->i2c_clk = devm_clk_get(td->dev, "i2c"); 1448 if (IS_ERR(td->i2c_clk)) { 1449 dev_err(td->dev, "missing i2c clock\n"); 1450 return PTR_ERR(td->i2c_clk); 1451 } 1452 td->i2c_clk_rate = clk_get_rate(td->i2c_clk); 1453 1454 return 0; 1455 } 1456 1457 /** 1458 * dfll_init - Prepare the DFLL IP block for use 1459 * @td: DFLL instance 1460 * 1461 * Do everything necessary to prepare the DFLL IP block for use. The 1462 * DFLL will be left in DISABLED state. Called by dfll_probe(). 1463 * Returns 0 upon success, or passes along the error from whatever 1464 * function returned it. 1465 */ 1466 static int dfll_init(struct tegra_dfll *td) 1467 { 1468 int ret; 1469 1470 td->ref_rate = clk_get_rate(td->ref_clk); 1471 if (td->ref_rate != REF_CLOCK_RATE) { 1472 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu", 1473 td->ref_rate, REF_CLOCK_RATE); 1474 return -EINVAL; 1475 } 1476 1477 reset_control_deassert(td->dvco_rst); 1478 1479 ret = clk_prepare(td->ref_clk); 1480 if (ret) { 1481 dev_err(td->dev, "failed to prepare ref_clk\n"); 1482 return ret; 1483 } 1484 1485 ret = clk_prepare(td->soc_clk); 1486 if (ret) { 1487 dev_err(td->dev, "failed to prepare soc_clk\n"); 1488 goto di_err1; 1489 } 1490 1491 ret = clk_prepare(td->i2c_clk); 1492 if (ret) { 1493 dev_err(td->dev, "failed to prepare i2c_clk\n"); 1494 goto di_err2; 1495 } 1496 1497 td->last_unrounded_rate = 0; 1498 1499 pm_runtime_enable(td->dev); 1500 pm_runtime_get_sync(td->dev); 1501 1502 dfll_set_mode(td, DFLL_DISABLED); 1503 dfll_set_default_params(td); 1504 1505 if (td->soc->init_clock_trimmers) 1506 td->soc->init_clock_trimmers(); 1507 1508 dfll_set_open_loop_config(td); 1509 1510 dfll_init_out_if(td); 1511 1512 pm_runtime_put_sync(td->dev); 1513 1514 return 0; 1515 1516 di_err2: 1517 clk_unprepare(td->soc_clk); 1518 di_err1: 1519 clk_unprepare(td->ref_clk); 1520 1521 reset_control_assert(td->dvco_rst); 1522 1523 return ret; 1524 } 1525 1526 /* 1527 * DT data fetch 1528 */ 1529 1530 /* 1531 * Find a PMIC voltage register-to-voltage mapping for the given voltage. 1532 * An exact voltage match is required. 1533 */ 1534 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) 1535 { 1536 int i, n_voltages, reg_uV; 1537 1538 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) 1539 return -EINVAL; 1540 1541 n_voltages = regulator_count_voltages(td->vdd_reg); 1542 for (i = 0; i < n_voltages; i++) { 1543 reg_uV = regulator_list_voltage(td->vdd_reg, i); 1544 if (reg_uV < 0) 1545 break; 1546 1547 if (uV == reg_uV) 1548 return i; 1549 } 1550 1551 dev_err(td->dev, "no voltage map entry for %d uV\n", uV); 1552 return -EINVAL; 1553 } 1554 1555 /* 1556 * Find a PMIC voltage register-to-voltage mapping for the given voltage, 1557 * rounding up to the closest supported voltage. 1558 * */ 1559 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) 1560 { 1561 int i, n_voltages, reg_uV; 1562 1563 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) 1564 return -EINVAL; 1565 1566 n_voltages = regulator_count_voltages(td->vdd_reg); 1567 for (i = 0; i < n_voltages; i++) { 1568 reg_uV = regulator_list_voltage(td->vdd_reg, i); 1569 if (reg_uV < 0) 1570 break; 1571 1572 if (uV <= reg_uV) 1573 return i; 1574 } 1575 1576 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV); 1577 return -EINVAL; 1578 } 1579 1580 /* 1581 * dfll_build_pwm_lut - build the PWM regulator lookup table 1582 * @td: DFLL instance 1583 * @v_max: Vmax from OPP table 1584 * 1585 * Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC. 1586 * In this case closed loop output is controlling duty cycle directly. The s/w 1587 * look-up that maps PWM duty cycle to voltage is still built by this function. 1588 */ 1589 static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max) 1590 { 1591 int i; 1592 unsigned long rate, reg_volt; 1593 u8 lut_bottom = MAX_DFLL_VOLTAGES; 1594 int v_min = td->soc->cvb->min_millivolts * 1000; 1595 1596 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) { 1597 reg_volt = td->lut_uv[i]; 1598 1599 /* since opp voltage is exact mv */ 1600 reg_volt = (reg_volt / 1000) * 1000; 1601 if (reg_volt > v_max) 1602 break; 1603 1604 td->lut[i] = i; 1605 if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min)) 1606 lut_bottom = i; 1607 } 1608 1609 /* determine voltage boundaries */ 1610 td->lut_size = i; 1611 if ((lut_bottom == MAX_DFLL_VOLTAGES) || 1612 (lut_bottom + 1 >= td->lut_size)) { 1613 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n", 1614 td->soc->cvb->min_millivolts); 1615 return -EINVAL; 1616 } 1617 td->lut_bottom = lut_bottom; 1618 1619 /* determine rate boundaries */ 1620 rate = get_dvco_rate_below(td, td->lut_bottom); 1621 if (!rate) { 1622 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n", 1623 td->soc->cvb->min_millivolts); 1624 return -EINVAL; 1625 } 1626 td->dvco_rate_min = rate; 1627 1628 return 0; 1629 } 1630 1631 /** 1632 * dfll_build_i2c_lut - build the I2C voltage register lookup table 1633 * @td: DFLL instance 1634 * @v_max: Vmax from OPP table 1635 * 1636 * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with 1637 * PMIC voltage register values that span the entire DFLL operating range. 1638 * This function builds the look-up table based on the OPP table provided by 1639 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC 1640 * register-to-voltage mapping queried from the regulator framework. 1641 * 1642 * On success, fills in td->lut and returns 0, or -err on failure. 1643 */ 1644 static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) 1645 { 1646 unsigned long rate, v, v_opp; 1647 int ret = -EINVAL; 1648 int j, selector, lut; 1649 1650 v = td->soc->cvb->min_millivolts * 1000; 1651 lut = find_vdd_map_entry_exact(td, v); 1652 if (lut < 0) 1653 goto out; 1654 td->lut[0] = lut; 1655 td->lut_bottom = 0; 1656 1657 for (j = 1, rate = 0; ; rate++) { 1658 struct dev_pm_opp *opp; 1659 1660 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); 1661 if (IS_ERR(opp)) 1662 break; 1663 v_opp = dev_pm_opp_get_voltage(opp); 1664 1665 if (v_opp <= td->soc->cvb->min_millivolts * 1000) 1666 td->dvco_rate_min = dev_pm_opp_get_freq(opp); 1667 1668 dev_pm_opp_put(opp); 1669 1670 for (;;) { 1671 v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j)); 1672 if (v >= v_opp) 1673 break; 1674 1675 selector = find_vdd_map_entry_min(td, v); 1676 if (selector < 0) 1677 goto out; 1678 if (selector != td->lut[j - 1]) 1679 td->lut[j++] = selector; 1680 } 1681 1682 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp; 1683 selector = find_vdd_map_entry_exact(td, v); 1684 if (selector < 0) 1685 goto out; 1686 if (selector != td->lut[j - 1]) 1687 td->lut[j++] = selector; 1688 1689 if (v >= v_max) 1690 break; 1691 } 1692 td->lut_size = j; 1693 1694 if (!td->dvco_rate_min) 1695 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", 1696 td->soc->cvb->min_millivolts); 1697 else { 1698 ret = 0; 1699 for (j = 0; j < td->lut_size; j++) 1700 td->lut_uv[j] = 1701 regulator_list_voltage(td->vdd_reg, 1702 td->lut[j]); 1703 } 1704 1705 out: 1706 return ret; 1707 } 1708 1709 static int dfll_build_lut(struct tegra_dfll *td) 1710 { 1711 unsigned long rate, v_max; 1712 struct dev_pm_opp *opp; 1713 1714 rate = ULONG_MAX; 1715 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); 1716 if (IS_ERR(opp)) { 1717 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); 1718 return -EINVAL; 1719 } 1720 v_max = dev_pm_opp_get_voltage(opp); 1721 dev_pm_opp_put(opp); 1722 1723 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) 1724 return dfll_build_pwm_lut(td, v_max); 1725 else 1726 return dfll_build_i2c_lut(td, v_max); 1727 } 1728 1729 /** 1730 * read_dt_param - helper function for reading required parameters from the DT 1731 * @td: DFLL instance 1732 * @param: DT property name 1733 * @dest: output pointer for the value read 1734 * 1735 * Read a required numeric parameter from the DFLL device node, or complain 1736 * if the property doesn't exist. Returns a boolean indicating success for 1737 * easy chaining of multiple calls to this function. 1738 */ 1739 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest) 1740 { 1741 int err = of_property_read_u32(td->dev->of_node, param, dest); 1742 1743 if (err < 0) { 1744 dev_err(td->dev, "failed to read DT parameter %s: %d\n", 1745 param, err); 1746 return false; 1747 } 1748 1749 return true; 1750 } 1751 1752 /** 1753 * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem 1754 * @td: DFLL instance 1755 * 1756 * Read all the parameters required for operation in I2C mode. The parameters 1757 * can originate from the device tree or the regulator subsystem. 1758 * Returns 0 on success or -err on failure. 1759 */ 1760 static int dfll_fetch_i2c_params(struct tegra_dfll *td) 1761 { 1762 struct regmap *regmap; 1763 struct device *i2c_dev; 1764 struct i2c_client *i2c_client; 1765 int vsel_reg, vsel_mask; 1766 int ret; 1767 1768 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate)) 1769 return -EINVAL; 1770 1771 regmap = regulator_get_regmap(td->vdd_reg); 1772 i2c_dev = regmap_get_device(regmap); 1773 i2c_client = to_i2c_client(i2c_dev); 1774 1775 td->i2c_slave_addr = i2c_client->addr; 1776 1777 ret = regulator_get_hardware_vsel_register(td->vdd_reg, 1778 &vsel_reg, 1779 &vsel_mask); 1780 if (ret < 0) { 1781 dev_err(td->dev, 1782 "regulator unsuitable for DFLL I2C operation\n"); 1783 return -EINVAL; 1784 } 1785 td->i2c_reg = vsel_reg; 1786 1787 return 0; 1788 } 1789 1790 static int dfll_fetch_pwm_params(struct tegra_dfll *td) 1791 { 1792 int ret, i; 1793 u32 pwm_period; 1794 1795 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) { 1796 dev_err(td->dev, 1797 "Missing step or alignment info for PWM regulator"); 1798 return -EINVAL; 1799 } 1800 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) 1801 td->lut_uv[i] = td->soc->alignment.offset_uv + 1802 i * td->soc->alignment.step_uv; 1803 1804 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts", 1805 &td->reg_init_uV); 1806 if (!ret) { 1807 dev_err(td->dev, "couldn't get initialized voltage\n"); 1808 return ret; 1809 } 1810 1811 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period); 1812 if (!ret) { 1813 dev_err(td->dev, "couldn't get PWM period\n"); 1814 return ret; 1815 } 1816 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1); 1817 1818 td->pwm_pin = devm_pinctrl_get(td->dev); 1819 if (IS_ERR(td->pwm_pin)) { 1820 dev_err(td->dev, "DT: missing pinctrl device\n"); 1821 return PTR_ERR(td->pwm_pin); 1822 } 1823 1824 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin, 1825 "dvfs_pwm_enable"); 1826 if (IS_ERR(td->pwm_enable_state)) { 1827 dev_err(td->dev, "DT: missing pwm enabled state\n"); 1828 return PTR_ERR(td->pwm_enable_state); 1829 } 1830 1831 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin, 1832 "dvfs_pwm_disable"); 1833 if (IS_ERR(td->pwm_disable_state)) { 1834 dev_err(td->dev, "DT: missing pwm disabled state\n"); 1835 return PTR_ERR(td->pwm_disable_state); 1836 } 1837 1838 return 0; 1839 } 1840 1841 /** 1842 * dfll_fetch_common_params - read DFLL parameters from the device tree 1843 * @td: DFLL instance 1844 * 1845 * Read all the DT parameters that are common to both I2C and PWM operation. 1846 * Returns 0 on success or -EINVAL on any failure. 1847 */ 1848 static int dfll_fetch_common_params(struct tegra_dfll *td) 1849 { 1850 bool ok = true; 1851 1852 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl); 1853 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate); 1854 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode); 1855 ok &= read_dt_param(td, "nvidia,cf", &td->cf); 1856 ok &= read_dt_param(td, "nvidia,ci", &td->ci); 1857 ok &= read_dt_param(td, "nvidia,cg", &td->cg); 1858 td->cg_scale = of_property_read_bool(td->dev->of_node, 1859 "nvidia,cg-scale"); 1860 1861 if (of_property_read_string(td->dev->of_node, "clock-output-names", 1862 &td->output_clock_name)) { 1863 dev_err(td->dev, "missing clock-output-names property\n"); 1864 ok = false; 1865 } 1866 1867 return ok ? 0 : -EINVAL; 1868 } 1869 1870 /* 1871 * API exported to per-SoC platform drivers 1872 */ 1873 1874 /** 1875 * tegra_dfll_register - probe a Tegra DFLL device 1876 * @pdev: DFLL platform_device * 1877 * @soc: Per-SoC integration and characterization data for this DFLL instance 1878 * 1879 * Probe and initialize a DFLL device instance. Intended to be called 1880 * by a SoC-specific shim driver that passes in per-SoC integration 1881 * and configuration data via @soc. Returns 0 on success or -err on failure. 1882 */ 1883 int tegra_dfll_register(struct platform_device *pdev, 1884 struct tegra_dfll_soc_data *soc) 1885 { 1886 struct resource *mem; 1887 struct tegra_dfll *td; 1888 int ret; 1889 1890 if (!soc) { 1891 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n"); 1892 return -EINVAL; 1893 } 1894 1895 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL); 1896 if (!td) 1897 return -ENOMEM; 1898 td->dev = &pdev->dev; 1899 platform_set_drvdata(pdev, td); 1900 1901 td->soc = soc; 1902 1903 td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); 1904 if (IS_ERR(td->dvco_rst)) { 1905 dev_err(td->dev, "couldn't get dvco reset\n"); 1906 return PTR_ERR(td->dvco_rst); 1907 } 1908 1909 ret = dfll_fetch_common_params(td); 1910 if (ret) { 1911 dev_err(td->dev, "couldn't parse device tree parameters\n"); 1912 return ret; 1913 } 1914 1915 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) { 1916 td->pmu_if = TEGRA_DFLL_PMU_PWM; 1917 ret = dfll_fetch_pwm_params(td); 1918 } else { 1919 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); 1920 if (IS_ERR(td->vdd_reg)) { 1921 dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); 1922 return PTR_ERR(td->vdd_reg); 1923 } 1924 td->pmu_if = TEGRA_DFLL_PMU_I2C; 1925 ret = dfll_fetch_i2c_params(td); 1926 } 1927 if (ret) 1928 return ret; 1929 1930 ret = dfll_build_lut(td); 1931 if (ret) { 1932 dev_err(td->dev, "couldn't build LUT\n"); 1933 return ret; 1934 } 1935 1936 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1937 if (!mem) { 1938 dev_err(td->dev, "no control register resource\n"); 1939 return -ENODEV; 1940 } 1941 1942 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); 1943 if (!td->base) { 1944 dev_err(td->dev, "couldn't ioremap DFLL control registers\n"); 1945 return -ENODEV; 1946 } 1947 1948 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1949 if (!mem) { 1950 dev_err(td->dev, "no i2c_base resource\n"); 1951 return -ENODEV; 1952 } 1953 1954 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); 1955 if (!td->i2c_base) { 1956 dev_err(td->dev, "couldn't ioremap i2c_base resource\n"); 1957 return -ENODEV; 1958 } 1959 1960 mem = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1961 if (!mem) { 1962 dev_err(td->dev, "no i2c_controller_base resource\n"); 1963 return -ENODEV; 1964 } 1965 1966 td->i2c_controller_base = devm_ioremap(td->dev, mem->start, 1967 resource_size(mem)); 1968 if (!td->i2c_controller_base) { 1969 dev_err(td->dev, 1970 "couldn't ioremap i2c_controller_base resource\n"); 1971 return -ENODEV; 1972 } 1973 1974 mem = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1975 if (!mem) { 1976 dev_err(td->dev, "no lut_base resource\n"); 1977 return -ENODEV; 1978 } 1979 1980 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); 1981 if (!td->lut_base) { 1982 dev_err(td->dev, 1983 "couldn't ioremap lut_base resource\n"); 1984 return -ENODEV; 1985 } 1986 1987 ret = dfll_init_clks(td); 1988 if (ret) { 1989 dev_err(&pdev->dev, "DFLL clock init error\n"); 1990 return ret; 1991 } 1992 1993 /* Enable the clocks and set the device up */ 1994 ret = dfll_init(td); 1995 if (ret) 1996 return ret; 1997 1998 ret = dfll_register_clk(td); 1999 if (ret) { 2000 dev_err(&pdev->dev, "DFLL clk registration failed\n"); 2001 return ret; 2002 } 2003 2004 dfll_debug_init(td); 2005 2006 return 0; 2007 } 2008 EXPORT_SYMBOL(tegra_dfll_register); 2009 2010 /** 2011 * tegra_dfll_unregister - release all of the DFLL driver resources for a device 2012 * @pdev: DFLL platform_device * 2013 * 2014 * Unbind this driver from the DFLL hardware device represented by 2015 * @pdev. The DFLL must be disabled for this to succeed. Returns a 2016 * soc pointer upon success or -EBUSY if the DFLL is still active. 2017 */ 2018 struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev) 2019 { 2020 struct tegra_dfll *td = platform_get_drvdata(pdev); 2021 2022 /* Try to prevent removal while the DFLL is active */ 2023 if (td->mode != DFLL_DISABLED) { 2024 dev_err(&pdev->dev, 2025 "must disable DFLL before removing driver\n"); 2026 return ERR_PTR(-EBUSY); 2027 } 2028 2029 debugfs_remove_recursive(td->debugfs_dir); 2030 2031 dfll_unregister_clk(td); 2032 pm_runtime_disable(&pdev->dev); 2033 2034 clk_unprepare(td->ref_clk); 2035 clk_unprepare(td->soc_clk); 2036 clk_unprepare(td->i2c_clk); 2037 2038 reset_control_assert(td->dvco_rst); 2039 2040 return td->soc; 2041 } 2042 EXPORT_SYMBOL(tegra_dfll_unregister); 2043