xref: /openbmc/linux/drivers/clk/sunxi/clk-sunxi.c (revision 6aa7de05)
1 /*
2  * Copyright 2013 Emilio López
3  *
4  * Emilio López <emilio@elopez.com.ar>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/reset-controller.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/log2.h>
26 
27 #include "clk-factors.h"
28 
29 static DEFINE_SPINLOCK(clk_lock);
30 
31 /* Maximum number of parents our clocks have */
32 #define SUNXI_MAX_PARENTS	5
33 
34 /**
35  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
36  * PLL1 rate is calculated as follows
37  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38  * parent_rate is always 24Mhz
39  */
40 
41 static void sun4i_get_pll1_factors(struct factors_request *req)
42 {
43 	u8 div;
44 
45 	/* Normalize value to a 6M multiple */
46 	div = req->rate / 6000000;
47 	req->rate = 6000000 * div;
48 
49 	/* m is always zero for pll1 */
50 	req->m = 0;
51 
52 	/* k is 1 only on these cases */
53 	if (req->rate >= 768000000 || req->rate == 42000000 ||
54 			req->rate == 54000000)
55 		req->k = 1;
56 	else
57 		req->k = 0;
58 
59 	/* p will be 3 for divs under 10 */
60 	if (div < 10)
61 		req->p = 3;
62 
63 	/* p will be 2 for divs between 10 - 20 and odd divs under 32 */
64 	else if (div < 20 || (div < 32 && (div & 1)))
65 		req->p = 2;
66 
67 	/* p will be 1 for even divs under 32, divs under 40 and odd pairs
68 	 * of divs between 40-62 */
69 	else if (div < 40 || (div < 64 && (div & 2)))
70 		req->p = 1;
71 
72 	/* any other entries have p = 0 */
73 	else
74 		req->p = 0;
75 
76 	/* calculate a suitable n based on k and p */
77 	div <<= req->p;
78 	div /= (req->k + 1);
79 	req->n = div / 4;
80 }
81 
82 /**
83  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
84  * PLL1 rate is calculated as follows
85  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
86  * parent_rate should always be 24MHz
87  */
88 static void sun6i_a31_get_pll1_factors(struct factors_request *req)
89 {
90 	/*
91 	 * We can operate only on MHz, this will make our life easier
92 	 * later.
93 	 */
94 	u32 freq_mhz = req->rate / 1000000;
95 	u32 parent_freq_mhz = req->parent_rate / 1000000;
96 
97 	/*
98 	 * Round down the frequency to the closest multiple of either
99 	 * 6 or 16
100 	 */
101 	u32 round_freq_6 = round_down(freq_mhz, 6);
102 	u32 round_freq_16 = round_down(freq_mhz, 16);
103 
104 	if (round_freq_6 > round_freq_16)
105 		freq_mhz = round_freq_6;
106 	else
107 		freq_mhz = round_freq_16;
108 
109 	req->rate = freq_mhz * 1000000;
110 
111 	/* If the frequency is a multiple of 32 MHz, k is always 3 */
112 	if (!(freq_mhz % 32))
113 		req->k = 3;
114 	/* If the frequency is a multiple of 9 MHz, k is always 2 */
115 	else if (!(freq_mhz % 9))
116 		req->k = 2;
117 	/* If the frequency is a multiple of 8 MHz, k is always 1 */
118 	else if (!(freq_mhz % 8))
119 		req->k = 1;
120 	/* Otherwise, we don't use the k factor */
121 	else
122 		req->k = 0;
123 
124 	/*
125 	 * If the frequency is a multiple of 2 but not a multiple of
126 	 * 3, m is 3. This is the first time we use 6 here, yet we
127 	 * will use it on several other places.
128 	 * We use this number because it's the lowest frequency we can
129 	 * generate (with n = 0, k = 0, m = 3), so every other frequency
130 	 * somehow relates to this frequency.
131 	 */
132 	if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
133 		req->m = 2;
134 	/*
135 	 * If the frequency is a multiple of 6MHz, but the factor is
136 	 * odd, m will be 3
137 	 */
138 	else if ((freq_mhz / 6) & 1)
139 		req->m = 3;
140 	/* Otherwise, we end up with m = 1 */
141 	else
142 		req->m = 1;
143 
144 	/* Calculate n thanks to the above factors we already got */
145 	req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
146 		 - 1;
147 
148 	/*
149 	 * If n end up being outbound, and that we can still decrease
150 	 * m, do it.
151 	 */
152 	if ((req->n + 1) > 31 && (req->m + 1) > 1) {
153 		req->n = (req->n + 1) / 2 - 1;
154 		req->m = (req->m + 1) / 2 - 1;
155 	}
156 }
157 
158 /**
159  * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
160  * PLL1 rate is calculated as follows
161  * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
162  * parent_rate is always 24Mhz
163  */
164 
165 static void sun8i_a23_get_pll1_factors(struct factors_request *req)
166 {
167 	u8 div;
168 
169 	/* Normalize value to a 6M multiple */
170 	div = req->rate / 6000000;
171 	req->rate = 6000000 * div;
172 
173 	/* m is always zero for pll1 */
174 	req->m = 0;
175 
176 	/* k is 1 only on these cases */
177 	if (req->rate >= 768000000 || req->rate == 42000000 ||
178 			req->rate == 54000000)
179 		req->k = 1;
180 	else
181 		req->k = 0;
182 
183 	/* p will be 2 for divs under 20 and odd divs under 32 */
184 	if (div < 20 || (div < 32 && (div & 1)))
185 		req->p = 2;
186 
187 	/* p will be 1 for even divs under 32, divs under 40 and odd pairs
188 	 * of divs between 40-62 */
189 	else if (div < 40 || (div < 64 && (div & 2)))
190 		req->p = 1;
191 
192 	/* any other entries have p = 0 */
193 	else
194 		req->p = 0;
195 
196 	/* calculate a suitable n based on k and p */
197 	div <<= req->p;
198 	div /= (req->k + 1);
199 	req->n = div / 4 - 1;
200 }
201 
202 /**
203  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
204  * PLL5 rate is calculated as follows
205  * rate = parent_rate * n * (k + 1)
206  * parent_rate is always 24Mhz
207  */
208 
209 static void sun4i_get_pll5_factors(struct factors_request *req)
210 {
211 	u8 div;
212 
213 	/* Normalize value to a parent_rate multiple (24M) */
214 	div = req->rate / req->parent_rate;
215 	req->rate = req->parent_rate * div;
216 
217 	if (div < 31)
218 		req->k = 0;
219 	else if (div / 2 < 31)
220 		req->k = 1;
221 	else if (div / 3 < 31)
222 		req->k = 2;
223 	else
224 		req->k = 3;
225 
226 	req->n = DIV_ROUND_UP(div, (req->k + 1));
227 }
228 
229 /**
230  * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
231  * PLL6x2 rate is calculated as follows
232  * rate = parent_rate * (n + 1) * (k + 1)
233  * parent_rate is always 24Mhz
234  */
235 
236 static void sun6i_a31_get_pll6_factors(struct factors_request *req)
237 {
238 	u8 div;
239 
240 	/* Normalize value to a parent_rate multiple (24M) */
241 	div = req->rate / req->parent_rate;
242 	req->rate = req->parent_rate * div;
243 
244 	req->k = div / 32;
245 	if (req->k > 3)
246 		req->k = 3;
247 
248 	req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
249 }
250 
251 /**
252  * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
253  * AHB rate is calculated as follows
254  * rate = parent_rate >> p
255  */
256 
257 static void sun5i_a13_get_ahb_factors(struct factors_request *req)
258 {
259 	u32 div;
260 
261 	/* divide only */
262 	if (req->parent_rate < req->rate)
263 		req->rate = req->parent_rate;
264 
265 	/*
266 	 * user manual says valid speed is 8k ~ 276M, but tests show it
267 	 * can work at speeds up to 300M, just after reparenting to pll6
268 	 */
269 	if (req->rate < 8000)
270 		req->rate = 8000;
271 	if (req->rate > 300000000)
272 		req->rate = 300000000;
273 
274 	div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
275 
276 	/* p = 0 ~ 3 */
277 	if (div > 3)
278 		div = 3;
279 
280 	req->rate = req->parent_rate >> div;
281 
282 	req->p = div;
283 }
284 
285 #define SUN6I_AHB1_PARENT_PLL6	3
286 
287 /**
288  * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
289  * AHB rate is calculated as follows
290  * rate = parent_rate >> p
291  *
292  * if parent is pll6, then
293  * parent_rate = pll6 rate / (m + 1)
294  */
295 
296 static void sun6i_get_ahb1_factors(struct factors_request *req)
297 {
298 	u8 div, calcp, calcm = 1;
299 
300 	/*
301 	 * clock can only divide, so we will never be able to achieve
302 	 * frequencies higher than the parent frequency
303 	 */
304 	if (req->parent_rate && req->rate > req->parent_rate)
305 		req->rate = req->parent_rate;
306 
307 	div = DIV_ROUND_UP(req->parent_rate, req->rate);
308 
309 	/* calculate pre-divider if parent is pll6 */
310 	if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
311 		if (div < 4)
312 			calcp = 0;
313 		else if (div / 2 < 4)
314 			calcp = 1;
315 		else if (div / 4 < 4)
316 			calcp = 2;
317 		else
318 			calcp = 3;
319 
320 		calcm = DIV_ROUND_UP(div, 1 << calcp);
321 	} else {
322 		calcp = __roundup_pow_of_two(div);
323 		calcp = calcp > 3 ? 3 : calcp;
324 	}
325 
326 	req->rate = (req->parent_rate / calcm) >> calcp;
327 	req->p = calcp;
328 	req->m = calcm - 1;
329 }
330 
331 /**
332  * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
333  *			 parent index
334  */
335 static void sun6i_ahb1_recalc(struct factors_request *req)
336 {
337 	req->rate = req->parent_rate;
338 
339 	/* apply pre-divider first if parent is pll6 */
340 	if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
341 		req->rate /= req->m + 1;
342 
343 	/* clk divider */
344 	req->rate >>= req->p;
345 }
346 
347 /**
348  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
349  * APB1 rate is calculated as follows
350  * rate = (parent_rate >> p) / (m + 1);
351  */
352 
353 static void sun4i_get_apb1_factors(struct factors_request *req)
354 {
355 	u8 calcm, calcp;
356 	int div;
357 
358 	if (req->parent_rate < req->rate)
359 		req->rate = req->parent_rate;
360 
361 	div = DIV_ROUND_UP(req->parent_rate, req->rate);
362 
363 	/* Invalid rate! */
364 	if (div > 32)
365 		return;
366 
367 	if (div <= 4)
368 		calcp = 0;
369 	else if (div <= 8)
370 		calcp = 1;
371 	else if (div <= 16)
372 		calcp = 2;
373 	else
374 		calcp = 3;
375 
376 	calcm = (div >> calcp) - 1;
377 
378 	req->rate = (req->parent_rate >> calcp) / (calcm + 1);
379 	req->m = calcm;
380 	req->p = calcp;
381 }
382 
383 
384 
385 
386 /**
387  * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
388  * CLK_OUT rate is calculated as follows
389  * rate = (parent_rate >> p) / (m + 1);
390  */
391 
392 static void sun7i_a20_get_out_factors(struct factors_request *req)
393 {
394 	u8 div, calcm, calcp;
395 
396 	/* These clocks can only divide, so we will never be able to achieve
397 	 * frequencies higher than the parent frequency */
398 	if (req->rate > req->parent_rate)
399 		req->rate = req->parent_rate;
400 
401 	div = DIV_ROUND_UP(req->parent_rate, req->rate);
402 
403 	if (div < 32)
404 		calcp = 0;
405 	else if (div / 2 < 32)
406 		calcp = 1;
407 	else if (div / 4 < 32)
408 		calcp = 2;
409 	else
410 		calcp = 3;
411 
412 	calcm = DIV_ROUND_UP(div, 1 << calcp);
413 
414 	req->rate = (req->parent_rate >> calcp) / calcm;
415 	req->m = calcm - 1;
416 	req->p = calcp;
417 }
418 
419 /**
420  * sunxi_factors_clk_setup() - Setup function for factor clocks
421  */
422 
423 static const struct clk_factors_config sun4i_pll1_config = {
424 	.nshift = 8,
425 	.nwidth = 5,
426 	.kshift = 4,
427 	.kwidth = 2,
428 	.mshift = 0,
429 	.mwidth = 2,
430 	.pshift = 16,
431 	.pwidth = 2,
432 };
433 
434 static const struct clk_factors_config sun6i_a31_pll1_config = {
435 	.nshift	= 8,
436 	.nwidth = 5,
437 	.kshift = 4,
438 	.kwidth = 2,
439 	.mshift = 0,
440 	.mwidth = 2,
441 	.n_start = 1,
442 };
443 
444 static const struct clk_factors_config sun8i_a23_pll1_config = {
445 	.nshift = 8,
446 	.nwidth = 5,
447 	.kshift = 4,
448 	.kwidth = 2,
449 	.mshift = 0,
450 	.mwidth = 2,
451 	.pshift = 16,
452 	.pwidth = 2,
453 	.n_start = 1,
454 };
455 
456 static const struct clk_factors_config sun4i_pll5_config = {
457 	.nshift = 8,
458 	.nwidth = 5,
459 	.kshift = 4,
460 	.kwidth = 2,
461 };
462 
463 static const struct clk_factors_config sun6i_a31_pll6_config = {
464 	.nshift	= 8,
465 	.nwidth = 5,
466 	.kshift = 4,
467 	.kwidth = 2,
468 	.n_start = 1,
469 };
470 
471 static const struct clk_factors_config sun5i_a13_ahb_config = {
472 	.pshift = 4,
473 	.pwidth = 2,
474 };
475 
476 static const struct clk_factors_config sun6i_ahb1_config = {
477 	.mshift = 6,
478 	.mwidth = 2,
479 	.pshift = 4,
480 	.pwidth = 2,
481 };
482 
483 static const struct clk_factors_config sun4i_apb1_config = {
484 	.mshift = 0,
485 	.mwidth = 5,
486 	.pshift = 16,
487 	.pwidth = 2,
488 };
489 
490 /* user manual says "n" but it's really "p" */
491 static const struct clk_factors_config sun7i_a20_out_config = {
492 	.mshift = 8,
493 	.mwidth = 5,
494 	.pshift = 20,
495 	.pwidth = 2,
496 };
497 
498 static const struct factors_data sun4i_pll1_data __initconst = {
499 	.enable = 31,
500 	.table = &sun4i_pll1_config,
501 	.getter = sun4i_get_pll1_factors,
502 };
503 
504 static const struct factors_data sun6i_a31_pll1_data __initconst = {
505 	.enable = 31,
506 	.table = &sun6i_a31_pll1_config,
507 	.getter = sun6i_a31_get_pll1_factors,
508 };
509 
510 static const struct factors_data sun8i_a23_pll1_data __initconst = {
511 	.enable = 31,
512 	.table = &sun8i_a23_pll1_config,
513 	.getter = sun8i_a23_get_pll1_factors,
514 };
515 
516 static const struct factors_data sun7i_a20_pll4_data __initconst = {
517 	.enable = 31,
518 	.table = &sun4i_pll5_config,
519 	.getter = sun4i_get_pll5_factors,
520 };
521 
522 static const struct factors_data sun4i_pll5_data __initconst = {
523 	.enable = 31,
524 	.table = &sun4i_pll5_config,
525 	.getter = sun4i_get_pll5_factors,
526 };
527 
528 static const struct factors_data sun6i_a31_pll6_data __initconst = {
529 	.enable = 31,
530 	.table = &sun6i_a31_pll6_config,
531 	.getter = sun6i_a31_get_pll6_factors,
532 };
533 
534 static const struct factors_data sun5i_a13_ahb_data __initconst = {
535 	.mux = 6,
536 	.muxmask = BIT(1) | BIT(0),
537 	.table = &sun5i_a13_ahb_config,
538 	.getter = sun5i_a13_get_ahb_factors,
539 };
540 
541 static const struct factors_data sun6i_ahb1_data __initconst = {
542 	.mux = 12,
543 	.muxmask = BIT(1) | BIT(0),
544 	.table = &sun6i_ahb1_config,
545 	.getter = sun6i_get_ahb1_factors,
546 	.recalc = sun6i_ahb1_recalc,
547 };
548 
549 static const struct factors_data sun4i_apb1_data __initconst = {
550 	.mux = 24,
551 	.muxmask = BIT(1) | BIT(0),
552 	.table = &sun4i_apb1_config,
553 	.getter = sun4i_get_apb1_factors,
554 };
555 
556 static const struct factors_data sun7i_a20_out_data __initconst = {
557 	.enable = 31,
558 	.mux = 24,
559 	.muxmask = BIT(1) | BIT(0),
560 	.table = &sun7i_a20_out_config,
561 	.getter = sun7i_a20_get_out_factors,
562 };
563 
564 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
565 						   const struct factors_data *data)
566 {
567 	void __iomem *reg;
568 
569 	reg = of_iomap(node, 0);
570 	if (!reg) {
571 		pr_err("Could not get registers for factors-clk: %s\n",
572 		       node->name);
573 		return NULL;
574 	}
575 
576 	return sunxi_factors_register(node, data, &clk_lock, reg);
577 }
578 
579 static void __init sun4i_pll1_clk_setup(struct device_node *node)
580 {
581 	sunxi_factors_clk_setup(node, &sun4i_pll1_data);
582 }
583 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
584 	       sun4i_pll1_clk_setup);
585 
586 static void __init sun6i_pll1_clk_setup(struct device_node *node)
587 {
588 	sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
589 }
590 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
591 	       sun6i_pll1_clk_setup);
592 
593 static void __init sun8i_pll1_clk_setup(struct device_node *node)
594 {
595 	sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
596 }
597 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
598 	       sun8i_pll1_clk_setup);
599 
600 static void __init sun7i_pll4_clk_setup(struct device_node *node)
601 {
602 	sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
603 }
604 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
605 	       sun7i_pll4_clk_setup);
606 
607 static void __init sun5i_ahb_clk_setup(struct device_node *node)
608 {
609 	sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
610 }
611 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
612 	       sun5i_ahb_clk_setup);
613 
614 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
615 {
616 	sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
617 }
618 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
619 	       sun6i_ahb1_clk_setup);
620 
621 static void __init sun4i_apb1_clk_setup(struct device_node *node)
622 {
623 	sunxi_factors_clk_setup(node, &sun4i_apb1_data);
624 }
625 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
626 	       sun4i_apb1_clk_setup);
627 
628 static void __init sun7i_out_clk_setup(struct device_node *node)
629 {
630 	sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
631 }
632 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
633 	       sun7i_out_clk_setup);
634 
635 
636 /**
637  * sunxi_mux_clk_setup() - Setup function for muxes
638  */
639 
640 #define SUNXI_MUX_GATE_WIDTH	2
641 
642 struct mux_data {
643 	u8 shift;
644 };
645 
646 static const struct mux_data sun4i_cpu_mux_data __initconst = {
647 	.shift = 16,
648 };
649 
650 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
651 	.shift = 12,
652 };
653 
654 static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
655 	.shift = 0,
656 };
657 
658 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
659 					       const struct mux_data *data)
660 {
661 	struct clk *clk;
662 	const char *clk_name = node->name;
663 	const char *parents[SUNXI_MAX_PARENTS];
664 	void __iomem *reg;
665 	int i;
666 
667 	reg = of_iomap(node, 0);
668 	if (!reg) {
669 		pr_err("Could not map registers for mux-clk: %pOF\n", node);
670 		return NULL;
671 	}
672 
673 	i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
674 	if (of_property_read_string(node, "clock-output-names", &clk_name)) {
675 		pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
676 		       __func__, node);
677 		goto out_unmap;
678 	}
679 
680 	clk = clk_register_mux(NULL, clk_name, parents, i,
681 			       CLK_SET_RATE_PARENT, reg,
682 			       data->shift, SUNXI_MUX_GATE_WIDTH,
683 			       0, &clk_lock);
684 
685 	if (IS_ERR(clk)) {
686 		pr_err("%s: failed to register mux clock %s: %ld\n", __func__,
687 		       clk_name, PTR_ERR(clk));
688 		goto out_unmap;
689 	}
690 
691 	if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
692 		pr_err("%s: failed to add clock provider for %s\n",
693 		       __func__, clk_name);
694 		clk_unregister_divider(clk);
695 		goto out_unmap;
696 	}
697 
698 	return clk;
699 out_unmap:
700 	iounmap(reg);
701 	return NULL;
702 }
703 
704 static void __init sun4i_cpu_clk_setup(struct device_node *node)
705 {
706 	struct clk *clk;
707 
708 	clk = sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data);
709 	if (!clk)
710 		return;
711 
712 	/* Protect CPU clock */
713 	__clk_get(clk);
714 	clk_prepare_enable(clk);
715 }
716 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
717 	       sun4i_cpu_clk_setup);
718 
719 static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
720 {
721 	sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data);
722 }
723 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
724 	       sun6i_ahb1_mux_clk_setup);
725 
726 static void __init sun8i_ahb2_clk_setup(struct device_node *node)
727 {
728 	sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data);
729 }
730 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
731 	       sun8i_ahb2_clk_setup);
732 
733 
734 /**
735  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
736  */
737 
738 struct div_data {
739 	u8	shift;
740 	u8	pow;
741 	u8	width;
742 	const struct clk_div_table *table;
743 };
744 
745 static const struct div_data sun4i_axi_data __initconst = {
746 	.shift	= 0,
747 	.pow	= 0,
748 	.width	= 2,
749 };
750 
751 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
752 	{ .val = 0, .div = 1 },
753 	{ .val = 1, .div = 2 },
754 	{ .val = 2, .div = 3 },
755 	{ .val = 3, .div = 4 },
756 	{ .val = 4, .div = 4 },
757 	{ .val = 5, .div = 4 },
758 	{ .val = 6, .div = 4 },
759 	{ .val = 7, .div = 4 },
760 	{ } /* sentinel */
761 };
762 
763 static const struct div_data sun8i_a23_axi_data __initconst = {
764 	.width	= 3,
765 	.table	= sun8i_a23_axi_table,
766 };
767 
768 static const struct div_data sun4i_ahb_data __initconst = {
769 	.shift	= 4,
770 	.pow	= 1,
771 	.width	= 2,
772 };
773 
774 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
775 	{ .val = 0, .div = 2 },
776 	{ .val = 1, .div = 2 },
777 	{ .val = 2, .div = 4 },
778 	{ .val = 3, .div = 8 },
779 	{ } /* sentinel */
780 };
781 
782 static const struct div_data sun4i_apb0_data __initconst = {
783 	.shift	= 8,
784 	.pow	= 1,
785 	.width	= 2,
786 	.table	= sun4i_apb0_table,
787 };
788 
789 static void __init sunxi_divider_clk_setup(struct device_node *node,
790 					   const struct div_data *data)
791 {
792 	struct clk *clk;
793 	const char *clk_name = node->name;
794 	const char *clk_parent;
795 	void __iomem *reg;
796 
797 	reg = of_iomap(node, 0);
798 	if (!reg) {
799 		pr_err("Could not map registers for mux-clk: %pOF\n", node);
800 		return;
801 	}
802 
803 	clk_parent = of_clk_get_parent_name(node, 0);
804 
805 	if (of_property_read_string(node, "clock-output-names", &clk_name)) {
806 		pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
807 		       __func__, node);
808 		goto out_unmap;
809 	}
810 
811 	clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
812 					 reg, data->shift, data->width,
813 					 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
814 					 data->table, &clk_lock);
815 	if (IS_ERR(clk)) {
816 		pr_err("%s: failed to register divider clock %s: %ld\n",
817 		       __func__, clk_name, PTR_ERR(clk));
818 		goto out_unmap;
819 	}
820 
821 	if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
822 		pr_err("%s: failed to add clock provider for %s\n",
823 		       __func__, clk_name);
824 		goto out_unregister;
825 	}
826 
827 	if (clk_register_clkdev(clk, clk_name, NULL)) {
828 		of_clk_del_provider(node);
829 		goto out_unregister;
830 	}
831 
832 	return;
833 out_unregister:
834 	clk_unregister_divider(clk);
835 
836 out_unmap:
837 	iounmap(reg);
838 }
839 
840 static void __init sun4i_ahb_clk_setup(struct device_node *node)
841 {
842 	sunxi_divider_clk_setup(node, &sun4i_ahb_data);
843 }
844 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
845 	       sun4i_ahb_clk_setup);
846 
847 static void __init sun4i_apb0_clk_setup(struct device_node *node)
848 {
849 	sunxi_divider_clk_setup(node, &sun4i_apb0_data);
850 }
851 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
852 	       sun4i_apb0_clk_setup);
853 
854 static void __init sun4i_axi_clk_setup(struct device_node *node)
855 {
856 	sunxi_divider_clk_setup(node, &sun4i_axi_data);
857 }
858 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
859 	       sun4i_axi_clk_setup);
860 
861 static void __init sun8i_axi_clk_setup(struct device_node *node)
862 {
863 	sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
864 }
865 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
866 	       sun8i_axi_clk_setup);
867 
868 
869 
870 /**
871  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
872  */
873 
874 #define SUNXI_GATES_MAX_SIZE	64
875 
876 struct gates_data {
877 	DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
878 };
879 
880 /**
881  * sunxi_divs_clk_setup() helper data
882  */
883 
884 #define SUNXI_DIVS_MAX_QTY	4
885 #define SUNXI_DIVISOR_WIDTH	2
886 
887 struct divs_data {
888 	const struct factors_data *factors; /* data for the factor clock */
889 	int ndivs; /* number of outputs */
890 	/*
891 	 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
892 	 * self or base factor clock refers to the output from the pll
893 	 * itself. The remaining refer to fixed or configurable divider
894 	 * outputs.
895 	 */
896 	struct {
897 		u8 self; /* is it the base factor clock? (only one) */
898 		u8 fixed; /* is it a fixed divisor? if not... */
899 		struct clk_div_table *table; /* is it a table based divisor? */
900 		u8 shift; /* otherwise it's a normal divisor with this shift */
901 		u8 pow;   /* is it power-of-two based? */
902 		u8 gate;  /* is it independently gateable? */
903 	} div[SUNXI_DIVS_MAX_QTY];
904 };
905 
906 static struct clk_div_table pll6_sata_tbl[] = {
907 	{ .val = 0, .div = 6, },
908 	{ .val = 1, .div = 12, },
909 	{ .val = 2, .div = 18, },
910 	{ .val = 3, .div = 24, },
911 	{ } /* sentinel */
912 };
913 
914 static const struct divs_data pll5_divs_data __initconst = {
915 	.factors = &sun4i_pll5_data,
916 	.ndivs = 2,
917 	.div = {
918 		{ .shift = 0, .pow = 0, }, /* M, DDR */
919 		{ .shift = 16, .pow = 1, }, /* P, other */
920 		/* No output for the base factor clock */
921 	}
922 };
923 
924 static const struct divs_data pll6_divs_data __initconst = {
925 	.factors = &sun4i_pll5_data,
926 	.ndivs = 4,
927 	.div = {
928 		{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
929 		{ .fixed = 2 }, /* P, other */
930 		{ .self = 1 }, /* base factor clock, 2x */
931 		{ .fixed = 4 }, /* pll6 / 4, used as ahb input */
932 	}
933 };
934 
935 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
936 	.factors = &sun6i_a31_pll6_data,
937 	.ndivs = 2,
938 	.div = {
939 		{ .fixed = 2 }, /* normal output */
940 		{ .self = 1 }, /* base factor clock, 2x */
941 	}
942 };
943 
944 /**
945  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
946  *
947  * These clocks look something like this
948  *            ________________________
949  *           |         ___divisor 1---|----> to consumer
950  * parent >--|  pll___/___divisor 2---|----> to consumer
951  *           |        \_______________|____> to consumer
952  *           |________________________|
953  */
954 
955 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
956 						 const struct divs_data *data)
957 {
958 	struct clk_onecell_data *clk_data;
959 	const char *parent;
960 	const char *clk_name;
961 	struct clk **clks, *pclk;
962 	struct clk_hw *gate_hw, *rate_hw;
963 	const struct clk_ops *rate_ops;
964 	struct clk_gate *gate = NULL;
965 	struct clk_fixed_factor *fix_factor;
966 	struct clk_divider *divider;
967 	struct factors_data factors = *data->factors;
968 	char *derived_name = NULL;
969 	void __iomem *reg;
970 	int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
971 	int flags, clkflags;
972 
973 	/* if number of children known, use it */
974 	if (data->ndivs)
975 		ndivs = data->ndivs;
976 
977 	/* Try to find a name for base factor clock */
978 	for (i = 0; i < ndivs; i++) {
979 		if (data->div[i].self) {
980 			of_property_read_string_index(node, "clock-output-names",
981 						      i, &factors.name);
982 			break;
983 		}
984 	}
985 	/* If we don't have a .self clk use the first output-name up to '_' */
986 	if (factors.name == NULL) {
987 		char *endp;
988 
989 		of_property_read_string_index(node, "clock-output-names",
990 						      0, &clk_name);
991 		endp = strchr(clk_name, '_');
992 		if (endp) {
993 			derived_name = kstrndup(clk_name, endp - clk_name,
994 						GFP_KERNEL);
995 			factors.name = derived_name;
996 		} else {
997 			factors.name = clk_name;
998 		}
999 	}
1000 
1001 	/* Set up factor clock that we will be dividing */
1002 	pclk = sunxi_factors_clk_setup(node, &factors);
1003 	if (!pclk)
1004 		return NULL;
1005 
1006 	parent = __clk_get_name(pclk);
1007 	kfree(derived_name);
1008 
1009 	reg = of_iomap(node, 0);
1010 	if (!reg) {
1011 		pr_err("Could not map registers for divs-clk: %pOF\n", node);
1012 		return NULL;
1013 	}
1014 
1015 	clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1016 	if (!clk_data)
1017 		goto out_unmap;
1018 
1019 	clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1020 	if (!clks)
1021 		goto free_clkdata;
1022 
1023 	clk_data->clks = clks;
1024 
1025 	/* It's not a good idea to have automatic reparenting changing
1026 	 * our RAM clock! */
1027 	clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1028 
1029 	for (i = 0; i < ndivs; i++) {
1030 		if (of_property_read_string_index(node, "clock-output-names",
1031 						  i, &clk_name) != 0)
1032 			break;
1033 
1034 		/* If this is the base factor clock, only update clks */
1035 		if (data->div[i].self) {
1036 			clk_data->clks[i] = pclk;
1037 			continue;
1038 		}
1039 
1040 		gate_hw = NULL;
1041 		rate_hw = NULL;
1042 		rate_ops = NULL;
1043 
1044 		/* If this leaf clock can be gated, create a gate */
1045 		if (data->div[i].gate) {
1046 			gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1047 			if (!gate)
1048 				goto free_clks;
1049 
1050 			gate->reg = reg;
1051 			gate->bit_idx = data->div[i].gate;
1052 			gate->lock = &clk_lock;
1053 
1054 			gate_hw = &gate->hw;
1055 		}
1056 
1057 		/* Leaves can be fixed or configurable divisors */
1058 		if (data->div[i].fixed) {
1059 			fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1060 			if (!fix_factor)
1061 				goto free_gate;
1062 
1063 			fix_factor->mult = 1;
1064 			fix_factor->div = data->div[i].fixed;
1065 
1066 			rate_hw = &fix_factor->hw;
1067 			rate_ops = &clk_fixed_factor_ops;
1068 		} else {
1069 			divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1070 			if (!divider)
1071 				goto free_gate;
1072 
1073 			flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1074 
1075 			divider->reg = reg;
1076 			divider->shift = data->div[i].shift;
1077 			divider->width = SUNXI_DIVISOR_WIDTH;
1078 			divider->flags = flags;
1079 			divider->lock = &clk_lock;
1080 			divider->table = data->div[i].table;
1081 
1082 			rate_hw = &divider->hw;
1083 			rate_ops = &clk_divider_ops;
1084 		}
1085 
1086 		/* Wrap the (potential) gate and the divisor on a composite
1087 		 * clock to unify them */
1088 		clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1089 						 NULL, NULL,
1090 						 rate_hw, rate_ops,
1091 						 gate_hw, &clk_gate_ops,
1092 						 clkflags);
1093 
1094 		WARN_ON(IS_ERR(clk_data->clks[i]));
1095 	}
1096 
1097 	/* Adjust to the real max */
1098 	clk_data->clk_num = i;
1099 
1100 	if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {
1101 		pr_err("%s: failed to add clock provider for %s\n",
1102 		       __func__, clk_name);
1103 		goto free_gate;
1104 	}
1105 
1106 	return clks;
1107 free_gate:
1108 	kfree(gate);
1109 free_clks:
1110 	kfree(clks);
1111 free_clkdata:
1112 	kfree(clk_data);
1113 out_unmap:
1114 	iounmap(reg);
1115 	return NULL;
1116 }
1117 
1118 static void __init sun4i_pll5_clk_setup(struct device_node *node)
1119 {
1120 	struct clk **clks;
1121 
1122 	clks = sunxi_divs_clk_setup(node, &pll5_divs_data);
1123 	if (!clks)
1124 		return;
1125 
1126 	/* Protect PLL5_DDR */
1127 	__clk_get(clks[0]);
1128 	clk_prepare_enable(clks[0]);
1129 }
1130 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1131 	       sun4i_pll5_clk_setup);
1132 
1133 static void __init sun4i_pll6_clk_setup(struct device_node *node)
1134 {
1135 	sunxi_divs_clk_setup(node, &pll6_divs_data);
1136 }
1137 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1138 	       sun4i_pll6_clk_setup);
1139 
1140 static void __init sun6i_pll6_clk_setup(struct device_node *node)
1141 {
1142 	sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);
1143 }
1144 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1145 	       sun6i_pll6_clk_setup);
1146 
1147 /*
1148  * sun6i display
1149  *
1150  * rate = parent_rate / (m + 1);
1151  */
1152 static void sun6i_display_factors(struct factors_request *req)
1153 {
1154 	u8 m;
1155 
1156 	if (req->rate > req->parent_rate)
1157 		req->rate = req->parent_rate;
1158 
1159 	m = DIV_ROUND_UP(req->parent_rate, req->rate);
1160 
1161 	req->rate = req->parent_rate / m;
1162 	req->m = m - 1;
1163 }
1164 
1165 static const struct clk_factors_config sun6i_display_config = {
1166 	.mshift = 0,
1167 	.mwidth = 4,
1168 };
1169 
1170 static const struct factors_data sun6i_display_data __initconst = {
1171 	.enable = 31,
1172 	.mux = 24,
1173 	.muxmask = BIT(2) | BIT(1) | BIT(0),
1174 	.table = &sun6i_display_config,
1175 	.getter = sun6i_display_factors,
1176 };
1177 
1178 static void __init sun6i_display_setup(struct device_node *node)
1179 {
1180 	sunxi_factors_clk_setup(node, &sun6i_display_data);
1181 }
1182 CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",
1183 	       sun6i_display_setup);
1184