1 /* 2 * Copyright 2013 Emilio López 3 * 4 * Emilio López <emilio@elopez.com.ar> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk-provider.h> 18 #include <linux/clkdev.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/reset-controller.h> 22 23 #include "clk-factors.h" 24 25 static DEFINE_SPINLOCK(clk_lock); 26 27 /* Maximum number of parents our clocks have */ 28 #define SUNXI_MAX_PARENTS 5 29 30 /** 31 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 32 * PLL1 rate is calculated as follows 33 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); 34 * parent_rate is always 24Mhz 35 */ 36 37 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, 38 u8 *n, u8 *k, u8 *m, u8 *p) 39 { 40 u8 div; 41 42 /* Normalize value to a 6M multiple */ 43 div = *freq / 6000000; 44 *freq = 6000000 * div; 45 46 /* we were called to round the frequency, we can now return */ 47 if (n == NULL) 48 return; 49 50 /* m is always zero for pll1 */ 51 *m = 0; 52 53 /* k is 1 only on these cases */ 54 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) 55 *k = 1; 56 else 57 *k = 0; 58 59 /* p will be 3 for divs under 10 */ 60 if (div < 10) 61 *p = 3; 62 63 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ 64 else if (div < 20 || (div < 32 && (div & 1))) 65 *p = 2; 66 67 /* p will be 1 for even divs under 32, divs under 40 and odd pairs 68 * of divs between 40-62 */ 69 else if (div < 40 || (div < 64 && (div & 2))) 70 *p = 1; 71 72 /* any other entries have p = 0 */ 73 else 74 *p = 0; 75 76 /* calculate a suitable n based on k and p */ 77 div <<= *p; 78 div /= (*k + 1); 79 *n = div / 4; 80 } 81 82 /** 83 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 84 * PLL1 rate is calculated as follows 85 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1); 86 * parent_rate should always be 24MHz 87 */ 88 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, 89 u8 *n, u8 *k, u8 *m, u8 *p) 90 { 91 /* 92 * We can operate only on MHz, this will make our life easier 93 * later. 94 */ 95 u32 freq_mhz = *freq / 1000000; 96 u32 parent_freq_mhz = parent_rate / 1000000; 97 98 /* 99 * Round down the frequency to the closest multiple of either 100 * 6 or 16 101 */ 102 u32 round_freq_6 = round_down(freq_mhz, 6); 103 u32 round_freq_16 = round_down(freq_mhz, 16); 104 105 if (round_freq_6 > round_freq_16) 106 freq_mhz = round_freq_6; 107 else 108 freq_mhz = round_freq_16; 109 110 *freq = freq_mhz * 1000000; 111 112 /* 113 * If the factors pointer are null, we were just called to 114 * round down the frequency. 115 * Exit. 116 */ 117 if (n == NULL) 118 return; 119 120 /* If the frequency is a multiple of 32 MHz, k is always 3 */ 121 if (!(freq_mhz % 32)) 122 *k = 3; 123 /* If the frequency is a multiple of 9 MHz, k is always 2 */ 124 else if (!(freq_mhz % 9)) 125 *k = 2; 126 /* If the frequency is a multiple of 8 MHz, k is always 1 */ 127 else if (!(freq_mhz % 8)) 128 *k = 1; 129 /* Otherwise, we don't use the k factor */ 130 else 131 *k = 0; 132 133 /* 134 * If the frequency is a multiple of 2 but not a multiple of 135 * 3, m is 3. This is the first time we use 6 here, yet we 136 * will use it on several other places. 137 * We use this number because it's the lowest frequency we can 138 * generate (with n = 0, k = 0, m = 3), so every other frequency 139 * somehow relates to this frequency. 140 */ 141 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) 142 *m = 2; 143 /* 144 * If the frequency is a multiple of 6MHz, but the factor is 145 * odd, m will be 3 146 */ 147 else if ((freq_mhz / 6) & 1) 148 *m = 3; 149 /* Otherwise, we end up with m = 1 */ 150 else 151 *m = 1; 152 153 /* Calculate n thanks to the above factors we already got */ 154 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1; 155 156 /* 157 * If n end up being outbound, and that we can still decrease 158 * m, do it. 159 */ 160 if ((*n + 1) > 31 && (*m + 1) > 1) { 161 *n = (*n + 1) / 2 - 1; 162 *m = (*m + 1) / 2 - 1; 163 } 164 } 165 166 /** 167 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1 168 * PLL1 rate is calculated as follows 169 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1); 170 * parent_rate is always 24Mhz 171 */ 172 173 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate, 174 u8 *n, u8 *k, u8 *m, u8 *p) 175 { 176 u8 div; 177 178 /* Normalize value to a 6M multiple */ 179 div = *freq / 6000000; 180 *freq = 6000000 * div; 181 182 /* we were called to round the frequency, we can now return */ 183 if (n == NULL) 184 return; 185 186 /* m is always zero for pll1 */ 187 *m = 0; 188 189 /* k is 1 only on these cases */ 190 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) 191 *k = 1; 192 else 193 *k = 0; 194 195 /* p will be 2 for divs under 20 and odd divs under 32 */ 196 if (div < 20 || (div < 32 && (div & 1))) 197 *p = 2; 198 199 /* p will be 1 for even divs under 32, divs under 40 and odd pairs 200 * of divs between 40-62 */ 201 else if (div < 40 || (div < 64 && (div & 2))) 202 *p = 1; 203 204 /* any other entries have p = 0 */ 205 else 206 *p = 0; 207 208 /* calculate a suitable n based on k and p */ 209 div <<= *p; 210 div /= (*k + 1); 211 *n = div / 4 - 1; 212 } 213 214 /** 215 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5 216 * PLL5 rate is calculated as follows 217 * rate = parent_rate * n * (k + 1) 218 * parent_rate is always 24Mhz 219 */ 220 221 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, 222 u8 *n, u8 *k, u8 *m, u8 *p) 223 { 224 u8 div; 225 226 /* Normalize value to a parent_rate multiple (24M) */ 227 div = *freq / parent_rate; 228 *freq = parent_rate * div; 229 230 /* we were called to round the frequency, we can now return */ 231 if (n == NULL) 232 return; 233 234 if (div < 31) 235 *k = 0; 236 else if (div / 2 < 31) 237 *k = 1; 238 else if (div / 3 < 31) 239 *k = 2; 240 else 241 *k = 3; 242 243 *n = DIV_ROUND_UP(div, (*k+1)); 244 } 245 246 /** 247 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6 248 * PLL6 rate is calculated as follows 249 * rate = parent_rate * n * (k + 1) / 2 250 * parent_rate is always 24Mhz 251 */ 252 253 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate, 254 u8 *n, u8 *k, u8 *m, u8 *p) 255 { 256 u8 div; 257 258 /* 259 * We always have 24MHz / 2, so we can just say that our 260 * parent clock is 12MHz. 261 */ 262 parent_rate = parent_rate / 2; 263 264 /* Normalize value to a parent_rate multiple (24M / 2) */ 265 div = *freq / parent_rate; 266 *freq = parent_rate * div; 267 268 /* we were called to round the frequency, we can now return */ 269 if (n == NULL) 270 return; 271 272 *k = div / 32; 273 if (*k > 3) 274 *k = 3; 275 276 *n = DIV_ROUND_UP(div, (*k+1)); 277 } 278 279 /** 280 * sun4i_get_apb1_factors() - calculates m, p factors for APB1 281 * APB1 rate is calculated as follows 282 * rate = (parent_rate >> p) / (m + 1); 283 */ 284 285 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, 286 u8 *n, u8 *k, u8 *m, u8 *p) 287 { 288 u8 calcm, calcp; 289 290 if (parent_rate < *freq) 291 *freq = parent_rate; 292 293 parent_rate = DIV_ROUND_UP(parent_rate, *freq); 294 295 /* Invalid rate! */ 296 if (parent_rate > 32) 297 return; 298 299 if (parent_rate <= 4) 300 calcp = 0; 301 else if (parent_rate <= 8) 302 calcp = 1; 303 else if (parent_rate <= 16) 304 calcp = 2; 305 else 306 calcp = 3; 307 308 calcm = (parent_rate >> calcp) - 1; 309 310 *freq = (parent_rate >> calcp) / (calcm + 1); 311 312 /* we were called to round the frequency, we can now return */ 313 if (n == NULL) 314 return; 315 316 *m = calcm; 317 *p = calcp; 318 } 319 320 321 322 /** 323 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks 324 * MOD0 rate is calculated as follows 325 * rate = (parent_rate >> p) / (m + 1); 326 */ 327 328 static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, 329 u8 *n, u8 *k, u8 *m, u8 *p) 330 { 331 u8 div, calcm, calcp; 332 333 /* These clocks can only divide, so we will never be able to achieve 334 * frequencies higher than the parent frequency */ 335 if (*freq > parent_rate) 336 *freq = parent_rate; 337 338 div = DIV_ROUND_UP(parent_rate, *freq); 339 340 if (div < 16) 341 calcp = 0; 342 else if (div / 2 < 16) 343 calcp = 1; 344 else if (div / 4 < 16) 345 calcp = 2; 346 else 347 calcp = 3; 348 349 calcm = DIV_ROUND_UP(div, 1 << calcp); 350 351 *freq = (parent_rate >> calcp) / calcm; 352 353 /* we were called to round the frequency, we can now return */ 354 if (n == NULL) 355 return; 356 357 *m = calcm - 1; 358 *p = calcp; 359 } 360 361 362 363 /** 364 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B 365 * CLK_OUT rate is calculated as follows 366 * rate = (parent_rate >> p) / (m + 1); 367 */ 368 369 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, 370 u8 *n, u8 *k, u8 *m, u8 *p) 371 { 372 u8 div, calcm, calcp; 373 374 /* These clocks can only divide, so we will never be able to achieve 375 * frequencies higher than the parent frequency */ 376 if (*freq > parent_rate) 377 *freq = parent_rate; 378 379 div = DIV_ROUND_UP(parent_rate, *freq); 380 381 if (div < 32) 382 calcp = 0; 383 else if (div / 2 < 32) 384 calcp = 1; 385 else if (div / 4 < 32) 386 calcp = 2; 387 else 388 calcp = 3; 389 390 calcm = DIV_ROUND_UP(div, 1 << calcp); 391 392 *freq = (parent_rate >> calcp) / calcm; 393 394 /* we were called to round the frequency, we can now return */ 395 if (n == NULL) 396 return; 397 398 *m = calcm - 1; 399 *p = calcp; 400 } 401 402 /** 403 * clk_sunxi_mmc_phase_control() - configures MMC clock phase control 404 */ 405 406 void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output) 407 { 408 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 409 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) 410 411 struct clk_hw *hw = __clk_get_hw(clk); 412 struct clk_composite *composite = to_clk_composite(hw); 413 struct clk_hw *rate_hw = composite->rate_hw; 414 struct clk_factors *factors = to_clk_factors(rate_hw); 415 unsigned long flags = 0; 416 u32 reg; 417 418 if (factors->lock) 419 spin_lock_irqsave(factors->lock, flags); 420 421 reg = readl(factors->reg); 422 423 /* set sample clock phase control */ 424 reg &= ~(0x7 << 20); 425 reg |= ((sample & 0x7) << 20); 426 427 /* set output clock phase control */ 428 reg &= ~(0x7 << 8); 429 reg |= ((output & 0x7) << 8); 430 431 writel(reg, factors->reg); 432 433 if (factors->lock) 434 spin_unlock_irqrestore(factors->lock, flags); 435 } 436 EXPORT_SYMBOL(clk_sunxi_mmc_phase_control); 437 438 439 /** 440 * sunxi_factors_clk_setup() - Setup function for factor clocks 441 */ 442 443 #define SUNXI_FACTORS_MUX_MASK 0x3 444 445 struct factors_data { 446 int enable; 447 int mux; 448 struct clk_factors_config *table; 449 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); 450 const char *name; 451 }; 452 453 static struct clk_factors_config sun4i_pll1_config = { 454 .nshift = 8, 455 .nwidth = 5, 456 .kshift = 4, 457 .kwidth = 2, 458 .mshift = 0, 459 .mwidth = 2, 460 .pshift = 16, 461 .pwidth = 2, 462 }; 463 464 static struct clk_factors_config sun6i_a31_pll1_config = { 465 .nshift = 8, 466 .nwidth = 5, 467 .kshift = 4, 468 .kwidth = 2, 469 .mshift = 0, 470 .mwidth = 2, 471 }; 472 473 static struct clk_factors_config sun8i_a23_pll1_config = { 474 .nshift = 8, 475 .nwidth = 5, 476 .kshift = 4, 477 .kwidth = 2, 478 .mshift = 0, 479 .mwidth = 2, 480 .pshift = 16, 481 .pwidth = 2, 482 .n_start = 1, 483 }; 484 485 static struct clk_factors_config sun4i_pll5_config = { 486 .nshift = 8, 487 .nwidth = 5, 488 .kshift = 4, 489 .kwidth = 2, 490 }; 491 492 static struct clk_factors_config sun6i_a31_pll6_config = { 493 .nshift = 8, 494 .nwidth = 5, 495 .kshift = 4, 496 .kwidth = 2, 497 }; 498 499 static struct clk_factors_config sun4i_apb1_config = { 500 .mshift = 0, 501 .mwidth = 5, 502 .pshift = 16, 503 .pwidth = 2, 504 }; 505 506 /* user manual says "n" but it's really "p" */ 507 static struct clk_factors_config sun4i_mod0_config = { 508 .mshift = 0, 509 .mwidth = 4, 510 .pshift = 16, 511 .pwidth = 2, 512 }; 513 514 /* user manual says "n" but it's really "p" */ 515 static struct clk_factors_config sun7i_a20_out_config = { 516 .mshift = 8, 517 .mwidth = 5, 518 .pshift = 20, 519 .pwidth = 2, 520 }; 521 522 static const struct factors_data sun4i_pll1_data __initconst = { 523 .enable = 31, 524 .table = &sun4i_pll1_config, 525 .getter = sun4i_get_pll1_factors, 526 }; 527 528 static const struct factors_data sun6i_a31_pll1_data __initconst = { 529 .enable = 31, 530 .table = &sun6i_a31_pll1_config, 531 .getter = sun6i_a31_get_pll1_factors, 532 }; 533 534 static const struct factors_data sun8i_a23_pll1_data __initconst = { 535 .enable = 31, 536 .table = &sun8i_a23_pll1_config, 537 .getter = sun8i_a23_get_pll1_factors, 538 }; 539 540 static const struct factors_data sun7i_a20_pll4_data __initconst = { 541 .enable = 31, 542 .table = &sun4i_pll5_config, 543 .getter = sun4i_get_pll5_factors, 544 }; 545 546 static const struct factors_data sun4i_pll5_data __initconst = { 547 .enable = 31, 548 .table = &sun4i_pll5_config, 549 .getter = sun4i_get_pll5_factors, 550 .name = "pll5", 551 }; 552 553 static const struct factors_data sun4i_pll6_data __initconst = { 554 .enable = 31, 555 .table = &sun4i_pll5_config, 556 .getter = sun4i_get_pll5_factors, 557 .name = "pll6", 558 }; 559 560 static const struct factors_data sun6i_a31_pll6_data __initconst = { 561 .enable = 31, 562 .table = &sun6i_a31_pll6_config, 563 .getter = sun6i_a31_get_pll6_factors, 564 }; 565 566 static const struct factors_data sun4i_apb1_data __initconst = { 567 .table = &sun4i_apb1_config, 568 .getter = sun4i_get_apb1_factors, 569 }; 570 571 static const struct factors_data sun4i_mod0_data __initconst = { 572 .enable = 31, 573 .mux = 24, 574 .table = &sun4i_mod0_config, 575 .getter = sun4i_get_mod0_factors, 576 }; 577 578 static const struct factors_data sun7i_a20_out_data __initconst = { 579 .enable = 31, 580 .mux = 24, 581 .table = &sun7i_a20_out_config, 582 .getter = sun7i_a20_get_out_factors, 583 }; 584 585 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, 586 const struct factors_data *data) 587 { 588 struct clk *clk; 589 struct clk_factors *factors; 590 struct clk_gate *gate = NULL; 591 struct clk_mux *mux = NULL; 592 struct clk_hw *gate_hw = NULL; 593 struct clk_hw *mux_hw = NULL; 594 const char *clk_name = node->name; 595 const char *parents[SUNXI_MAX_PARENTS]; 596 void __iomem *reg; 597 int i = 0; 598 599 reg = of_iomap(node, 0); 600 601 /* if we have a mux, we will have >1 parents */ 602 while (i < SUNXI_MAX_PARENTS && 603 (parents[i] = of_clk_get_parent_name(node, i)) != NULL) 604 i++; 605 606 /* 607 * some factor clocks, such as pll5 and pll6, may have multiple 608 * outputs, and have their name designated in factors_data 609 */ 610 if (data->name) 611 clk_name = data->name; 612 else 613 of_property_read_string(node, "clock-output-names", &clk_name); 614 615 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); 616 if (!factors) 617 return NULL; 618 619 /* Add a gate if this factor clock can be gated */ 620 if (data->enable) { 621 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 622 if (!gate) { 623 kfree(factors); 624 return NULL; 625 } 626 627 /* set up gate properties */ 628 gate->reg = reg; 629 gate->bit_idx = data->enable; 630 gate->lock = &clk_lock; 631 gate_hw = &gate->hw; 632 } 633 634 /* Add a mux if this factor clock can be muxed */ 635 if (data->mux) { 636 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); 637 if (!mux) { 638 kfree(factors); 639 kfree(gate); 640 return NULL; 641 } 642 643 /* set up gate properties */ 644 mux->reg = reg; 645 mux->shift = data->mux; 646 mux->mask = SUNXI_FACTORS_MUX_MASK; 647 mux->lock = &clk_lock; 648 mux_hw = &mux->hw; 649 } 650 651 /* set up factors properties */ 652 factors->reg = reg; 653 factors->config = data->table; 654 factors->get_factors = data->getter; 655 factors->lock = &clk_lock; 656 657 clk = clk_register_composite(NULL, clk_name, 658 parents, i, 659 mux_hw, &clk_mux_ops, 660 &factors->hw, &clk_factors_ops, 661 gate_hw, &clk_gate_ops, 0); 662 663 if (!IS_ERR(clk)) { 664 of_clk_add_provider(node, of_clk_src_simple_get, clk); 665 clk_register_clkdev(clk, clk_name, NULL); 666 } 667 668 return clk; 669 } 670 671 672 673 /** 674 * sunxi_mux_clk_setup() - Setup function for muxes 675 */ 676 677 #define SUNXI_MUX_GATE_WIDTH 2 678 679 struct mux_data { 680 u8 shift; 681 }; 682 683 static const struct mux_data sun4i_cpu_mux_data __initconst = { 684 .shift = 16, 685 }; 686 687 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { 688 .shift = 12, 689 }; 690 691 static const struct mux_data sun4i_apb1_mux_data __initconst = { 692 .shift = 24, 693 }; 694 695 static void __init sunxi_mux_clk_setup(struct device_node *node, 696 struct mux_data *data) 697 { 698 struct clk *clk; 699 const char *clk_name = node->name; 700 const char *parents[SUNXI_MAX_PARENTS]; 701 void __iomem *reg; 702 int i = 0; 703 704 reg = of_iomap(node, 0); 705 706 while (i < SUNXI_MAX_PARENTS && 707 (parents[i] = of_clk_get_parent_name(node, i)) != NULL) 708 i++; 709 710 of_property_read_string(node, "clock-output-names", &clk_name); 711 712 clk = clk_register_mux(NULL, clk_name, parents, i, 713 CLK_SET_RATE_NO_REPARENT, reg, 714 data->shift, SUNXI_MUX_GATE_WIDTH, 715 0, &clk_lock); 716 717 if (clk) { 718 of_clk_add_provider(node, of_clk_src_simple_get, clk); 719 clk_register_clkdev(clk, clk_name, NULL); 720 } 721 } 722 723 724 725 /** 726 * sunxi_divider_clk_setup() - Setup function for simple divider clocks 727 */ 728 729 struct div_data { 730 u8 shift; 731 u8 pow; 732 u8 width; 733 const struct clk_div_table *table; 734 }; 735 736 static const struct div_data sun4i_axi_data __initconst = { 737 .shift = 0, 738 .pow = 0, 739 .width = 2, 740 }; 741 742 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = { 743 { .val = 0, .div = 1 }, 744 { .val = 1, .div = 2 }, 745 { .val = 2, .div = 3 }, 746 { .val = 3, .div = 4 }, 747 { .val = 4, .div = 4 }, 748 { .val = 5, .div = 4 }, 749 { .val = 6, .div = 4 }, 750 { .val = 7, .div = 4 }, 751 { } /* sentinel */ 752 }; 753 754 static const struct div_data sun8i_a23_axi_data __initconst = { 755 .width = 3, 756 .table = sun8i_a23_axi_table, 757 }; 758 759 static const struct div_data sun4i_ahb_data __initconst = { 760 .shift = 4, 761 .pow = 1, 762 .width = 2, 763 }; 764 765 static const struct div_data sun4i_apb0_data __initconst = { 766 .shift = 8, 767 .pow = 1, 768 .width = 2, 769 }; 770 771 static const struct div_data sun6i_a31_apb2_div_data __initconst = { 772 .shift = 0, 773 .pow = 0, 774 .width = 4, 775 }; 776 777 static void __init sunxi_divider_clk_setup(struct device_node *node, 778 struct div_data *data) 779 { 780 struct clk *clk; 781 const char *clk_name = node->name; 782 const char *clk_parent; 783 void __iomem *reg; 784 785 reg = of_iomap(node, 0); 786 787 clk_parent = of_clk_get_parent_name(node, 0); 788 789 of_property_read_string(node, "clock-output-names", &clk_name); 790 791 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, 792 reg, data->shift, data->width, 793 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, 794 data->table, &clk_lock); 795 if (clk) { 796 of_clk_add_provider(node, of_clk_src_simple_get, clk); 797 clk_register_clkdev(clk, clk_name, NULL); 798 } 799 } 800 801 802 803 /** 804 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling 805 */ 806 807 struct gates_reset_data { 808 void __iomem *reg; 809 spinlock_t *lock; 810 struct reset_controller_dev rcdev; 811 }; 812 813 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev, 814 unsigned long id) 815 { 816 struct gates_reset_data *data = container_of(rcdev, 817 struct gates_reset_data, 818 rcdev); 819 unsigned long flags; 820 u32 reg; 821 822 spin_lock_irqsave(data->lock, flags); 823 824 reg = readl(data->reg); 825 writel(reg & ~BIT(id), data->reg); 826 827 spin_unlock_irqrestore(data->lock, flags); 828 829 return 0; 830 } 831 832 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev, 833 unsigned long id) 834 { 835 struct gates_reset_data *data = container_of(rcdev, 836 struct gates_reset_data, 837 rcdev); 838 unsigned long flags; 839 u32 reg; 840 841 spin_lock_irqsave(data->lock, flags); 842 843 reg = readl(data->reg); 844 writel(reg | BIT(id), data->reg); 845 846 spin_unlock_irqrestore(data->lock, flags); 847 848 return 0; 849 } 850 851 static struct reset_control_ops sunxi_gates_reset_ops = { 852 .assert = sunxi_gates_reset_assert, 853 .deassert = sunxi_gates_reset_deassert, 854 }; 855 856 /** 857 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks 858 */ 859 860 #define SUNXI_GATES_MAX_SIZE 64 861 862 struct gates_data { 863 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); 864 u32 reset_mask; 865 }; 866 867 static const struct gates_data sun4i_axi_gates_data __initconst = { 868 .mask = {1}, 869 }; 870 871 static const struct gates_data sun4i_ahb_gates_data __initconst = { 872 .mask = {0x7F77FFF, 0x14FB3F}, 873 }; 874 875 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { 876 .mask = {0x147667e7, 0x185915}, 877 }; 878 879 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = { 880 .mask = {0x107067e7, 0x185111}, 881 }; 882 883 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = { 884 .mask = {0xEDFE7F62, 0x794F931}, 885 }; 886 887 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = { 888 .mask = { 0x12f77fff, 0x16ff3f }, 889 }; 890 891 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = { 892 .mask = {0x25386742, 0x2505111}, 893 }; 894 895 static const struct gates_data sun4i_apb0_gates_data __initconst = { 896 .mask = {0x4EF}, 897 }; 898 899 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = { 900 .mask = {0x469}, 901 }; 902 903 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { 904 .mask = {0x61}, 905 }; 906 907 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { 908 .mask = { 0x4ff }, 909 }; 910 911 static const struct gates_data sun4i_apb1_gates_data __initconst = { 912 .mask = {0xFF00F7}, 913 }; 914 915 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = { 916 .mask = {0xf0007}, 917 }; 918 919 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = { 920 .mask = {0xa0007}, 921 }; 922 923 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = { 924 .mask = {0x3031}, 925 }; 926 927 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = { 928 .mask = {0x3021}, 929 }; 930 931 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { 932 .mask = {0x3F000F}, 933 }; 934 935 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { 936 .mask = { 0xff80ff }, 937 }; 938 939 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = { 940 .mask = {0x1F0007}, 941 }; 942 943 static const struct gates_data sun4i_a10_usb_gates_data __initconst = { 944 .mask = {0x1C0}, 945 .reset_mask = 0x07, 946 }; 947 948 static const struct gates_data sun5i_a13_usb_gates_data __initconst = { 949 .mask = {0x140}, 950 .reset_mask = 0x03, 951 }; 952 953 static const struct gates_data sun6i_a31_usb_gates_data __initconst = { 954 .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) }, 955 .reset_mask = BIT(2) | BIT(1) | BIT(0), 956 }; 957 958 static void __init sunxi_gates_clk_setup(struct device_node *node, 959 struct gates_data *data) 960 { 961 struct clk_onecell_data *clk_data; 962 struct gates_reset_data *reset_data; 963 const char *clk_parent; 964 const char *clk_name; 965 void __iomem *reg; 966 int qty; 967 int i = 0; 968 int j = 0; 969 970 reg = of_iomap(node, 0); 971 972 clk_parent = of_clk_get_parent_name(node, 0); 973 974 /* Worst-case size approximation and memory allocation */ 975 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); 976 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); 977 if (!clk_data) 978 return; 979 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); 980 if (!clk_data->clks) { 981 kfree(clk_data); 982 return; 983 } 984 985 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { 986 of_property_read_string_index(node, "clock-output-names", 987 j, &clk_name); 988 989 clk_data->clks[i] = clk_register_gate(NULL, clk_name, 990 clk_parent, 0, 991 reg + 4 * (i/32), i % 32, 992 0, &clk_lock); 993 WARN_ON(IS_ERR(clk_data->clks[i])); 994 clk_register_clkdev(clk_data->clks[i], clk_name, NULL); 995 996 j++; 997 } 998 999 /* Adjust to the real max */ 1000 clk_data->clk_num = i; 1001 1002 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1003 1004 /* Register a reset controler for gates with reset bits */ 1005 if (data->reset_mask == 0) 1006 return; 1007 1008 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL); 1009 if (!reset_data) 1010 return; 1011 1012 reset_data->reg = reg; 1013 reset_data->lock = &clk_lock; 1014 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; 1015 reset_data->rcdev.ops = &sunxi_gates_reset_ops; 1016 reset_data->rcdev.of_node = node; 1017 reset_controller_register(&reset_data->rcdev); 1018 } 1019 1020 1021 1022 /** 1023 * sunxi_divs_clk_setup() helper data 1024 */ 1025 1026 #define SUNXI_DIVS_MAX_QTY 2 1027 #define SUNXI_DIVISOR_WIDTH 2 1028 1029 struct divs_data { 1030 const struct factors_data *factors; /* data for the factor clock */ 1031 struct { 1032 u8 fixed; /* is it a fixed divisor? if not... */ 1033 struct clk_div_table *table; /* is it a table based divisor? */ 1034 u8 shift; /* otherwise it's a normal divisor with this shift */ 1035 u8 pow; /* is it power-of-two based? */ 1036 u8 gate; /* is it independently gateable? */ 1037 } div[SUNXI_DIVS_MAX_QTY]; 1038 }; 1039 1040 static struct clk_div_table pll6_sata_tbl[] = { 1041 { .val = 0, .div = 6, }, 1042 { .val = 1, .div = 12, }, 1043 { .val = 2, .div = 18, }, 1044 { .val = 3, .div = 24, }, 1045 { } /* sentinel */ 1046 }; 1047 1048 static const struct divs_data pll5_divs_data __initconst = { 1049 .factors = &sun4i_pll5_data, 1050 .div = { 1051 { .shift = 0, .pow = 0, }, /* M, DDR */ 1052 { .shift = 16, .pow = 1, }, /* P, other */ 1053 } 1054 }; 1055 1056 static const struct divs_data pll6_divs_data __initconst = { 1057 .factors = &sun4i_pll6_data, 1058 .div = { 1059 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ 1060 { .fixed = 2 }, /* P, other */ 1061 } 1062 }; 1063 1064 /** 1065 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks 1066 * 1067 * These clocks look something like this 1068 * ________________________ 1069 * | ___divisor 1---|----> to consumer 1070 * parent >--| pll___/___divisor 2---|----> to consumer 1071 * | \_______________|____> to consumer 1072 * |________________________| 1073 */ 1074 1075 static void __init sunxi_divs_clk_setup(struct device_node *node, 1076 struct divs_data *data) 1077 { 1078 struct clk_onecell_data *clk_data; 1079 const char *parent; 1080 const char *clk_name; 1081 struct clk **clks, *pclk; 1082 struct clk_hw *gate_hw, *rate_hw; 1083 const struct clk_ops *rate_ops; 1084 struct clk_gate *gate = NULL; 1085 struct clk_fixed_factor *fix_factor; 1086 struct clk_divider *divider; 1087 void __iomem *reg; 1088 int i = 0; 1089 int flags, clkflags; 1090 1091 /* Set up factor clock that we will be dividing */ 1092 pclk = sunxi_factors_clk_setup(node, data->factors); 1093 parent = __clk_get_name(pclk); 1094 1095 reg = of_iomap(node, 0); 1096 1097 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); 1098 if (!clk_data) 1099 return; 1100 1101 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); 1102 if (!clks) 1103 goto free_clkdata; 1104 1105 clk_data->clks = clks; 1106 1107 /* It's not a good idea to have automatic reparenting changing 1108 * our RAM clock! */ 1109 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; 1110 1111 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) { 1112 if (of_property_read_string_index(node, "clock-output-names", 1113 i, &clk_name) != 0) 1114 break; 1115 1116 gate_hw = NULL; 1117 rate_hw = NULL; 1118 rate_ops = NULL; 1119 1120 /* If this leaf clock can be gated, create a gate */ 1121 if (data->div[i].gate) { 1122 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 1123 if (!gate) 1124 goto free_clks; 1125 1126 gate->reg = reg; 1127 gate->bit_idx = data->div[i].gate; 1128 gate->lock = &clk_lock; 1129 1130 gate_hw = &gate->hw; 1131 } 1132 1133 /* Leaves can be fixed or configurable divisors */ 1134 if (data->div[i].fixed) { 1135 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL); 1136 if (!fix_factor) 1137 goto free_gate; 1138 1139 fix_factor->mult = 1; 1140 fix_factor->div = data->div[i].fixed; 1141 1142 rate_hw = &fix_factor->hw; 1143 rate_ops = &clk_fixed_factor_ops; 1144 } else { 1145 divider = kzalloc(sizeof(*divider), GFP_KERNEL); 1146 if (!divider) 1147 goto free_gate; 1148 1149 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; 1150 1151 divider->reg = reg; 1152 divider->shift = data->div[i].shift; 1153 divider->width = SUNXI_DIVISOR_WIDTH; 1154 divider->flags = flags; 1155 divider->lock = &clk_lock; 1156 divider->table = data->div[i].table; 1157 1158 rate_hw = ÷r->hw; 1159 rate_ops = &clk_divider_ops; 1160 } 1161 1162 /* Wrap the (potential) gate and the divisor on a composite 1163 * clock to unify them */ 1164 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, 1165 NULL, NULL, 1166 rate_hw, rate_ops, 1167 gate_hw, &clk_gate_ops, 1168 clkflags); 1169 1170 WARN_ON(IS_ERR(clk_data->clks[i])); 1171 clk_register_clkdev(clks[i], clk_name, NULL); 1172 } 1173 1174 /* The last clock available on the getter is the parent */ 1175 clks[i++] = pclk; 1176 1177 /* Adjust to the real max */ 1178 clk_data->clk_num = i; 1179 1180 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1181 1182 return; 1183 1184 free_gate: 1185 kfree(gate); 1186 free_clks: 1187 kfree(clks); 1188 free_clkdata: 1189 kfree(clk_data); 1190 } 1191 1192 1193 1194 /* Matches for factors clocks */ 1195 static const struct of_device_id clk_factors_match[] __initconst = { 1196 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,}, 1197 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, 1198 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,}, 1199 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,}, 1200 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,}, 1201 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,}, 1202 {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,}, 1203 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,}, 1204 {} 1205 }; 1206 1207 /* Matches for divider clocks */ 1208 static const struct of_device_id clk_div_match[] __initconst = { 1209 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,}, 1210 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,}, 1211 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,}, 1212 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,}, 1213 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, 1214 {} 1215 }; 1216 1217 /* Matches for divided outputs */ 1218 static const struct of_device_id clk_divs_match[] __initconst = { 1219 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,}, 1220 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,}, 1221 {} 1222 }; 1223 1224 /* Matches for mux clocks */ 1225 static const struct of_device_id clk_mux_match[] __initconst = { 1226 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,}, 1227 {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,}, 1228 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, 1229 {} 1230 }; 1231 1232 /* Matches for gate clocks */ 1233 static const struct of_device_id clk_gates_match[] __initconst = { 1234 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,}, 1235 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, 1236 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,}, 1237 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, 1238 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, 1239 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, 1240 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,}, 1241 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, 1242 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, 1243 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, 1244 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, 1245 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, 1246 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, 1247 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, 1248 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, 1249 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, 1250 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,}, 1251 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, 1252 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,}, 1253 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,}, 1254 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,}, 1255 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,}, 1256 {} 1257 }; 1258 1259 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, 1260 void *function) 1261 { 1262 struct device_node *np; 1263 const struct div_data *data; 1264 const struct of_device_id *match; 1265 void (*setup_function)(struct device_node *, const void *) = function; 1266 1267 for_each_matching_node_and_match(np, clk_match, &match) { 1268 data = match->data; 1269 setup_function(np, data); 1270 } 1271 } 1272 1273 static void __init sunxi_init_clocks(const char *clocks[], int nclocks) 1274 { 1275 unsigned int i; 1276 1277 /* Register factor clocks */ 1278 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); 1279 1280 /* Register divider clocks */ 1281 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); 1282 1283 /* Register divided output clocks */ 1284 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup); 1285 1286 /* Register mux clocks */ 1287 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); 1288 1289 /* Register gate clocks */ 1290 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); 1291 1292 /* Protect the clocks that needs to stay on */ 1293 for (i = 0; i < nclocks; i++) { 1294 struct clk *clk = clk_get(NULL, clocks[i]); 1295 1296 if (!IS_ERR(clk)) 1297 clk_prepare_enable(clk); 1298 } 1299 } 1300 1301 static const char *sun4i_a10_critical_clocks[] __initdata = { 1302 "pll5_ddr", 1303 "ahb_sdram", 1304 }; 1305 1306 static void __init sun4i_a10_init_clocks(struct device_node *node) 1307 { 1308 sunxi_init_clocks(sun4i_a10_critical_clocks, 1309 ARRAY_SIZE(sun4i_a10_critical_clocks)); 1310 } 1311 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks); 1312 1313 static const char *sun5i_critical_clocks[] __initdata = { 1314 "mbus", 1315 "pll5_ddr", 1316 "ahb_sdram", 1317 }; 1318 1319 static void __init sun5i_init_clocks(struct device_node *node) 1320 { 1321 sunxi_init_clocks(sun5i_critical_clocks, 1322 ARRAY_SIZE(sun5i_critical_clocks)); 1323 } 1324 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks); 1325 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks); 1326 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks); 1327 1328 static const char *sun6i_critical_clocks[] __initdata = { 1329 "cpu", 1330 "ahb1_sdram", 1331 }; 1332 1333 static void __init sun6i_init_clocks(struct device_node *node) 1334 { 1335 sunxi_init_clocks(sun6i_critical_clocks, 1336 ARRAY_SIZE(sun6i_critical_clocks)); 1337 } 1338 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks); 1339 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks); 1340