1 /* 2 * Copyright 2013 Emilio López 3 * 4 * Emilio López <emilio@elopez.com.ar> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk-provider.h> 18 #include <linux/clkdev.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 22 #include "clk-factors.h" 23 24 static DEFINE_SPINLOCK(clk_lock); 25 26 /** 27 * sun4i_osc_clk_setup() - Setup function for gatable oscillator 28 */ 29 30 #define SUNXI_OSC24M_GATE 0 31 32 static void __init sun4i_osc_clk_setup(struct device_node *node) 33 { 34 struct clk *clk; 35 struct clk_fixed_rate *fixed; 36 struct clk_gate *gate; 37 const char *clk_name = node->name; 38 u32 rate; 39 40 /* allocate fixed-rate and gate clock structs */ 41 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); 42 if (!fixed) 43 return; 44 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 45 if (!gate) { 46 kfree(fixed); 47 return; 48 } 49 50 if (of_property_read_u32(node, "clock-frequency", &rate)) 51 return; 52 53 /* set up gate and fixed rate properties */ 54 gate->reg = of_iomap(node, 0); 55 gate->bit_idx = SUNXI_OSC24M_GATE; 56 gate->lock = &clk_lock; 57 fixed->fixed_rate = rate; 58 59 clk = clk_register_composite(NULL, clk_name, 60 NULL, 0, 61 NULL, NULL, 62 &fixed->hw, &clk_fixed_rate_ops, 63 &gate->hw, &clk_gate_ops, 64 CLK_IS_ROOT); 65 66 if (!IS_ERR(clk)) { 67 of_clk_add_provider(node, of_clk_src_simple_get, clk); 68 clk_register_clkdev(clk, clk_name, NULL); 69 } 70 } 71 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup); 72 73 74 75 /** 76 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 77 * PLL1 rate is calculated as follows 78 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); 79 * parent_rate is always 24Mhz 80 */ 81 82 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, 83 u8 *n, u8 *k, u8 *m, u8 *p) 84 { 85 u8 div; 86 87 /* Normalize value to a 6M multiple */ 88 div = *freq / 6000000; 89 *freq = 6000000 * div; 90 91 /* we were called to round the frequency, we can now return */ 92 if (n == NULL) 93 return; 94 95 /* m is always zero for pll1 */ 96 *m = 0; 97 98 /* k is 1 only on these cases */ 99 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) 100 *k = 1; 101 else 102 *k = 0; 103 104 /* p will be 3 for divs under 10 */ 105 if (div < 10) 106 *p = 3; 107 108 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ 109 else if (div < 20 || (div < 32 && (div & 1))) 110 *p = 2; 111 112 /* p will be 1 for even divs under 32, divs under 40 and odd pairs 113 * of divs between 40-62 */ 114 else if (div < 40 || (div < 64 && (div & 2))) 115 *p = 1; 116 117 /* any other entries have p = 0 */ 118 else 119 *p = 0; 120 121 /* calculate a suitable n based on k and p */ 122 div <<= *p; 123 div /= (*k + 1); 124 *n = div / 4; 125 } 126 127 /** 128 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 129 * PLL1 rate is calculated as follows 130 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1); 131 * parent_rate should always be 24MHz 132 */ 133 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, 134 u8 *n, u8 *k, u8 *m, u8 *p) 135 { 136 /* 137 * We can operate only on MHz, this will make our life easier 138 * later. 139 */ 140 u32 freq_mhz = *freq / 1000000; 141 u32 parent_freq_mhz = parent_rate / 1000000; 142 143 /* 144 * Round down the frequency to the closest multiple of either 145 * 6 or 16 146 */ 147 u32 round_freq_6 = round_down(freq_mhz, 6); 148 u32 round_freq_16 = round_down(freq_mhz, 16); 149 150 if (round_freq_6 > round_freq_16) 151 freq_mhz = round_freq_6; 152 else 153 freq_mhz = round_freq_16; 154 155 *freq = freq_mhz * 1000000; 156 157 /* 158 * If the factors pointer are null, we were just called to 159 * round down the frequency. 160 * Exit. 161 */ 162 if (n == NULL) 163 return; 164 165 /* If the frequency is a multiple of 32 MHz, k is always 3 */ 166 if (!(freq_mhz % 32)) 167 *k = 3; 168 /* If the frequency is a multiple of 9 MHz, k is always 2 */ 169 else if (!(freq_mhz % 9)) 170 *k = 2; 171 /* If the frequency is a multiple of 8 MHz, k is always 1 */ 172 else if (!(freq_mhz % 8)) 173 *k = 1; 174 /* Otherwise, we don't use the k factor */ 175 else 176 *k = 0; 177 178 /* 179 * If the frequency is a multiple of 2 but not a multiple of 180 * 3, m is 3. This is the first time we use 6 here, yet we 181 * will use it on several other places. 182 * We use this number because it's the lowest frequency we can 183 * generate (with n = 0, k = 0, m = 3), so every other frequency 184 * somehow relates to this frequency. 185 */ 186 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) 187 *m = 2; 188 /* 189 * If the frequency is a multiple of 6MHz, but the factor is 190 * odd, m will be 3 191 */ 192 else if ((freq_mhz / 6) & 1) 193 *m = 3; 194 /* Otherwise, we end up with m = 1 */ 195 else 196 *m = 1; 197 198 /* Calculate n thanks to the above factors we already got */ 199 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1; 200 201 /* 202 * If n end up being outbound, and that we can still decrease 203 * m, do it. 204 */ 205 if ((*n + 1) > 31 && (*m + 1) > 1) { 206 *n = (*n + 1) / 2 - 1; 207 *m = (*m + 1) / 2 - 1; 208 } 209 } 210 211 /** 212 * sun4i_get_apb1_factors() - calculates m, p factors for APB1 213 * APB1 rate is calculated as follows 214 * rate = (parent_rate >> p) / (m + 1); 215 */ 216 217 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, 218 u8 *n, u8 *k, u8 *m, u8 *p) 219 { 220 u8 calcm, calcp; 221 222 if (parent_rate < *freq) 223 *freq = parent_rate; 224 225 parent_rate = (parent_rate + (*freq - 1)) / *freq; 226 227 /* Invalid rate! */ 228 if (parent_rate > 32) 229 return; 230 231 if (parent_rate <= 4) 232 calcp = 0; 233 else if (parent_rate <= 8) 234 calcp = 1; 235 else if (parent_rate <= 16) 236 calcp = 2; 237 else 238 calcp = 3; 239 240 calcm = (parent_rate >> calcp) - 1; 241 242 *freq = (parent_rate >> calcp) / (calcm + 1); 243 244 /* we were called to round the frequency, we can now return */ 245 if (n == NULL) 246 return; 247 248 *m = calcm; 249 *p = calcp; 250 } 251 252 253 254 /** 255 * sunxi_factors_clk_setup() - Setup function for factor clocks 256 */ 257 258 struct factors_data { 259 struct clk_factors_config *table; 260 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); 261 }; 262 263 static struct clk_factors_config sun4i_pll1_config = { 264 .nshift = 8, 265 .nwidth = 5, 266 .kshift = 4, 267 .kwidth = 2, 268 .mshift = 0, 269 .mwidth = 2, 270 .pshift = 16, 271 .pwidth = 2, 272 }; 273 274 static struct clk_factors_config sun6i_a31_pll1_config = { 275 .nshift = 8, 276 .nwidth = 5, 277 .kshift = 4, 278 .kwidth = 2, 279 .mshift = 0, 280 .mwidth = 2, 281 }; 282 283 static struct clk_factors_config sun4i_apb1_config = { 284 .mshift = 0, 285 .mwidth = 5, 286 .pshift = 16, 287 .pwidth = 2, 288 }; 289 290 static const struct factors_data sun4i_pll1_data __initconst = { 291 .table = &sun4i_pll1_config, 292 .getter = sun4i_get_pll1_factors, 293 }; 294 295 static const struct factors_data sun6i_a31_pll1_data __initconst = { 296 .table = &sun6i_a31_pll1_config, 297 .getter = sun6i_a31_get_pll1_factors, 298 }; 299 300 static const struct factors_data sun4i_apb1_data __initconst = { 301 .table = &sun4i_apb1_config, 302 .getter = sun4i_get_apb1_factors, 303 }; 304 305 static void __init sunxi_factors_clk_setup(struct device_node *node, 306 struct factors_data *data) 307 { 308 struct clk *clk; 309 const char *clk_name = node->name; 310 const char *parent; 311 void *reg; 312 313 reg = of_iomap(node, 0); 314 315 parent = of_clk_get_parent_name(node, 0); 316 317 clk = clk_register_factors(NULL, clk_name, parent, 0, reg, 318 data->table, data->getter, &clk_lock); 319 320 if (!IS_ERR(clk)) { 321 of_clk_add_provider(node, of_clk_src_simple_get, clk); 322 clk_register_clkdev(clk, clk_name, NULL); 323 } 324 } 325 326 327 328 /** 329 * sunxi_mux_clk_setup() - Setup function for muxes 330 */ 331 332 #define SUNXI_MUX_GATE_WIDTH 2 333 334 struct mux_data { 335 u8 shift; 336 }; 337 338 static const struct mux_data sun4i_cpu_mux_data __initconst = { 339 .shift = 16, 340 }; 341 342 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { 343 .shift = 12, 344 }; 345 346 static const struct mux_data sun4i_apb1_mux_data __initconst = { 347 .shift = 24, 348 }; 349 350 static void __init sunxi_mux_clk_setup(struct device_node *node, 351 struct mux_data *data) 352 { 353 struct clk *clk; 354 const char *clk_name = node->name; 355 const char *parents[5]; 356 void *reg; 357 int i = 0; 358 359 reg = of_iomap(node, 0); 360 361 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL) 362 i++; 363 364 clk = clk_register_mux(NULL, clk_name, parents, i, 365 CLK_SET_RATE_NO_REPARENT, reg, 366 data->shift, SUNXI_MUX_GATE_WIDTH, 367 0, &clk_lock); 368 369 if (clk) { 370 of_clk_add_provider(node, of_clk_src_simple_get, clk); 371 clk_register_clkdev(clk, clk_name, NULL); 372 } 373 } 374 375 376 377 /** 378 * sunxi_divider_clk_setup() - Setup function for simple divider clocks 379 */ 380 381 struct div_data { 382 u8 shift; 383 u8 pow; 384 u8 width; 385 }; 386 387 static const struct div_data sun4i_axi_data __initconst = { 388 .shift = 0, 389 .pow = 0, 390 .width = 2, 391 }; 392 393 static const struct div_data sun4i_ahb_data __initconst = { 394 .shift = 4, 395 .pow = 1, 396 .width = 2, 397 }; 398 399 static const struct div_data sun4i_apb0_data __initconst = { 400 .shift = 8, 401 .pow = 1, 402 .width = 2, 403 }; 404 405 static const struct div_data sun6i_a31_apb2_div_data __initconst = { 406 .shift = 0, 407 .pow = 0, 408 .width = 4, 409 }; 410 411 static void __init sunxi_divider_clk_setup(struct device_node *node, 412 struct div_data *data) 413 { 414 struct clk *clk; 415 const char *clk_name = node->name; 416 const char *clk_parent; 417 void *reg; 418 419 reg = of_iomap(node, 0); 420 421 clk_parent = of_clk_get_parent_name(node, 0); 422 423 clk = clk_register_divider(NULL, clk_name, clk_parent, 0, 424 reg, data->shift, data->width, 425 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, 426 &clk_lock); 427 if (clk) { 428 of_clk_add_provider(node, of_clk_src_simple_get, clk); 429 clk_register_clkdev(clk, clk_name, NULL); 430 } 431 } 432 433 434 435 /** 436 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks 437 */ 438 439 #define SUNXI_GATES_MAX_SIZE 64 440 441 struct gates_data { 442 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); 443 }; 444 445 static const struct gates_data sun4i_axi_gates_data __initconst = { 446 .mask = {1}, 447 }; 448 449 static const struct gates_data sun4i_ahb_gates_data __initconst = { 450 .mask = {0x7F77FFF, 0x14FB3F}, 451 }; 452 453 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { 454 .mask = {0x147667e7, 0x185915}, 455 }; 456 457 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = { 458 .mask = {0x107067e7, 0x185111}, 459 }; 460 461 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = { 462 .mask = {0xEDFE7F62, 0x794F931}, 463 }; 464 465 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = { 466 .mask = { 0x12f77fff, 0x16ff3f }, 467 }; 468 469 static const struct gates_data sun4i_apb0_gates_data __initconst = { 470 .mask = {0x4EF}, 471 }; 472 473 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = { 474 .mask = {0x469}, 475 }; 476 477 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { 478 .mask = {0x61}, 479 }; 480 481 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { 482 .mask = { 0x4ff }, 483 }; 484 485 static const struct gates_data sun4i_apb1_gates_data __initconst = { 486 .mask = {0xFF00F7}, 487 }; 488 489 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = { 490 .mask = {0xf0007}, 491 }; 492 493 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = { 494 .mask = {0xa0007}, 495 }; 496 497 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = { 498 .mask = {0x3031}, 499 }; 500 501 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { 502 .mask = {0x3F000F}, 503 }; 504 505 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { 506 .mask = { 0xff80ff }, 507 }; 508 509 static void __init sunxi_gates_clk_setup(struct device_node *node, 510 struct gates_data *data) 511 { 512 struct clk_onecell_data *clk_data; 513 const char *clk_parent; 514 const char *clk_name; 515 void *reg; 516 int qty; 517 int i = 0; 518 int j = 0; 519 int ignore; 520 521 reg = of_iomap(node, 0); 522 523 clk_parent = of_clk_get_parent_name(node, 0); 524 525 /* Worst-case size approximation and memory allocation */ 526 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); 527 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); 528 if (!clk_data) 529 return; 530 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); 531 if (!clk_data->clks) { 532 kfree(clk_data); 533 return; 534 } 535 536 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { 537 of_property_read_string_index(node, "clock-output-names", 538 j, &clk_name); 539 540 /* No driver claims this clock, but it should remain gated */ 541 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0; 542 543 clk_data->clks[i] = clk_register_gate(NULL, clk_name, 544 clk_parent, ignore, 545 reg + 4 * (i/32), i % 32, 546 0, &clk_lock); 547 WARN_ON(IS_ERR(clk_data->clks[i])); 548 549 j++; 550 } 551 552 /* Adjust to the real max */ 553 clk_data->clk_num = i; 554 555 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 556 } 557 558 /* Matches for factors clocks */ 559 static const struct of_device_id clk_factors_match[] __initconst = { 560 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,}, 561 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, 562 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,}, 563 {} 564 }; 565 566 /* Matches for divider clocks */ 567 static const struct of_device_id clk_div_match[] __initconst = { 568 {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,}, 569 {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,}, 570 {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,}, 571 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, 572 {} 573 }; 574 575 /* Matches for mux clocks */ 576 static const struct of_device_id clk_mux_match[] __initconst = { 577 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,}, 578 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,}, 579 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, 580 {} 581 }; 582 583 /* Matches for gate clocks */ 584 static const struct of_device_id clk_gates_match[] __initconst = { 585 {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,}, 586 {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, 587 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,}, 588 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, 589 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, 590 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, 591 {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, 592 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, 593 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, 594 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, 595 {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, 596 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, 597 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, 598 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, 599 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, 600 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, 601 {} 602 }; 603 604 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, 605 void *function) 606 { 607 struct device_node *np; 608 const struct div_data *data; 609 const struct of_device_id *match; 610 void (*setup_function)(struct device_node *, const void *) = function; 611 612 for_each_matching_node(np, clk_match) { 613 match = of_match_node(clk_match, np); 614 data = match->data; 615 setup_function(np, data); 616 } 617 } 618 619 static void __init sunxi_init_clocks(struct device_node *np) 620 { 621 /* Register factor clocks */ 622 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); 623 624 /* Register divider clocks */ 625 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); 626 627 /* Register mux clocks */ 628 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); 629 630 /* Register gate clocks */ 631 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); 632 } 633 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks); 634 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks); 635 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks); 636 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks); 637 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks); 638