1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2014 Free Electrons
4  *
5  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
6  *
7  * Allwinner A31 APB0 clock gates driver
8  */
9 
10 #include <linux/clk-provider.h>
11 #include <linux/init.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 
16 #define SUN6I_APB0_GATES_MAX_SIZE	32
17 
18 struct gates_data {
19 	DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
20 };
21 
22 static const struct gates_data sun6i_a31_apb0_gates __initconst = {
23 	.mask = {0x7F},
24 };
25 
26 static const struct gates_data sun8i_a23_apb0_gates __initconst = {
27 	.mask = {0x5D},
28 };
29 
30 static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
31 	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
32 	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
33 	{ /* sentinel */ }
34 };
35 
36 static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
37 {
38 	struct device_node *np = pdev->dev.of_node;
39 	struct clk_onecell_data *clk_data;
40 	const struct of_device_id *device;
41 	const struct gates_data *data;
42 	const char *clk_parent;
43 	const char *clk_name;
44 	struct resource *r;
45 	void __iomem *reg;
46 	int ngates;
47 	int i;
48 	int j = 0;
49 
50 	if (!np)
51 		return -ENODEV;
52 
53 	device = of_match_device(sun6i_a31_apb0_gates_clk_dt_ids, &pdev->dev);
54 	if (!device)
55 		return -ENODEV;
56 	data = device->data;
57 
58 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
59 	reg = devm_ioremap_resource(&pdev->dev, r);
60 	if (IS_ERR(reg))
61 		return PTR_ERR(reg);
62 
63 	clk_parent = of_clk_get_parent_name(np, 0);
64 	if (!clk_parent)
65 		return -EINVAL;
66 
67 	clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
68 				GFP_KERNEL);
69 	if (!clk_data)
70 		return -ENOMEM;
71 
72 	/* Worst-case size approximation and memory allocation */
73 	ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
74 	clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
75 				      sizeof(struct clk *), GFP_KERNEL);
76 	if (!clk_data->clks)
77 		return -ENOMEM;
78 
79 	for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
80 		of_property_read_string_index(np, "clock-output-names",
81 					      j, &clk_name);
82 
83 		clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
84 						      clk_parent, 0, reg, i,
85 						      0, NULL);
86 		WARN_ON(IS_ERR(clk_data->clks[i]));
87 
88 		j++;
89 	}
90 
91 	clk_data->clk_num = ngates + 1;
92 
93 	return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
94 }
95 
96 static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
97 	.driver = {
98 		.name = "sun6i-a31-apb0-gates-clk",
99 		.of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
100 	},
101 	.probe = sun6i_a31_apb0_gates_clk_probe,
102 };
103 builtin_platform_driver(sun6i_a31_apb0_gates_clk_driver);
104