1 /*
2  * Copyright 2015 Maxime Ripard
3  *
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <linux/clk-provider.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 
24 #define TCON_CH1_SCLK2_PARENTS		4
25 
26 #define TCON_CH1_SCLK2_GATE_BIT		BIT(31)
27 #define TCON_CH1_SCLK2_MUX_MASK		3
28 #define TCON_CH1_SCLK2_MUX_SHIFT	24
29 #define TCON_CH1_SCLK2_DIV_MASK		0xf
30 #define TCON_CH1_SCLK2_DIV_SHIFT	0
31 
32 #define TCON_CH1_SCLK1_GATE_BIT		BIT(15)
33 #define TCON_CH1_SCLK1_HALF_BIT		BIT(11)
34 
35 struct tcon_ch1_clk {
36 	struct clk_hw	hw;
37 	spinlock_t	lock;
38 	void __iomem	*reg;
39 };
40 
41 #define hw_to_tclk(hw)	container_of(hw, struct tcon_ch1_clk, hw)
42 
43 static void tcon_ch1_disable(struct clk_hw *hw)
44 {
45 	struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
46 	unsigned long flags;
47 	u32 reg;
48 
49 	spin_lock_irqsave(&tclk->lock, flags);
50 	reg = readl(tclk->reg);
51 	reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
52 	writel(reg, tclk->reg);
53 	spin_unlock_irqrestore(&tclk->lock, flags);
54 }
55 
56 static int tcon_ch1_enable(struct clk_hw *hw)
57 {
58 	struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
59 	unsigned long flags;
60 	u32 reg;
61 
62 	spin_lock_irqsave(&tclk->lock, flags);
63 	reg = readl(tclk->reg);
64 	reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;
65 	writel(reg, tclk->reg);
66 	spin_unlock_irqrestore(&tclk->lock, flags);
67 
68 	return 0;
69 }
70 
71 static int tcon_ch1_is_enabled(struct clk_hw *hw)
72 {
73 	struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
74 	u32 reg;
75 
76 	reg = readl(tclk->reg);
77 	return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
78 }
79 
80 static u8 tcon_ch1_get_parent(struct clk_hw *hw)
81 {
82 	struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
83 	u32 reg;
84 
85 	reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;
86 	reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;
87 
88 	return reg;
89 }
90 
91 static int tcon_ch1_set_parent(struct clk_hw *hw, u8 index)
92 {
93 	struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
94 	unsigned long flags;
95 	u32 reg;
96 
97 	spin_lock_irqsave(&tclk->lock, flags);
98 	reg = readl(tclk->reg);
99 	reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT);
100 	reg |= index << TCON_CH1_SCLK2_MUX_SHIFT;
101 	writel(reg, tclk->reg);
102 	spin_unlock_irqrestore(&tclk->lock, flags);
103 
104 	return 0;
105 };
106 
107 static unsigned long tcon_ch1_calc_divider(unsigned long rate,
108 					   unsigned long parent_rate,
109 					   u8 *div,
110 					   bool *half)
111 {
112 	unsigned long best_rate = 0;
113 	u8 best_m = 0, m;
114 	bool is_double;
115 
116 	for (m = 1; m < 16; m++) {
117 		u8 d;
118 
119 		for (d = 1; d < 3; d++) {
120 			unsigned long tmp_rate;
121 
122 			tmp_rate = parent_rate / m / d;
123 
124 			if (tmp_rate > rate)
125 				continue;
126 
127 			if (!best_rate ||
128 			    (rate - tmp_rate) < (rate - best_rate)) {
129 				best_rate = tmp_rate;
130 				best_m = m;
131 				is_double = d;
132 			}
133 		}
134 	}
135 
136 	if (div && half) {
137 		*div = best_m;
138 		*half = is_double;
139 	}
140 
141 	return best_rate;
142 }
143 
144 static int tcon_ch1_determine_rate(struct clk_hw *hw,
145 				   struct clk_rate_request *req)
146 {
147 	long best_rate = -EINVAL;
148 	int i;
149 
150 	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
151 		unsigned long parent_rate;
152 		unsigned long tmp_rate;
153 		struct clk_hw *parent;
154 
155 		parent = clk_hw_get_parent_by_index(hw, i);
156 		if (!parent)
157 			continue;
158 
159 		parent_rate = clk_hw_get_rate(parent);
160 
161 		tmp_rate = tcon_ch1_calc_divider(req->rate, parent_rate,
162 						 NULL, NULL);
163 
164 		if (best_rate < 0 ||
165 		    (req->rate - tmp_rate) < (req->rate - best_rate)) {
166 			best_rate = tmp_rate;
167 			req->best_parent_rate = parent_rate;
168 			req->best_parent_hw = parent;
169 		}
170 	}
171 
172 	if (best_rate < 0)
173 		return best_rate;
174 
175 	req->rate = best_rate;
176 	return 0;
177 }
178 
179 static unsigned long tcon_ch1_recalc_rate(struct clk_hw *hw,
180 					  unsigned long parent_rate)
181 {
182 	struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
183 	u32 reg;
184 
185 	reg = readl(tclk->reg);
186 
187 	parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1;
188 
189 	if (reg & TCON_CH1_SCLK1_HALF_BIT)
190 		parent_rate /= 2;
191 
192 	return parent_rate;
193 }
194 
195 static int tcon_ch1_set_rate(struct clk_hw *hw, unsigned long rate,
196 			     unsigned long parent_rate)
197 {
198 	struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
199 	unsigned long flags;
200 	bool half;
201 	u8 div_m;
202 	u32 reg;
203 
204 	tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half);
205 
206 	spin_lock_irqsave(&tclk->lock, flags);
207 	reg = readl(tclk->reg);
208 	reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT);
209 	reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;
210 
211 	if (half)
212 		reg |= TCON_CH1_SCLK1_HALF_BIT;
213 
214 	writel(reg, tclk->reg);
215 	spin_unlock_irqrestore(&tclk->lock, flags);
216 
217 	return 0;
218 }
219 
220 static const struct clk_ops tcon_ch1_ops = {
221 	.disable	= tcon_ch1_disable,
222 	.enable		= tcon_ch1_enable,
223 	.is_enabled	= tcon_ch1_is_enabled,
224 
225 	.get_parent	= tcon_ch1_get_parent,
226 	.set_parent	= tcon_ch1_set_parent,
227 
228 	.determine_rate	= tcon_ch1_determine_rate,
229 	.recalc_rate	= tcon_ch1_recalc_rate,
230 	.set_rate	= tcon_ch1_set_rate,
231 };
232 
233 static void __init tcon_ch1_setup(struct device_node *node)
234 {
235 	const char *parents[TCON_CH1_SCLK2_PARENTS];
236 	const char *clk_name = node->name;
237 	struct clk_init_data init;
238 	struct tcon_ch1_clk *tclk;
239 	struct resource res;
240 	struct clk *clk;
241 	void __iomem *reg;
242 	int ret;
243 
244 	of_property_read_string(node, "clock-output-names", &clk_name);
245 
246 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
247 	if (IS_ERR(reg)) {
248 		pr_err("%s: Could not map the clock registers\n", clk_name);
249 		return;
250 	}
251 
252 	ret = of_clk_parent_fill(node, parents, TCON_CH1_SCLK2_PARENTS);
253 	if (ret != TCON_CH1_SCLK2_PARENTS) {
254 		pr_err("%s Could not retrieve the parents\n", clk_name);
255 		goto err_unmap;
256 	}
257 
258 	tclk = kzalloc(sizeof(*tclk), GFP_KERNEL);
259 	if (!tclk)
260 		goto err_unmap;
261 
262 	init.name = clk_name;
263 	init.ops = &tcon_ch1_ops;
264 	init.parent_names = parents;
265 	init.num_parents = TCON_CH1_SCLK2_PARENTS;
266 	init.flags = CLK_SET_RATE_PARENT;
267 
268 	tclk->reg = reg;
269 	tclk->hw.init = &init;
270 	spin_lock_init(&tclk->lock);
271 
272 	clk = clk_register(NULL, &tclk->hw);
273 	if (IS_ERR(clk)) {
274 		pr_err("%s: Couldn't register the clock\n", clk_name);
275 		goto err_free_data;
276 	}
277 
278 	ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
279 	if (ret) {
280 		pr_err("%s: Couldn't register our clock provider\n", clk_name);
281 		goto err_unregister_clk;
282 	}
283 
284 	return;
285 
286 err_unregister_clk:
287 	clk_unregister(clk);
288 err_free_data:
289 	kfree(tclk);
290 err_unmap:
291 	iounmap(reg);
292 	of_address_to_resource(node, 0, &res);
293 	release_mem_region(res.start, resource_size(&res));
294 }
295 
296 CLK_OF_DECLARE(tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",
297 	       tcon_ch1_setup);
298