1 /* 2 * Copyright (C) 2013 Emilio López <emilio@elopez.com.ar> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Adjustable factor-based clock implementation 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/of_address.h> 16 #include <linux/slab.h> 17 #include <linux/string.h> 18 19 #include "clk-factors.h" 20 21 /* 22 * DOC: basic adjustable factor-based clock 23 * 24 * Traits of this clock: 25 * prepare - clk_prepare only ensures that parents are prepared 26 * enable - clk_enable only ensures that parents are enabled 27 * rate - rate is adjustable. 28 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1) 29 * parent - fixed parent. No clk_set_parent support 30 */ 31 32 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) 33 34 #define FACTORS_MAX_PARENTS 5 35 36 #define SETMASK(len, pos) (((1U << (len)) - 1) << (pos)) 37 #define CLRMASK(len, pos) (~(SETMASK(len, pos))) 38 #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) 39 40 #define FACTOR_SET(bit, len, reg, val) \ 41 (((reg) & CLRMASK(len, bit)) | (val << (bit))) 42 43 static unsigned long clk_factors_recalc_rate(struct clk_hw *hw, 44 unsigned long parent_rate) 45 { 46 u8 n = 1, k = 0, p = 0, m = 0; 47 u32 reg; 48 unsigned long rate; 49 struct clk_factors *factors = to_clk_factors(hw); 50 const struct clk_factors_config *config = factors->config; 51 52 /* Fetch the register value */ 53 reg = readl(factors->reg); 54 55 /* Get each individual factor if applicable */ 56 if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE) 57 n = FACTOR_GET(config->nshift, config->nwidth, reg); 58 if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE) 59 k = FACTOR_GET(config->kshift, config->kwidth, reg); 60 if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE) 61 m = FACTOR_GET(config->mshift, config->mwidth, reg); 62 if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE) 63 p = FACTOR_GET(config->pshift, config->pwidth, reg); 64 65 if (factors->recalc) { 66 struct factors_request factors_req = { 67 .parent_rate = parent_rate, 68 .n = n, 69 .k = k, 70 .m = m, 71 .p = p, 72 }; 73 74 /* get mux details from mux clk structure */ 75 if (factors->mux) 76 factors_req.parent_index = 77 (reg >> factors->mux->shift) & 78 factors->mux->mask; 79 80 factors->recalc(&factors_req); 81 82 return factors_req.rate; 83 } 84 85 /* Calculate the rate */ 86 rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1); 87 88 return rate; 89 } 90 91 static int clk_factors_determine_rate(struct clk_hw *hw, 92 struct clk_rate_request *req) 93 { 94 struct clk_factors *factors = to_clk_factors(hw); 95 struct clk_hw *parent, *best_parent = NULL; 96 int i, num_parents; 97 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; 98 99 /* find the parent that can help provide the fastest rate <= rate */ 100 num_parents = clk_hw_get_num_parents(hw); 101 for (i = 0; i < num_parents; i++) { 102 struct factors_request factors_req = { 103 .rate = req->rate, 104 .parent_index = i, 105 }; 106 parent = clk_hw_get_parent_by_index(hw, i); 107 if (!parent) 108 continue; 109 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 110 parent_rate = clk_hw_round_rate(parent, req->rate); 111 else 112 parent_rate = clk_hw_get_rate(parent); 113 114 factors_req.parent_rate = parent_rate; 115 factors->get_factors(&factors_req); 116 child_rate = factors_req.rate; 117 118 if (child_rate <= req->rate && child_rate > best_child_rate) { 119 best_parent = parent; 120 best = parent_rate; 121 best_child_rate = child_rate; 122 } 123 } 124 125 if (!best_parent) 126 return -EINVAL; 127 128 req->best_parent_hw = best_parent; 129 req->best_parent_rate = best; 130 req->rate = best_child_rate; 131 132 return 0; 133 } 134 135 static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate, 136 unsigned long parent_rate) 137 { 138 struct factors_request req = { 139 .rate = rate, 140 .parent_rate = parent_rate, 141 }; 142 u32 reg; 143 struct clk_factors *factors = to_clk_factors(hw); 144 const struct clk_factors_config *config = factors->config; 145 unsigned long flags = 0; 146 147 factors->get_factors(&req); 148 149 if (factors->lock) 150 spin_lock_irqsave(factors->lock, flags); 151 152 /* Fetch the register value */ 153 reg = readl(factors->reg); 154 155 /* Set up the new factors - macros do not do anything if width is 0 */ 156 reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n); 157 reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k); 158 reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m); 159 reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p); 160 161 /* Apply them now */ 162 writel(reg, factors->reg); 163 164 /* delay 500us so pll stabilizes */ 165 __delay((rate >> 20) * 500 / 2); 166 167 if (factors->lock) 168 spin_unlock_irqrestore(factors->lock, flags); 169 170 return 0; 171 } 172 173 static const struct clk_ops clk_factors_ops = { 174 .determine_rate = clk_factors_determine_rate, 175 .recalc_rate = clk_factors_recalc_rate, 176 .set_rate = clk_factors_set_rate, 177 }; 178 179 struct clk *sunxi_factors_register(struct device_node *node, 180 const struct factors_data *data, 181 spinlock_t *lock, 182 void __iomem *reg) 183 { 184 struct clk *clk; 185 struct clk_factors *factors; 186 struct clk_gate *gate = NULL; 187 struct clk_mux *mux = NULL; 188 struct clk_hw *gate_hw = NULL; 189 struct clk_hw *mux_hw = NULL; 190 const char *clk_name = node->name; 191 const char *parents[FACTORS_MAX_PARENTS]; 192 int ret, i = 0; 193 194 /* if we have a mux, we will have >1 parents */ 195 i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS); 196 197 /* 198 * some factor clocks, such as pll5 and pll6, may have multiple 199 * outputs, and have their name designated in factors_data 200 */ 201 if (data->name) 202 clk_name = data->name; 203 else 204 of_property_read_string(node, "clock-output-names", &clk_name); 205 206 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); 207 if (!factors) 208 goto err_factors; 209 210 /* set up factors properties */ 211 factors->reg = reg; 212 factors->config = data->table; 213 factors->get_factors = data->getter; 214 factors->recalc = data->recalc; 215 factors->lock = lock; 216 217 /* Add a gate if this factor clock can be gated */ 218 if (data->enable) { 219 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 220 if (!gate) 221 goto err_gate; 222 223 factors->gate = gate; 224 225 /* set up gate properties */ 226 gate->reg = reg; 227 gate->bit_idx = data->enable; 228 gate->lock = factors->lock; 229 gate_hw = &gate->hw; 230 } 231 232 /* Add a mux if this factor clock can be muxed */ 233 if (data->mux) { 234 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); 235 if (!mux) 236 goto err_mux; 237 238 factors->mux = mux; 239 240 /* set up gate properties */ 241 mux->reg = reg; 242 mux->shift = data->mux; 243 mux->mask = data->muxmask; 244 mux->lock = factors->lock; 245 mux_hw = &mux->hw; 246 } 247 248 clk = clk_register_composite(NULL, clk_name, 249 parents, i, 250 mux_hw, &clk_mux_ops, 251 &factors->hw, &clk_factors_ops, 252 gate_hw, &clk_gate_ops, 0); 253 if (IS_ERR(clk)) 254 goto err_register; 255 256 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 257 if (ret) 258 goto err_provider; 259 260 return clk; 261 262 err_provider: 263 /* TODO: The composite clock stuff will leak a bit here. */ 264 clk_unregister(clk); 265 err_register: 266 kfree(mux); 267 err_mux: 268 kfree(gate); 269 err_gate: 270 kfree(factors); 271 err_factors: 272 return NULL; 273 } 274 275 void sunxi_factors_unregister(struct device_node *node, struct clk *clk) 276 { 277 struct clk_hw *hw = __clk_get_hw(clk); 278 struct clk_factors *factors; 279 280 if (!hw) 281 return; 282 283 factors = to_clk_factors(hw); 284 285 of_clk_del_provider(node); 286 /* TODO: The composite clock stuff will leak a bit here. */ 287 clk_unregister(clk); 288 kfree(factors->mux); 289 kfree(factors->gate); 290 kfree(factors); 291 } 292