1 /* 2 * Copyright 2013 Emilio López 3 * Emilio López <emilio@elopez.com.ar> 4 * 5 * Copyright 2015 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/clk-provider.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/slab.h> 24 25 #include <dt-bindings/clock/sun4i-a10-pll2.h> 26 27 #define SUN4I_PLL2_ENABLE 31 28 29 #define SUN4I_PLL2_PRE_DIV_SHIFT 0 30 #define SUN4I_PLL2_PRE_DIV_WIDTH 5 31 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0) 32 33 #define SUN4I_PLL2_N_SHIFT 8 34 #define SUN4I_PLL2_N_WIDTH 7 35 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0) 36 37 #define SUN4I_PLL2_POST_DIV_SHIFT 26 38 #define SUN4I_PLL2_POST_DIV_WIDTH 4 39 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0) 40 41 #define SUN4I_PLL2_POST_DIV_VALUE 4 42 43 #define SUN4I_PLL2_OUTPUTS 4 44 45 static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); 46 47 static void __init sun4i_pll2_setup(struct device_node *node, 48 int post_div_offset) 49 { 50 const char *clk_name = node->name, *parent; 51 struct clk **clks, *base_clk, *prediv_clk; 52 struct clk_onecell_data *clk_data; 53 struct clk_multiplier *mult; 54 struct clk_gate *gate; 55 void __iomem *reg; 56 u32 val; 57 58 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 59 if (IS_ERR(reg)) 60 return; 61 62 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 63 if (!clk_data) 64 goto err_unmap; 65 66 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); 67 if (!clks) 68 goto err_free_data; 69 70 parent = of_clk_get_parent_name(node, 0); 71 prediv_clk = clk_register_divider(NULL, "pll2-prediv", 72 parent, 0, reg, 73 SUN4I_PLL2_PRE_DIV_SHIFT, 74 SUN4I_PLL2_PRE_DIV_WIDTH, 75 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 76 &sun4i_a10_pll2_lock); 77 if (IS_ERR(prediv_clk)) { 78 pr_err("Couldn't register the prediv clock\n"); 79 goto err_free_array; 80 } 81 82 /* Setup the gate part of the PLL2 */ 83 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 84 if (!gate) 85 goto err_unregister_prediv; 86 87 gate->reg = reg; 88 gate->bit_idx = SUN4I_PLL2_ENABLE; 89 gate->lock = &sun4i_a10_pll2_lock; 90 91 /* Setup the multiplier part of the PLL2 */ 92 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); 93 if (!mult) 94 goto err_free_gate; 95 96 mult->reg = reg; 97 mult->shift = SUN4I_PLL2_N_SHIFT; 98 mult->width = 7; 99 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | 100 CLK_MULTIPLIER_ROUND_CLOSEST; 101 mult->lock = &sun4i_a10_pll2_lock; 102 103 parent = __clk_get_name(prediv_clk); 104 base_clk = clk_register_composite(NULL, "pll2-base", 105 &parent, 1, 106 NULL, NULL, 107 &mult->hw, &clk_multiplier_ops, 108 &gate->hw, &clk_gate_ops, 109 CLK_SET_RATE_PARENT); 110 if (IS_ERR(base_clk)) { 111 pr_err("Couldn't register the base multiplier clock\n"); 112 goto err_free_multiplier; 113 } 114 115 parent = __clk_get_name(base_clk); 116 117 /* 118 * PLL2-1x 119 * 120 * This is supposed to have a post divider, but we won't need 121 * to use it, we just need to initialise it to 4, and use a 122 * fixed divider. 123 */ 124 val = readl(reg); 125 val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); 126 val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; 127 writel(val, reg); 128 129 of_property_read_string_index(node, "clock-output-names", 130 SUN4I_A10_PLL2_1X, &clk_name); 131 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, 132 parent, 133 CLK_SET_RATE_PARENT, 134 1, 135 SUN4I_PLL2_POST_DIV_VALUE); 136 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X])); 137 138 /* 139 * PLL2-2x 140 * 141 * This clock doesn't use the post divider, and really is just 142 * a fixed divider from the PLL2 base clock. 143 */ 144 of_property_read_string_index(node, "clock-output-names", 145 SUN4I_A10_PLL2_2X, &clk_name); 146 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, 147 parent, 148 CLK_SET_RATE_PARENT, 149 1, 2); 150 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X])); 151 152 /* PLL2-4x */ 153 of_property_read_string_index(node, "clock-output-names", 154 SUN4I_A10_PLL2_4X, &clk_name); 155 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, 156 parent, 157 CLK_SET_RATE_PARENT, 158 1, 1); 159 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X])); 160 161 /* PLL2-8x */ 162 of_property_read_string_index(node, "clock-output-names", 163 SUN4I_A10_PLL2_8X, &clk_name); 164 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, 165 parent, 166 CLK_SET_RATE_PARENT, 167 2, 1); 168 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X])); 169 170 clk_data->clks = clks; 171 clk_data->clk_num = SUN4I_PLL2_OUTPUTS; 172 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 173 174 return; 175 176 err_free_multiplier: 177 kfree(mult); 178 err_free_gate: 179 kfree(gate); 180 err_unregister_prediv: 181 clk_unregister_divider(prediv_clk); 182 err_free_array: 183 kfree(clks); 184 err_free_data: 185 kfree(clk_data); 186 err_unmap: 187 iounmap(reg); 188 } 189 190 static void __init sun4i_a10_pll2_setup(struct device_node *node) 191 { 192 sun4i_pll2_setup(node, 0); 193 } 194 195 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk", 196 sun4i_a10_pll2_setup); 197 198 static void __init sun5i_a13_pll2_setup(struct device_node *node) 199 { 200 sun4i_pll2_setup(node, 1); 201 } 202 203 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk", 204 sun5i_a13_pll2_setup); 205