1 /* 2 * Copyright 2013 Emilio López 3 * Emilio López <emilio@elopez.com.ar> 4 * 5 * Copyright 2015 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/clk-provider.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/slab.h> 23 24 #include <dt-bindings/clock/sun4i-a10-pll2.h> 25 26 #define SUN4I_PLL2_ENABLE 31 27 28 #define SUN4I_PLL2_PRE_DIV_SHIFT 0 29 #define SUN4I_PLL2_PRE_DIV_WIDTH 5 30 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0) 31 32 #define SUN4I_PLL2_N_SHIFT 8 33 #define SUN4I_PLL2_N_WIDTH 7 34 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0) 35 36 #define SUN4I_PLL2_POST_DIV_SHIFT 26 37 #define SUN4I_PLL2_POST_DIV_WIDTH 4 38 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0) 39 40 #define SUN4I_PLL2_POST_DIV_VALUE 4 41 42 #define SUN4I_PLL2_OUTPUTS 4 43 44 static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); 45 46 static void __init sun4i_pll2_setup(struct device_node *node) 47 { 48 const char *clk_name = node->name, *parent; 49 struct clk **clks, *base_clk, *prediv_clk; 50 struct clk_onecell_data *clk_data; 51 struct clk_multiplier *mult; 52 struct clk_gate *gate; 53 void __iomem *reg; 54 u32 val; 55 56 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 57 if (IS_ERR(reg)) 58 return; 59 60 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 61 if (!clk_data) 62 goto err_unmap; 63 64 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); 65 if (!clks) 66 goto err_free_data; 67 68 parent = of_clk_get_parent_name(node, 0); 69 prediv_clk = clk_register_divider(NULL, "pll2-prediv", 70 parent, 0, reg, 71 SUN4I_PLL2_PRE_DIV_SHIFT, 72 SUN4I_PLL2_PRE_DIV_WIDTH, 73 CLK_DIVIDER_ONE_BASED | 74 CLK_DIVIDER_ALLOW_ZERO, 75 &sun4i_a10_pll2_lock); 76 if (!prediv_clk) { 77 pr_err("Couldn't register the prediv clock\n"); 78 goto err_free_array; 79 } 80 81 /* Setup the gate part of the PLL2 */ 82 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 83 if (!gate) 84 goto err_unregister_prediv; 85 86 gate->reg = reg; 87 gate->bit_idx = SUN4I_PLL2_ENABLE; 88 gate->lock = &sun4i_a10_pll2_lock; 89 90 /* Setup the multiplier part of the PLL2 */ 91 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); 92 if (!mult) 93 goto err_free_gate; 94 95 mult->reg = reg; 96 mult->shift = SUN4I_PLL2_N_SHIFT; 97 mult->width = 7; 98 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | 99 CLK_MULTIPLIER_ROUND_CLOSEST; 100 mult->lock = &sun4i_a10_pll2_lock; 101 102 parent = __clk_get_name(prediv_clk); 103 base_clk = clk_register_composite(NULL, "pll2-base", 104 &parent, 1, 105 NULL, NULL, 106 &mult->hw, &clk_multiplier_ops, 107 &gate->hw, &clk_gate_ops, 108 CLK_SET_RATE_PARENT); 109 if (!base_clk) { 110 pr_err("Couldn't register the base multiplier clock\n"); 111 goto err_free_multiplier; 112 } 113 114 parent = __clk_get_name(base_clk); 115 116 /* 117 * PLL2-1x 118 * 119 * This is supposed to have a post divider, but we won't need 120 * to use it, we just need to initialise it to 4, and use a 121 * fixed divider. 122 */ 123 val = readl(reg); 124 val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); 125 val |= SUN4I_PLL2_POST_DIV_VALUE << SUN4I_PLL2_POST_DIV_SHIFT; 126 writel(val, reg); 127 128 of_property_read_string_index(node, "clock-output-names", 129 SUN4I_A10_PLL2_1X, &clk_name); 130 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, 131 parent, 132 CLK_SET_RATE_PARENT, 133 1, 134 SUN4I_PLL2_POST_DIV_VALUE); 135 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X])); 136 137 /* 138 * PLL2-2x 139 * 140 * This clock doesn't use the post divider, and really is just 141 * a fixed divider from the PLL2 base clock. 142 */ 143 of_property_read_string_index(node, "clock-output-names", 144 SUN4I_A10_PLL2_2X, &clk_name); 145 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, 146 parent, 147 CLK_SET_RATE_PARENT, 148 1, 2); 149 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X])); 150 151 /* PLL2-4x */ 152 of_property_read_string_index(node, "clock-output-names", 153 SUN4I_A10_PLL2_4X, &clk_name); 154 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, 155 parent, 156 CLK_SET_RATE_PARENT, 157 1, 1); 158 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X])); 159 160 /* PLL2-8x */ 161 of_property_read_string_index(node, "clock-output-names", 162 SUN4I_A10_PLL2_8X, &clk_name); 163 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, 164 parent, 165 CLK_SET_RATE_PARENT, 166 2, 1); 167 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X])); 168 169 clk_data->clks = clks; 170 clk_data->clk_num = SUN4I_PLL2_OUTPUTS; 171 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 172 173 return; 174 175 err_free_multiplier: 176 kfree(mult); 177 err_free_gate: 178 kfree(gate); 179 err_unregister_prediv: 180 clk_unregister_divider(prediv_clk); 181 err_free_array: 182 kfree(clks); 183 err_free_data: 184 kfree(clk_data); 185 err_unmap: 186 iounmap(reg); 187 } 188 CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-pll2-clk", sun4i_pll2_setup); 189