1 /* 2 * Copyright (c) 2016 Maxime Ripard. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _CCU_NM_H_ 15 #define _CCU_NM_H_ 16 17 #include <linux/clk-provider.h> 18 19 #include "ccu_common.h" 20 #include "ccu_div.h" 21 #include "ccu_frac.h" 22 #include "ccu_mult.h" 23 #include "ccu_sdm.h" 24 25 /* 26 * struct ccu_nm - Definition of an N-M clock 27 * 28 * Clocks based on the formula parent * N / M 29 */ 30 struct ccu_nm { 31 u32 enable; 32 u32 lock; 33 34 struct ccu_mult_internal n; 35 struct ccu_div_internal m; 36 struct ccu_frac_internal frac; 37 struct ccu_sdm_internal sdm; 38 39 unsigned int fixed_post_div; 40 41 struct ccu_common common; 42 }; 43 44 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ 45 _nshift, _nwidth, \ 46 _mshift, _mwidth, \ 47 _sdm_table, _sdm_en, \ 48 _sdm_reg, _sdm_reg_en, \ 49 _gate, _lock, _flags) \ 50 struct ccu_nm _struct = { \ 51 .enable = _gate, \ 52 .lock = _lock, \ 53 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ 54 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ 55 .sdm = _SUNXI_CCU_SDM(_sdm_table, _sdm_en, \ 56 _sdm_reg, _sdm_reg_en),\ 57 .common = { \ 58 .reg = _reg, \ 59 .features = CCU_FEATURE_SIGMA_DELTA_MOD, \ 60 .hw.init = CLK_HW_INIT(_name, \ 61 _parent, \ 62 &ccu_nm_ops, \ 63 _flags), \ 64 }, \ 65 } 66 67 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ 68 _nshift, _nwidth, \ 69 _mshift, _mwidth, \ 70 _frac_en, _frac_sel, \ 71 _frac_rate_0, _frac_rate_1, \ 72 _gate, _lock, _flags) \ 73 struct ccu_nm _struct = { \ 74 .enable = _gate, \ 75 .lock = _lock, \ 76 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ 77 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ 78 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \ 79 _frac_rate_0, \ 80 _frac_rate_1), \ 81 .common = { \ 82 .reg = _reg, \ 83 .features = CCU_FEATURE_FRACTIONAL, \ 84 .hw.init = CLK_HW_INIT(_name, \ 85 _parent, \ 86 &ccu_nm_ops, \ 87 _flags), \ 88 }, \ 89 } 90 91 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ 92 _nshift, _nwidth, \ 93 _mshift, _mwidth, \ 94 _gate, _lock, _flags) \ 95 struct ccu_nm _struct = { \ 96 .enable = _gate, \ 97 .lock = _lock, \ 98 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ 99 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ 100 .common = { \ 101 .reg = _reg, \ 102 .hw.init = CLK_HW_INIT(_name, \ 103 _parent, \ 104 &ccu_nm_ops, \ 105 _flags), \ 106 }, \ 107 } 108 109 static inline struct ccu_nm *hw_to_ccu_nm(struct clk_hw *hw) 110 { 111 struct ccu_common *common = hw_to_ccu_common(hw); 112 113 return container_of(common, struct ccu_nm, common); 114 } 115 116 extern const struct clk_ops ccu_nm_ops; 117 118 #endif /* _CCU_NM_H_ */ 119