1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 */ 10 11 #include <linux/clk-provider.h> 12 13 #include "ccu_frac.h" 14 #include "ccu_gate.h" 15 #include "ccu_nm.h" 16 17 struct _ccu_nm { 18 unsigned long n, min_n, max_n; 19 unsigned long m, min_m, max_m; 20 }; 21 22 static void ccu_nm_find_best(unsigned long parent, unsigned long rate, 23 struct _ccu_nm *nm) 24 { 25 unsigned long best_rate = 0; 26 unsigned long best_n = 0, best_m = 0; 27 unsigned long _n, _m; 28 29 for (_n = nm->min_n; _n <= nm->max_n; _n++) { 30 for (_m = nm->min_m; _m <= nm->max_m; _m++) { 31 unsigned long tmp_rate = parent * _n / _m; 32 33 if (tmp_rate > rate) 34 continue; 35 36 if ((rate - tmp_rate) < (rate - best_rate)) { 37 best_rate = tmp_rate; 38 best_n = _n; 39 best_m = _m; 40 } 41 } 42 } 43 44 nm->n = best_n; 45 nm->m = best_m; 46 } 47 48 static void ccu_nm_disable(struct clk_hw *hw) 49 { 50 struct ccu_nm *nm = hw_to_ccu_nm(hw); 51 52 return ccu_gate_helper_disable(&nm->common, nm->enable); 53 } 54 55 static int ccu_nm_enable(struct clk_hw *hw) 56 { 57 struct ccu_nm *nm = hw_to_ccu_nm(hw); 58 59 return ccu_gate_helper_enable(&nm->common, nm->enable); 60 } 61 62 static int ccu_nm_is_enabled(struct clk_hw *hw) 63 { 64 struct ccu_nm *nm = hw_to_ccu_nm(hw); 65 66 return ccu_gate_helper_is_enabled(&nm->common, nm->enable); 67 } 68 69 static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw, 70 unsigned long parent_rate) 71 { 72 struct ccu_nm *nm = hw_to_ccu_nm(hw); 73 unsigned long rate; 74 unsigned long n, m; 75 u32 reg; 76 77 if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac)) { 78 rate = ccu_frac_helper_read_rate(&nm->common, &nm->frac); 79 80 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 81 rate /= nm->fixed_post_div; 82 83 return rate; 84 } 85 86 reg = readl(nm->common.base + nm->common.reg); 87 88 n = reg >> nm->n.shift; 89 n &= (1 << nm->n.width) - 1; 90 n += nm->n.offset; 91 if (!n) 92 n++; 93 94 m = reg >> nm->m.shift; 95 m &= (1 << nm->m.width) - 1; 96 m += nm->m.offset; 97 if (!m) 98 m++; 99 100 if (ccu_sdm_helper_is_enabled(&nm->common, &nm->sdm)) 101 rate = ccu_sdm_helper_read_rate(&nm->common, &nm->sdm, m, n); 102 else 103 rate = parent_rate * n / m; 104 105 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 106 rate /= nm->fixed_post_div; 107 108 return rate; 109 } 110 111 static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, 112 unsigned long *parent_rate) 113 { 114 struct ccu_nm *nm = hw_to_ccu_nm(hw); 115 struct _ccu_nm _nm; 116 117 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 118 rate *= nm->fixed_post_div; 119 120 if (rate < nm->min_rate) { 121 rate = nm->min_rate; 122 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 123 rate /= nm->fixed_post_div; 124 return rate; 125 } 126 127 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { 128 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 129 rate /= nm->fixed_post_div; 130 return rate; 131 } 132 133 if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) { 134 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 135 rate /= nm->fixed_post_div; 136 return rate; 137 } 138 139 _nm.min_n = nm->n.min ?: 1; 140 _nm.max_n = nm->n.max ?: 1 << nm->n.width; 141 _nm.min_m = 1; 142 _nm.max_m = nm->m.max ?: 1 << nm->m.width; 143 144 ccu_nm_find_best(*parent_rate, rate, &_nm); 145 rate = *parent_rate * _nm.n / _nm.m; 146 147 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 148 rate /= nm->fixed_post_div; 149 150 return rate; 151 } 152 153 static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, 154 unsigned long parent_rate) 155 { 156 struct ccu_nm *nm = hw_to_ccu_nm(hw); 157 struct _ccu_nm _nm; 158 unsigned long flags; 159 u32 reg; 160 161 /* Adjust target rate according to post-dividers */ 162 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 163 rate = rate * nm->fixed_post_div; 164 165 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { 166 spin_lock_irqsave(nm->common.lock, flags); 167 168 /* most SoCs require M to be 0 if fractional mode is used */ 169 reg = readl(nm->common.base + nm->common.reg); 170 reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); 171 writel(reg, nm->common.base + nm->common.reg); 172 173 spin_unlock_irqrestore(nm->common.lock, flags); 174 175 ccu_frac_helper_enable(&nm->common, &nm->frac); 176 177 return ccu_frac_helper_set_rate(&nm->common, &nm->frac, 178 rate, nm->lock); 179 } else { 180 ccu_frac_helper_disable(&nm->common, &nm->frac); 181 } 182 183 _nm.min_n = nm->n.min ?: 1; 184 _nm.max_n = nm->n.max ?: 1 << nm->n.width; 185 _nm.min_m = 1; 186 _nm.max_m = nm->m.max ?: 1 << nm->m.width; 187 188 if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) { 189 ccu_sdm_helper_enable(&nm->common, &nm->sdm, rate); 190 191 /* Sigma delta modulation requires specific N and M factors */ 192 ccu_sdm_helper_get_factors(&nm->common, &nm->sdm, rate, 193 &_nm.m, &_nm.n); 194 } else { 195 ccu_sdm_helper_disable(&nm->common, &nm->sdm); 196 ccu_nm_find_best(parent_rate, rate, &_nm); 197 } 198 199 spin_lock_irqsave(nm->common.lock, flags); 200 201 reg = readl(nm->common.base + nm->common.reg); 202 reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); 203 reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); 204 205 reg |= (_nm.n - nm->n.offset) << nm->n.shift; 206 reg |= (_nm.m - nm->m.offset) << nm->m.shift; 207 writel(reg, nm->common.base + nm->common.reg); 208 209 spin_unlock_irqrestore(nm->common.lock, flags); 210 211 ccu_helper_wait_for_lock(&nm->common, nm->lock); 212 213 return 0; 214 } 215 216 const struct clk_ops ccu_nm_ops = { 217 .disable = ccu_nm_disable, 218 .enable = ccu_nm_enable, 219 .is_enabled = ccu_nm_is_enabled, 220 221 .recalc_rate = ccu_nm_recalc_rate, 222 .round_rate = ccu_nm_round_rate, 223 .set_rate = ccu_nm_set_rate, 224 }; 225