1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 12 #include "ccu_gate.h" 13 #include "ccu_mux.h" 14 15 static u16 ccu_mux_get_prediv(struct ccu_common *common, 16 struct ccu_mux_internal *cm, 17 int parent_index) 18 { 19 u16 prediv = 1; 20 u32 reg; 21 22 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || 23 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || 24 (common->features & CCU_FEATURE_ALL_PREDIV))) 25 return 1; 26 27 if (common->features & CCU_FEATURE_ALL_PREDIV) 28 return common->prediv; 29 30 reg = readl(common->base + common->reg); 31 if (parent_index < 0) { 32 parent_index = reg >> cm->shift; 33 parent_index &= (1 << cm->width) - 1; 34 } 35 36 if (common->features & CCU_FEATURE_FIXED_PREDIV) { 37 int i; 38 39 for (i = 0; i < cm->n_predivs; i++) 40 if (parent_index == cm->fixed_predivs[i].index) 41 prediv = cm->fixed_predivs[i].div; 42 } 43 44 if (common->features & CCU_FEATURE_VARIABLE_PREDIV) { 45 int i; 46 47 for (i = 0; i < cm->n_var_predivs; i++) 48 if (parent_index == cm->var_predivs[i].index) { 49 u8 div; 50 51 div = reg >> cm->var_predivs[i].shift; 52 div &= (1 << cm->var_predivs[i].width) - 1; 53 prediv = div + 1; 54 } 55 } 56 57 return prediv; 58 } 59 60 unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common, 61 struct ccu_mux_internal *cm, 62 int parent_index, 63 unsigned long parent_rate) 64 { 65 return parent_rate / ccu_mux_get_prediv(common, cm, parent_index); 66 } 67 68 static unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common, 69 struct ccu_mux_internal *cm, 70 int parent_index, 71 unsigned long parent_rate) 72 { 73 return parent_rate * ccu_mux_get_prediv(common, cm, parent_index); 74 } 75 76 int ccu_mux_helper_determine_rate(struct ccu_common *common, 77 struct ccu_mux_internal *cm, 78 struct clk_rate_request *req, 79 unsigned long (*round)(struct ccu_mux_internal *, 80 struct clk_hw *, 81 unsigned long *, 82 unsigned long, 83 void *), 84 void *data) 85 { 86 unsigned long best_parent_rate = 0, best_rate = 0; 87 struct clk_hw *best_parent, *hw = &common->hw; 88 unsigned int i; 89 90 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { 91 unsigned long adj_parent_rate; 92 93 best_parent = clk_hw_get_parent(hw); 94 best_parent_rate = clk_hw_get_rate(best_parent); 95 adj_parent_rate = ccu_mux_helper_apply_prediv(common, cm, -1, 96 best_parent_rate); 97 98 best_rate = round(cm, best_parent, &adj_parent_rate, 99 req->rate, data); 100 101 /* 102 * adj_parent_rate might have been modified by our clock. 103 * Unapply the pre-divider if there's one, and give 104 * the actual frequency the parent needs to run at. 105 */ 106 best_parent_rate = ccu_mux_helper_unapply_prediv(common, cm, -1, 107 adj_parent_rate); 108 109 goto out; 110 } 111 112 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 113 unsigned long tmp_rate, parent_rate; 114 struct clk_hw *parent; 115 116 parent = clk_hw_get_parent_by_index(hw, i); 117 if (!parent) 118 continue; 119 120 parent_rate = ccu_mux_helper_apply_prediv(common, cm, i, 121 clk_hw_get_rate(parent)); 122 123 tmp_rate = round(cm, parent, &parent_rate, req->rate, data); 124 125 /* 126 * parent_rate might have been modified by our clock. 127 * Unapply the pre-divider if there's one, and give 128 * the actual frequency the parent needs to run at. 129 */ 130 parent_rate = ccu_mux_helper_unapply_prediv(common, cm, i, 131 parent_rate); 132 if (tmp_rate == req->rate) { 133 best_parent = parent; 134 best_parent_rate = parent_rate; 135 best_rate = tmp_rate; 136 goto out; 137 } 138 139 if ((req->rate - tmp_rate) < (req->rate - best_rate)) { 140 best_rate = tmp_rate; 141 best_parent_rate = parent_rate; 142 best_parent = parent; 143 } 144 } 145 146 if (best_rate == 0) 147 return -EINVAL; 148 149 out: 150 req->best_parent_hw = best_parent; 151 req->best_parent_rate = best_parent_rate; 152 req->rate = best_rate; 153 return 0; 154 } 155 156 u8 ccu_mux_helper_get_parent(struct ccu_common *common, 157 struct ccu_mux_internal *cm) 158 { 159 u32 reg; 160 u8 parent; 161 162 reg = readl(common->base + common->reg); 163 parent = reg >> cm->shift; 164 parent &= (1 << cm->width) - 1; 165 166 if (cm->table) { 167 int num_parents = clk_hw_get_num_parents(&common->hw); 168 int i; 169 170 for (i = 0; i < num_parents; i++) 171 if (cm->table[i] == parent) 172 return i; 173 } 174 175 return parent; 176 } 177 178 int ccu_mux_helper_set_parent(struct ccu_common *common, 179 struct ccu_mux_internal *cm, 180 u8 index) 181 { 182 unsigned long flags; 183 u32 reg; 184 185 if (cm->table) 186 index = cm->table[index]; 187 188 spin_lock_irqsave(common->lock, flags); 189 190 reg = readl(common->base + common->reg); 191 reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift); 192 writel(reg | (index << cm->shift), common->base + common->reg); 193 194 spin_unlock_irqrestore(common->lock, flags); 195 196 return 0; 197 } 198 199 static void ccu_mux_disable(struct clk_hw *hw) 200 { 201 struct ccu_mux *cm = hw_to_ccu_mux(hw); 202 203 return ccu_gate_helper_disable(&cm->common, cm->enable); 204 } 205 206 static int ccu_mux_enable(struct clk_hw *hw) 207 { 208 struct ccu_mux *cm = hw_to_ccu_mux(hw); 209 210 return ccu_gate_helper_enable(&cm->common, cm->enable); 211 } 212 213 static int ccu_mux_is_enabled(struct clk_hw *hw) 214 { 215 struct ccu_mux *cm = hw_to_ccu_mux(hw); 216 217 return ccu_gate_helper_is_enabled(&cm->common, cm->enable); 218 } 219 220 static u8 ccu_mux_get_parent(struct clk_hw *hw) 221 { 222 struct ccu_mux *cm = hw_to_ccu_mux(hw); 223 224 return ccu_mux_helper_get_parent(&cm->common, &cm->mux); 225 } 226 227 static int ccu_mux_set_parent(struct clk_hw *hw, u8 index) 228 { 229 struct ccu_mux *cm = hw_to_ccu_mux(hw); 230 231 return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); 232 } 233 234 static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw, 235 unsigned long parent_rate) 236 { 237 struct ccu_mux *cm = hw_to_ccu_mux(hw); 238 239 return ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1, 240 parent_rate); 241 } 242 243 const struct clk_ops ccu_mux_ops = { 244 .disable = ccu_mux_disable, 245 .enable = ccu_mux_enable, 246 .is_enabled = ccu_mux_is_enabled, 247 248 .get_parent = ccu_mux_get_parent, 249 .set_parent = ccu_mux_set_parent, 250 251 .determine_rate = __clk_mux_determine_rate, 252 .recalc_rate = ccu_mux_recalc_rate, 253 }; 254 255 /* 256 * This clock notifier is called when the frequency of the of the parent 257 * PLL clock is to be changed. The idea is to switch the parent to a 258 * stable clock, such as the main oscillator, while the PLL frequency 259 * stabilizes. 260 */ 261 static int ccu_mux_notifier_cb(struct notifier_block *nb, 262 unsigned long event, void *data) 263 { 264 struct ccu_mux_nb *mux = to_ccu_mux_nb(nb); 265 int ret = 0; 266 267 if (event == PRE_RATE_CHANGE) { 268 mux->original_index = ccu_mux_helper_get_parent(mux->common, 269 mux->cm); 270 ret = ccu_mux_helper_set_parent(mux->common, mux->cm, 271 mux->bypass_index); 272 } else if (event == POST_RATE_CHANGE) { 273 ret = ccu_mux_helper_set_parent(mux->common, mux->cm, 274 mux->original_index); 275 } 276 277 udelay(mux->delay_us); 278 279 return notifier_from_errno(ret); 280 } 281 282 int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb) 283 { 284 mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb; 285 286 return clk_notifier_register(clk, &mux_nb->clk_nb); 287 } 288