1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 */ 10 11 #include <linux/clk-provider.h> 12 13 #include "ccu_gate.h" 14 #include "ccu_mp.h" 15 16 static void ccu_mp_find_best(unsigned long parent, unsigned long rate, 17 unsigned int max_m, unsigned int max_p, 18 unsigned int *m, unsigned int *p) 19 { 20 unsigned long best_rate = 0; 21 unsigned int best_m = 0, best_p = 0; 22 unsigned int _m, _p; 23 24 for (_p = 1; _p <= max_p; _p <<= 1) { 25 for (_m = 1; _m <= max_m; _m++) { 26 unsigned long tmp_rate = parent / _p / _m; 27 28 if (tmp_rate > rate) 29 continue; 30 31 if ((rate - tmp_rate) < (rate - best_rate)) { 32 best_rate = tmp_rate; 33 best_m = _m; 34 best_p = _p; 35 } 36 } 37 } 38 39 *m = best_m; 40 *p = best_p; 41 } 42 43 static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux, 44 struct clk_hw *hw, 45 unsigned long *parent_rate, 46 unsigned long rate, 47 void *data) 48 { 49 struct ccu_mp *cmp = data; 50 unsigned int max_m, max_p; 51 unsigned int m, p; 52 53 max_m = cmp->m.max ?: 1 << cmp->m.width; 54 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); 55 56 ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); 57 58 return *parent_rate / p / m; 59 } 60 61 static void ccu_mp_disable(struct clk_hw *hw) 62 { 63 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 64 65 return ccu_gate_helper_disable(&cmp->common, cmp->enable); 66 } 67 68 static int ccu_mp_enable(struct clk_hw *hw) 69 { 70 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 71 72 return ccu_gate_helper_enable(&cmp->common, cmp->enable); 73 } 74 75 static int ccu_mp_is_enabled(struct clk_hw *hw) 76 { 77 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 78 79 return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable); 80 } 81 82 static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw, 83 unsigned long parent_rate) 84 { 85 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 86 unsigned int m, p; 87 u32 reg; 88 89 /* Adjust parent_rate according to pre-dividers */ 90 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, 91 parent_rate); 92 93 reg = readl(cmp->common.base + cmp->common.reg); 94 95 m = reg >> cmp->m.shift; 96 m &= (1 << cmp->m.width) - 1; 97 m += cmp->m.offset; 98 if (!m) 99 m++; 100 101 p = reg >> cmp->p.shift; 102 p &= (1 << cmp->p.width) - 1; 103 104 return (parent_rate >> p) / m; 105 } 106 107 static int ccu_mp_determine_rate(struct clk_hw *hw, 108 struct clk_rate_request *req) 109 { 110 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 111 112 return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux, 113 req, ccu_mp_round_rate, cmp); 114 } 115 116 static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate, 117 unsigned long parent_rate) 118 { 119 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 120 unsigned long flags; 121 unsigned int max_m, max_p; 122 unsigned int m, p; 123 u32 reg; 124 125 /* Adjust parent_rate according to pre-dividers */ 126 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, 127 parent_rate); 128 129 max_m = cmp->m.max ?: 1 << cmp->m.width; 130 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); 131 132 ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p); 133 134 spin_lock_irqsave(cmp->common.lock, flags); 135 136 reg = readl(cmp->common.base + cmp->common.reg); 137 reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift); 138 reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift); 139 reg |= (m - cmp->m.offset) << cmp->m.shift; 140 reg |= ilog2(p) << cmp->p.shift; 141 142 writel(reg, cmp->common.base + cmp->common.reg); 143 144 spin_unlock_irqrestore(cmp->common.lock, flags); 145 146 return 0; 147 } 148 149 static u8 ccu_mp_get_parent(struct clk_hw *hw) 150 { 151 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 152 153 return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux); 154 } 155 156 static int ccu_mp_set_parent(struct clk_hw *hw, u8 index) 157 { 158 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 159 160 return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index); 161 } 162 163 const struct clk_ops ccu_mp_ops = { 164 .disable = ccu_mp_disable, 165 .enable = ccu_mp_enable, 166 .is_enabled = ccu_mp_is_enabled, 167 168 .get_parent = ccu_mp_get_parent, 169 .set_parent = ccu_mp_set_parent, 170 171 .determine_rate = ccu_mp_determine_rate, 172 .recalc_rate = ccu_mp_recalc_rate, 173 .set_rate = ccu_mp_set_rate, 174 }; 175 176 /* 177 * Support for MMC timing mode switching 178 * 179 * The MMC clocks on some SoCs support switching between old and 180 * new timing modes. A platform specific API is provided to query 181 * and set the timing mode on supported SoCs. 182 * 183 * In addition, a special class of ccu_mp_ops is provided, which 184 * takes in to account the timing mode switch. When the new timing 185 * mode is active, the clock output rate is halved. This new class 186 * is a wrapper around the generic ccu_mp_ops. When clock rates 187 * are passed through to ccu_mp_ops callbacks, they are doubled 188 * if the new timing mode bit is set, to account for the post 189 * divider. Conversely, when clock rates are passed back, they 190 * are halved if the mode bit is set. 191 */ 192 193 static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw, 194 unsigned long parent_rate) 195 { 196 unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate); 197 struct ccu_common *cm = hw_to_ccu_common(hw); 198 u32 val = readl(cm->base + cm->reg); 199 200 if (val & CCU_MMC_NEW_TIMING_MODE) 201 return rate / 2; 202 return rate; 203 } 204 205 static int ccu_mp_mmc_determine_rate(struct clk_hw *hw, 206 struct clk_rate_request *req) 207 { 208 struct ccu_common *cm = hw_to_ccu_common(hw); 209 u32 val = readl(cm->base + cm->reg); 210 int ret; 211 212 /* adjust the requested clock rate */ 213 if (val & CCU_MMC_NEW_TIMING_MODE) { 214 req->rate *= 2; 215 req->min_rate *= 2; 216 req->max_rate *= 2; 217 } 218 219 ret = ccu_mp_determine_rate(hw, req); 220 221 /* re-adjust the requested clock rate back */ 222 if (val & CCU_MMC_NEW_TIMING_MODE) { 223 req->rate /= 2; 224 req->min_rate /= 2; 225 req->max_rate /= 2; 226 } 227 228 return ret; 229 } 230 231 static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate, 232 unsigned long parent_rate) 233 { 234 struct ccu_common *cm = hw_to_ccu_common(hw); 235 u32 val = readl(cm->base + cm->reg); 236 237 if (val & CCU_MMC_NEW_TIMING_MODE) 238 rate *= 2; 239 240 return ccu_mp_set_rate(hw, rate, parent_rate); 241 } 242 243 const struct clk_ops ccu_mp_mmc_ops = { 244 .disable = ccu_mp_disable, 245 .enable = ccu_mp_enable, 246 .is_enabled = ccu_mp_is_enabled, 247 248 .get_parent = ccu_mp_get_parent, 249 .set_parent = ccu_mp_set_parent, 250 251 .determine_rate = ccu_mp_mmc_determine_rate, 252 .recalc_rate = ccu_mp_mmc_recalc_rate, 253 .set_rate = ccu_mp_mmc_set_rate, 254 }; 255