1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/io.h> 13 14 #include "ccu_gate.h" 15 #include "ccu_mp.h" 16 17 static void ccu_mp_find_best(unsigned long parent, unsigned long rate, 18 unsigned int max_m, unsigned int max_p, 19 unsigned int *m, unsigned int *p) 20 { 21 unsigned long best_rate = 0; 22 unsigned int best_m = 0, best_p = 0; 23 unsigned int _m, _p; 24 25 for (_p = 1; _p <= max_p; _p <<= 1) { 26 for (_m = 1; _m <= max_m; _m++) { 27 unsigned long tmp_rate = parent / _p / _m; 28 29 if (tmp_rate > rate) 30 continue; 31 32 if ((rate - tmp_rate) < (rate - best_rate)) { 33 best_rate = tmp_rate; 34 best_m = _m; 35 best_p = _p; 36 } 37 } 38 } 39 40 *m = best_m; 41 *p = best_p; 42 } 43 44 static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw, 45 unsigned long *parent, 46 unsigned long rate, 47 unsigned int max_m, 48 unsigned int max_p) 49 { 50 unsigned long parent_rate_saved; 51 unsigned long parent_rate, now; 52 unsigned long best_rate = 0; 53 unsigned int _m, _p, div; 54 unsigned long maxdiv; 55 56 parent_rate_saved = *parent; 57 58 /* 59 * The maximum divider we can use without overflowing 60 * unsigned long in rate * m * p below 61 */ 62 maxdiv = max_m * max_p; 63 maxdiv = min(ULONG_MAX / rate, maxdiv); 64 65 for (_p = 1; _p <= max_p; _p <<= 1) { 66 for (_m = 1; _m <= max_m; _m++) { 67 div = _m * _p; 68 69 if (div > maxdiv) 70 break; 71 72 if (rate * div == parent_rate_saved) { 73 /* 74 * It's the most ideal case if the requested 75 * rate can be divided from parent clock without 76 * needing to change parent rate, so return the 77 * divider immediately. 78 */ 79 *parent = parent_rate_saved; 80 return rate; 81 } 82 83 parent_rate = clk_hw_round_rate(hw, rate * div); 84 now = parent_rate / div; 85 86 if (now <= rate && now > best_rate) { 87 best_rate = now; 88 *parent = parent_rate; 89 90 if (now == rate) 91 return rate; 92 } 93 } 94 } 95 96 return best_rate; 97 } 98 99 static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux, 100 struct clk_hw *hw, 101 unsigned long *parent_rate, 102 unsigned long rate, 103 void *data) 104 { 105 struct ccu_mp *cmp = data; 106 unsigned int max_m, max_p; 107 unsigned int m, p; 108 109 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 110 rate *= cmp->fixed_post_div; 111 112 max_m = cmp->m.max ?: 1 << cmp->m.width; 113 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); 114 115 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { 116 ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); 117 rate = *parent_rate / p / m; 118 } else { 119 rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate, 120 max_m, max_p); 121 } 122 123 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 124 rate /= cmp->fixed_post_div; 125 126 return rate; 127 } 128 129 static void ccu_mp_disable(struct clk_hw *hw) 130 { 131 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 132 133 return ccu_gate_helper_disable(&cmp->common, cmp->enable); 134 } 135 136 static int ccu_mp_enable(struct clk_hw *hw) 137 { 138 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 139 140 return ccu_gate_helper_enable(&cmp->common, cmp->enable); 141 } 142 143 static int ccu_mp_is_enabled(struct clk_hw *hw) 144 { 145 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 146 147 return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable); 148 } 149 150 static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw, 151 unsigned long parent_rate) 152 { 153 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 154 unsigned long rate; 155 unsigned int m, p; 156 u32 reg; 157 158 /* Adjust parent_rate according to pre-dividers */ 159 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, 160 parent_rate); 161 162 reg = readl(cmp->common.base + cmp->common.reg); 163 164 m = reg >> cmp->m.shift; 165 m &= (1 << cmp->m.width) - 1; 166 m += cmp->m.offset; 167 if (!m) 168 m++; 169 170 p = reg >> cmp->p.shift; 171 p &= (1 << cmp->p.width) - 1; 172 173 rate = (parent_rate >> p) / m; 174 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 175 rate /= cmp->fixed_post_div; 176 177 return rate; 178 } 179 180 static int ccu_mp_determine_rate(struct clk_hw *hw, 181 struct clk_rate_request *req) 182 { 183 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 184 185 return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux, 186 req, ccu_mp_round_rate, cmp); 187 } 188 189 static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate, 190 unsigned long parent_rate) 191 { 192 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 193 unsigned long flags; 194 unsigned int max_m, max_p; 195 unsigned int m, p; 196 u32 reg; 197 198 /* Adjust parent_rate according to pre-dividers */ 199 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, 200 parent_rate); 201 202 max_m = cmp->m.max ?: 1 << cmp->m.width; 203 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); 204 205 /* Adjust target rate according to post-dividers */ 206 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 207 rate = rate * cmp->fixed_post_div; 208 209 ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p); 210 211 spin_lock_irqsave(cmp->common.lock, flags); 212 213 reg = readl(cmp->common.base + cmp->common.reg); 214 reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift); 215 reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift); 216 reg |= (m - cmp->m.offset) << cmp->m.shift; 217 reg |= ilog2(p) << cmp->p.shift; 218 219 writel(reg, cmp->common.base + cmp->common.reg); 220 221 spin_unlock_irqrestore(cmp->common.lock, flags); 222 223 return 0; 224 } 225 226 static u8 ccu_mp_get_parent(struct clk_hw *hw) 227 { 228 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 229 230 return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux); 231 } 232 233 static int ccu_mp_set_parent(struct clk_hw *hw, u8 index) 234 { 235 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 236 237 return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index); 238 } 239 240 const struct clk_ops ccu_mp_ops = { 241 .disable = ccu_mp_disable, 242 .enable = ccu_mp_enable, 243 .is_enabled = ccu_mp_is_enabled, 244 245 .get_parent = ccu_mp_get_parent, 246 .set_parent = ccu_mp_set_parent, 247 248 .determine_rate = ccu_mp_determine_rate, 249 .recalc_rate = ccu_mp_recalc_rate, 250 .set_rate = ccu_mp_set_rate, 251 }; 252 253 /* 254 * Support for MMC timing mode switching 255 * 256 * The MMC clocks on some SoCs support switching between old and 257 * new timing modes. A platform specific API is provided to query 258 * and set the timing mode on supported SoCs. 259 * 260 * In addition, a special class of ccu_mp_ops is provided, which 261 * takes in to account the timing mode switch. When the new timing 262 * mode is active, the clock output rate is halved. This new class 263 * is a wrapper around the generic ccu_mp_ops. When clock rates 264 * are passed through to ccu_mp_ops callbacks, they are doubled 265 * if the new timing mode bit is set, to account for the post 266 * divider. Conversely, when clock rates are passed back, they 267 * are halved if the mode bit is set. 268 */ 269 270 static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw, 271 unsigned long parent_rate) 272 { 273 unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate); 274 struct ccu_common *cm = hw_to_ccu_common(hw); 275 u32 val = readl(cm->base + cm->reg); 276 277 if (val & CCU_MMC_NEW_TIMING_MODE) 278 return rate / 2; 279 return rate; 280 } 281 282 static int ccu_mp_mmc_determine_rate(struct clk_hw *hw, 283 struct clk_rate_request *req) 284 { 285 struct ccu_common *cm = hw_to_ccu_common(hw); 286 u32 val = readl(cm->base + cm->reg); 287 int ret; 288 289 /* adjust the requested clock rate */ 290 if (val & CCU_MMC_NEW_TIMING_MODE) { 291 req->rate *= 2; 292 req->min_rate *= 2; 293 req->max_rate *= 2; 294 } 295 296 ret = ccu_mp_determine_rate(hw, req); 297 298 /* re-adjust the requested clock rate back */ 299 if (val & CCU_MMC_NEW_TIMING_MODE) { 300 req->rate /= 2; 301 req->min_rate /= 2; 302 req->max_rate /= 2; 303 } 304 305 return ret; 306 } 307 308 static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate, 309 unsigned long parent_rate) 310 { 311 struct ccu_common *cm = hw_to_ccu_common(hw); 312 u32 val = readl(cm->base + cm->reg); 313 314 if (val & CCU_MMC_NEW_TIMING_MODE) 315 rate *= 2; 316 317 return ccu_mp_set_rate(hw, rate, parent_rate); 318 } 319 320 const struct clk_ops ccu_mp_mmc_ops = { 321 .disable = ccu_mp_disable, 322 .enable = ccu_mp_enable, 323 .is_enabled = ccu_mp_is_enabled, 324 325 .get_parent = ccu_mp_get_parent, 326 .set_parent = ccu_mp_set_parent, 327 328 .determine_rate = ccu_mp_mmc_determine_rate, 329 .recalc_rate = ccu_mp_mmc_recalc_rate, 330 .set_rate = ccu_mp_mmc_set_rate, 331 }; 332