1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 */ 10 11 #include <linux/clk-provider.h> 12 13 #include "ccu_gate.h" 14 #include "ccu_div.h" 15 16 static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux, 17 struct clk_hw *parent, 18 unsigned long *parent_rate, 19 unsigned long rate, 20 void *data) 21 { 22 struct ccu_div *cd = data; 23 24 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) 25 rate *= cd->fixed_post_div; 26 27 rate = divider_round_rate_parent(&cd->common.hw, parent, 28 rate, parent_rate, 29 cd->div.table, cd->div.width, 30 cd->div.flags); 31 32 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) 33 rate /= cd->fixed_post_div; 34 35 return rate; 36 } 37 38 static void ccu_div_disable(struct clk_hw *hw) 39 { 40 struct ccu_div *cd = hw_to_ccu_div(hw); 41 42 return ccu_gate_helper_disable(&cd->common, cd->enable); 43 } 44 45 static int ccu_div_enable(struct clk_hw *hw) 46 { 47 struct ccu_div *cd = hw_to_ccu_div(hw); 48 49 return ccu_gate_helper_enable(&cd->common, cd->enable); 50 } 51 52 static int ccu_div_is_enabled(struct clk_hw *hw) 53 { 54 struct ccu_div *cd = hw_to_ccu_div(hw); 55 56 return ccu_gate_helper_is_enabled(&cd->common, cd->enable); 57 } 58 59 static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, 60 unsigned long parent_rate) 61 { 62 struct ccu_div *cd = hw_to_ccu_div(hw); 63 unsigned long val; 64 u32 reg; 65 66 reg = readl(cd->common.base + cd->common.reg); 67 val = reg >> cd->div.shift; 68 val &= (1 << cd->div.width) - 1; 69 70 parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, 71 parent_rate); 72 73 val = divider_recalc_rate(hw, parent_rate, val, cd->div.table, 74 cd->div.flags); 75 76 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) 77 val /= cd->fixed_post_div; 78 79 return val; 80 } 81 82 static int ccu_div_determine_rate(struct clk_hw *hw, 83 struct clk_rate_request *req) 84 { 85 struct ccu_div *cd = hw_to_ccu_div(hw); 86 87 return ccu_mux_helper_determine_rate(&cd->common, &cd->mux, 88 req, ccu_div_round_rate, cd); 89 } 90 91 static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, 92 unsigned long parent_rate) 93 { 94 struct ccu_div *cd = hw_to_ccu_div(hw); 95 unsigned long flags; 96 unsigned long val; 97 u32 reg; 98 99 parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, 100 parent_rate); 101 102 if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) 103 rate *= cd->fixed_post_div; 104 105 val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, 106 cd->div.flags); 107 108 spin_lock_irqsave(cd->common.lock, flags); 109 110 reg = readl(cd->common.base + cd->common.reg); 111 reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); 112 113 writel(reg | (val << cd->div.shift), 114 cd->common.base + cd->common.reg); 115 116 spin_unlock_irqrestore(cd->common.lock, flags); 117 118 return 0; 119 } 120 121 static u8 ccu_div_get_parent(struct clk_hw *hw) 122 { 123 struct ccu_div *cd = hw_to_ccu_div(hw); 124 125 return ccu_mux_helper_get_parent(&cd->common, &cd->mux); 126 } 127 128 static int ccu_div_set_parent(struct clk_hw *hw, u8 index) 129 { 130 struct ccu_div *cd = hw_to_ccu_div(hw); 131 132 return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index); 133 } 134 135 const struct clk_ops ccu_div_ops = { 136 .disable = ccu_div_disable, 137 .enable = ccu_div_enable, 138 .is_enabled = ccu_div_is_enabled, 139 140 .get_parent = ccu_div_get_parent, 141 .set_parent = ccu_div_set_parent, 142 143 .determine_rate = ccu_div_determine_rate, 144 .recalc_rate = ccu_div_recalc_rate, 145 .set_rate = ccu_div_set_rate, 146 }; 147