10380126eSMesih Kilinc // SPDX-License-Identifier: GPL-2.0
20380126eSMesih Kilinc /*
30380126eSMesih Kilinc * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.io>
40380126eSMesih Kilinc *
50380126eSMesih Kilinc */
60380126eSMesih Kilinc
70380126eSMesih Kilinc #include <linux/clk-provider.h>
862e59c4eSStephen Boyd #include <linux/io.h>
97ec03b58SSamuel Holland #include <linux/module.h>
107ec03b58SSamuel Holland #include <linux/platform_device.h>
110380126eSMesih Kilinc
120380126eSMesih Kilinc #include "ccu_common.h"
130380126eSMesih Kilinc #include "ccu_reset.h"
140380126eSMesih Kilinc
150380126eSMesih Kilinc #include "ccu_div.h"
160380126eSMesih Kilinc #include "ccu_gate.h"
170380126eSMesih Kilinc #include "ccu_mp.h"
180380126eSMesih Kilinc #include "ccu_mult.h"
190380126eSMesih Kilinc #include "ccu_nk.h"
200380126eSMesih Kilinc #include "ccu_nkm.h"
210380126eSMesih Kilinc #include "ccu_nkmp.h"
220380126eSMesih Kilinc #include "ccu_nm.h"
230380126eSMesih Kilinc #include "ccu_phase.h"
240380126eSMesih Kilinc
250380126eSMesih Kilinc #include "ccu-suniv-f1c100s.h"
260380126eSMesih Kilinc
270380126eSMesih Kilinc static struct ccu_nkmp pll_cpu_clk = {
280380126eSMesih Kilinc .enable = BIT(31),
290380126eSMesih Kilinc .lock = BIT(28),
300380126eSMesih Kilinc
310380126eSMesih Kilinc .n = _SUNXI_CCU_MULT(8, 5),
320380126eSMesih Kilinc .k = _SUNXI_CCU_MULT(4, 2),
330380126eSMesih Kilinc .m = _SUNXI_CCU_DIV(0, 2),
340380126eSMesih Kilinc /* MAX is guessed by the BSP table */
350380126eSMesih Kilinc .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
360380126eSMesih Kilinc
370380126eSMesih Kilinc .common = {
380380126eSMesih Kilinc .reg = 0x000,
390380126eSMesih Kilinc .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
400380126eSMesih Kilinc &ccu_nkmp_ops,
410380126eSMesih Kilinc CLK_SET_RATE_UNGATE),
420380126eSMesih Kilinc },
430380126eSMesih Kilinc };
440380126eSMesih Kilinc
450380126eSMesih Kilinc /*
460380126eSMesih Kilinc * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
470380126eSMesih Kilinc * the base (2x, 4x and 8x), and one variable divider (the one true
480380126eSMesih Kilinc * pll audio).
490380126eSMesih Kilinc *
500380126eSMesih Kilinc * We don't have any need for the variable divider for now, so we just
510380126eSMesih Kilinc * hardcode it to match with the clock names
520380126eSMesih Kilinc */
530380126eSMesih Kilinc #define SUNIV_PLL_AUDIO_REG 0x008
540380126eSMesih Kilinc
550380126eSMesih Kilinc static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
560380126eSMesih Kilinc "osc24M", 0x008,
570380126eSMesih Kilinc 8, 7, /* N */
580380126eSMesih Kilinc 0, 5, /* M */
590380126eSMesih Kilinc BIT(31), /* gate */
600380126eSMesih Kilinc BIT(28), /* lock */
610380126eSMesih Kilinc CLK_SET_RATE_UNGATE);
620380126eSMesih Kilinc
630380126eSMesih Kilinc static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
640380126eSMesih Kilinc "osc24M", 0x010,
650380126eSMesih Kilinc 8, 7, /* N */
660380126eSMesih Kilinc 0, 4, /* M */
670380126eSMesih Kilinc BIT(24), /* frac enable */
680380126eSMesih Kilinc BIT(25), /* frac select */
690380126eSMesih Kilinc 270000000, /* frac rate 0 */
700380126eSMesih Kilinc 297000000, /* frac rate 1 */
710380126eSMesih Kilinc BIT(31), /* gate */
720380126eSMesih Kilinc BIT(28), /* lock */
730380126eSMesih Kilinc CLK_SET_RATE_UNGATE);
740380126eSMesih Kilinc
750380126eSMesih Kilinc static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
760380126eSMesih Kilinc "osc24M", 0x018,
770380126eSMesih Kilinc 8, 7, /* N */
780380126eSMesih Kilinc 0, 4, /* M */
790380126eSMesih Kilinc BIT(24), /* frac enable */
800380126eSMesih Kilinc BIT(25), /* frac select */
810380126eSMesih Kilinc 270000000, /* frac rate 0 */
820380126eSMesih Kilinc 297000000, /* frac rate 1 */
830380126eSMesih Kilinc BIT(31), /* gate */
840380126eSMesih Kilinc BIT(28), /* lock */
850380126eSMesih Kilinc CLK_SET_RATE_UNGATE);
860380126eSMesih Kilinc
870380126eSMesih Kilinc static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
880380126eSMesih Kilinc "osc24M", 0x020,
890380126eSMesih Kilinc 8, 5, /* N */
900380126eSMesih Kilinc 4, 2, /* K */
910380126eSMesih Kilinc 0, 2, /* M */
920380126eSMesih Kilinc BIT(31), /* gate */
930380126eSMesih Kilinc BIT(28), /* lock */
940380126eSMesih Kilinc CLK_IS_CRITICAL);
950380126eSMesih Kilinc
960380126eSMesih Kilinc static struct ccu_nk pll_periph_clk = {
970380126eSMesih Kilinc .enable = BIT(31),
980380126eSMesih Kilinc .lock = BIT(28),
990380126eSMesih Kilinc .k = _SUNXI_CCU_MULT(4, 2),
1000380126eSMesih Kilinc .n = _SUNXI_CCU_MULT(8, 5),
1010380126eSMesih Kilinc .common = {
1020380126eSMesih Kilinc .reg = 0x028,
1030380126eSMesih Kilinc .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
1040380126eSMesih Kilinc &ccu_nk_ops, 0),
1050380126eSMesih Kilinc },
1060380126eSMesih Kilinc };
1070380126eSMesih Kilinc
1080380126eSMesih Kilinc static const char * const cpu_parents[] = { "osc32k", "osc24M",
1090380126eSMesih Kilinc "pll-cpu", "pll-cpu" };
1100380126eSMesih Kilinc static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
1110380126eSMesih Kilinc 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
1120380126eSMesih Kilinc
1130380126eSMesih Kilinc static const char * const ahb_parents[] = { "osc32k", "osc24M",
1140380126eSMesih Kilinc "cpu", "pll-periph" };
1150380126eSMesih Kilinc static const struct ccu_mux_var_prediv ahb_predivs[] = {
1160380126eSMesih Kilinc { .index = 3, .shift = 6, .width = 2 },
1170380126eSMesih Kilinc };
1180380126eSMesih Kilinc static struct ccu_div ahb_clk = {
1190380126eSMesih Kilinc .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
1200380126eSMesih Kilinc
1210380126eSMesih Kilinc .mux = {
1220380126eSMesih Kilinc .shift = 12,
1230380126eSMesih Kilinc .width = 2,
1240380126eSMesih Kilinc
1250380126eSMesih Kilinc .var_predivs = ahb_predivs,
1260380126eSMesih Kilinc .n_var_predivs = ARRAY_SIZE(ahb_predivs),
1270380126eSMesih Kilinc },
1280380126eSMesih Kilinc
1290380126eSMesih Kilinc .common = {
1300380126eSMesih Kilinc .reg = 0x054,
1310380126eSMesih Kilinc .features = CCU_FEATURE_VARIABLE_PREDIV,
1320380126eSMesih Kilinc .hw.init = CLK_HW_INIT_PARENTS("ahb",
1330380126eSMesih Kilinc ahb_parents,
1340380126eSMesih Kilinc &ccu_div_ops,
1350380126eSMesih Kilinc 0),
1360380126eSMesih Kilinc },
1370380126eSMesih Kilinc };
1380380126eSMesih Kilinc
1390380126eSMesih Kilinc static struct clk_div_table apb_div_table[] = {
1400380126eSMesih Kilinc { .val = 0, .div = 2 },
1410380126eSMesih Kilinc { .val = 1, .div = 2 },
1420380126eSMesih Kilinc { .val = 2, .div = 4 },
1430380126eSMesih Kilinc { .val = 3, .div = 8 },
1440380126eSMesih Kilinc { /* Sentinel */ },
1450380126eSMesih Kilinc };
1460380126eSMesih Kilinc static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
1470380126eSMesih Kilinc 0x054, 8, 2, apb_div_table, 0);
1480380126eSMesih Kilinc
1490380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb",
1500380126eSMesih Kilinc 0x060, BIT(6), 0);
1510380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
1520380126eSMesih Kilinc 0x060, BIT(8), 0);
1530380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
1540380126eSMesih Kilinc 0x060, BIT(9), 0);
1550380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
1560380126eSMesih Kilinc 0x060, BIT(14), 0);
1570380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
1580380126eSMesih Kilinc 0x060, BIT(20), 0);
1590380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
1600380126eSMesih Kilinc 0x060, BIT(21), 0);
1610380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
1620380126eSMesih Kilinc 0x060, BIT(24), 0);
1630380126eSMesih Kilinc
1640380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
1650380126eSMesih Kilinc 0x064, BIT(0), 0);
1660380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb",
1670380126eSMesih Kilinc 0x064, BIT(4), 0);
1680380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb",
1690380126eSMesih Kilinc 0x064, BIT(5), 0);
1700380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb",
1710380126eSMesih Kilinc 0x064, BIT(8), 0);
1720380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb",
1730380126eSMesih Kilinc 0x064, BIT(9), 0);
1740380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb",
1750380126eSMesih Kilinc 0x064, BIT(10), 0);
1760380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb",
1770380126eSMesih Kilinc 0x064, BIT(12), 0);
1780380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb",
1790380126eSMesih Kilinc 0x064, BIT(14), 0);
1800380126eSMesih Kilinc
1810380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb",
1820380126eSMesih Kilinc 0x068, BIT(0), 0);
1830380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb",
1840380126eSMesih Kilinc 0x068, BIT(1), 0);
1850380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb",
1860380126eSMesih Kilinc 0x068, BIT(2), 0);
1870380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb",
1880380126eSMesih Kilinc 0x068, BIT(3), 0);
1890380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb",
1900380126eSMesih Kilinc 0x068, BIT(12), 0);
1910380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb",
1920380126eSMesih Kilinc 0x068, BIT(16), 0);
1930380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb",
1940380126eSMesih Kilinc 0x068, BIT(17), 0);
1950380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb",
1960380126eSMesih Kilinc 0x068, BIT(18), 0);
1970380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb",
1980380126eSMesih Kilinc 0x068, BIT(19), 0);
1990380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb",
2000380126eSMesih Kilinc 0x068, BIT(20), 0);
2010380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb",
2020380126eSMesih Kilinc 0x068, BIT(21), 0);
2030380126eSMesih Kilinc static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb",
2040380126eSMesih Kilinc 0x068, BIT(22), 0);
2050380126eSMesih Kilinc
2060380126eSMesih Kilinc static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
2070380126eSMesih Kilinc static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
2080380126eSMesih Kilinc 0, 4, /* M */
2090380126eSMesih Kilinc 16, 2, /* P */
2100380126eSMesih Kilinc 24, 2, /* mux */
2110380126eSMesih Kilinc BIT(31), /* gate */
2120380126eSMesih Kilinc 0);
2130380126eSMesih Kilinc
2140380126eSMesih Kilinc static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
2150380126eSMesih Kilinc 0x088, 20, 3, 0);
2160380126eSMesih Kilinc static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
2170380126eSMesih Kilinc 0x088, 8, 3, 0);
2180380126eSMesih Kilinc
2190380126eSMesih Kilinc static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
2200380126eSMesih Kilinc 0, 4, /* M */
2210380126eSMesih Kilinc 16, 2, /* P */
2220380126eSMesih Kilinc 24, 2, /* mux */
2230380126eSMesih Kilinc BIT(31), /* gate */
2240380126eSMesih Kilinc 0);
2250380126eSMesih Kilinc
2260380126eSMesih Kilinc static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
2270380126eSMesih Kilinc 0x08c, 20, 3, 0);
2280380126eSMesih Kilinc static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
2290380126eSMesih Kilinc 0x08c, 8, 3, 0);
2300380126eSMesih Kilinc
2310380126eSMesih Kilinc static const char * const i2s_spdif_parents[] = { "pll-audio-8x",
2320380126eSMesih Kilinc "pll-audio-4x",
2330380126eSMesih Kilinc "pll-audio-2x",
2340380126eSMesih Kilinc "pll-audio" };
2350380126eSMesih Kilinc
2360380126eSMesih Kilinc static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
2370380126eSMesih Kilinc 0x0b0, 16, 2, BIT(31), 0);
2380380126eSMesih Kilinc
2390380126eSMesih Kilinc static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
2400380126eSMesih Kilinc 0x0b4, 16, 2, BIT(31), 0);
2410380126eSMesih Kilinc
242*f64603c9SAndre Przywara static const char * const ir_parents[] = { "osc32k", "osc24M" };
243*f64603c9SAndre Przywara static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
244*f64603c9SAndre Przywara ir_parents, 0x0b8,
245*f64603c9SAndre Przywara 0, 4, /* M */
246*f64603c9SAndre Przywara 16, 2, /* P */
247*f64603c9SAndre Przywara 24, 2, /* mux */
248*f64603c9SAndre Przywara BIT(31), /* gate */
249*f64603c9SAndre Przywara 0);
2500380126eSMesih Kilinc
2510380126eSMesih Kilinc static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
2526630aad7SIcenowy Zheng 0x0cc, BIT(1), 0);
2530380126eSMesih Kilinc
2540380126eSMesih Kilinc static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
2550380126eSMesih Kilinc 0x100, BIT(0), 0);
2560380126eSMesih Kilinc static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
2570380126eSMesih Kilinc 0x100, BIT(1), 0);
2580380126eSMesih Kilinc static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace",
2590380126eSMesih Kilinc "pll-ddr", 0x100, BIT(2), 0);
2600380126eSMesih Kilinc static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
2610380126eSMesih Kilinc 0x100, BIT(3), 0);
2620380126eSMesih Kilinc static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
2630380126eSMesih Kilinc 0x100, BIT(24), 0);
2640380126eSMesih Kilinc static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
2650380126eSMesih Kilinc 0x100, BIT(26), 0);
2660380126eSMesih Kilinc
2670380126eSMesih Kilinc static const char * const de_parents[] = { "pll-video", "pll-periph" };
2680380126eSMesih Kilinc static const u8 de_table[] = { 0, 2, };
2690380126eSMesih Kilinc static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
2700380126eSMesih Kilinc de_parents, de_table,
2710380126eSMesih Kilinc 0x104, 0, 4, 24, 3, BIT(31), 0);
2720380126eSMesih Kilinc
2730380126eSMesih Kilinc static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
2740380126eSMesih Kilinc de_parents, de_table,
2750380126eSMesih Kilinc 0x10c, 0, 4, 24, 3, BIT(31), 0);
2760380126eSMesih Kilinc
2770380126eSMesih Kilinc static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" };
2780380126eSMesih Kilinc static const u8 tcon_table[] = { 0, 2, };
2790380126eSMesih Kilinc static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon",
2800380126eSMesih Kilinc tcon_parents, tcon_table,
2810380126eSMesih Kilinc 0x118, 24, 3, BIT(31),
2820380126eSMesih Kilinc CLK_SET_RATE_PARENT);
2830380126eSMesih Kilinc
2840380126eSMesih Kilinc static const char * const deinterlace_parents[] = { "pll-video",
2850380126eSMesih Kilinc "pll-video-2x" };
2860380126eSMesih Kilinc static const u8 deinterlace_table[] = { 0, 2, };
2870380126eSMesih Kilinc static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace",
2880380126eSMesih Kilinc deinterlace_parents, deinterlace_table,
2890380126eSMesih Kilinc 0x11c, 0, 4, 24, 3, BIT(31), 0);
2900380126eSMesih Kilinc
2910380126eSMesih Kilinc static const char * const tve_clk2_parents[] = { "pll-video",
2920380126eSMesih Kilinc "pll-video-2x" };
2930380126eSMesih Kilinc static const u8 tve_clk2_table[] = { 0, 2, };
2940380126eSMesih Kilinc static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
2950380126eSMesih Kilinc tve_clk2_parents, tve_clk2_table,
2960380126eSMesih Kilinc 0x120, 0, 4, 24, 3, BIT(31), 0);
2970380126eSMesih Kilinc static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
2980380126eSMesih Kilinc 0x120, 8, 1, BIT(15), 0);
2990380126eSMesih Kilinc
3000380126eSMesih Kilinc static const char * const tvd_parents[] = { "pll-video", "osc24M",
3010380126eSMesih Kilinc "pll-video-2x" };
3020380126eSMesih Kilinc static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents,
3030380126eSMesih Kilinc 0x124, 0, 4, 24, 3, BIT(31), 0);
3040380126eSMesih Kilinc
3050380126eSMesih Kilinc static const char * const csi_parents[] = { "pll-video", "osc24M" };
3060380126eSMesih Kilinc static const u8 csi_table[] = { 0, 5, };
3070380126eSMesih Kilinc static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table,
3080380126eSMesih Kilinc 0x120, 0, 4, 8, 3, BIT(15), 0);
3090380126eSMesih Kilinc
3100380126eSMesih Kilinc /*
3110380126eSMesih Kilinc * TODO: BSP says the parent is pll-audio, however common sense and experience
3120380126eSMesih Kilinc * told us it should be pll-ve. pll-ve is totally not used in BSP code.
3130380126eSMesih Kilinc */
3140380126eSMesih Kilinc static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
3150380126eSMesih Kilinc
3160380126eSMesih Kilinc static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
3170380126eSMesih Kilinc
3180380126eSMesih Kilinc static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
3190380126eSMesih Kilinc
3200380126eSMesih Kilinc static struct ccu_common *suniv_ccu_clks[] = {
3210380126eSMesih Kilinc &pll_cpu_clk.common,
3220380126eSMesih Kilinc &pll_audio_base_clk.common,
3230380126eSMesih Kilinc &pll_video_clk.common,
3240380126eSMesih Kilinc &pll_ve_clk.common,
3250380126eSMesih Kilinc &pll_ddr0_clk.common,
3260380126eSMesih Kilinc &pll_periph_clk.common,
3270380126eSMesih Kilinc &cpu_clk.common,
3280380126eSMesih Kilinc &ahb_clk.common,
3290380126eSMesih Kilinc &apb_clk.common,
3300380126eSMesih Kilinc &bus_dma_clk.common,
3310380126eSMesih Kilinc &bus_mmc0_clk.common,
3320380126eSMesih Kilinc &bus_mmc1_clk.common,
3330380126eSMesih Kilinc &bus_dram_clk.common,
3340380126eSMesih Kilinc &bus_spi0_clk.common,
3350380126eSMesih Kilinc &bus_spi1_clk.common,
3360380126eSMesih Kilinc &bus_otg_clk.common,
3370380126eSMesih Kilinc &bus_ve_clk.common,
3380380126eSMesih Kilinc &bus_lcd_clk.common,
3390380126eSMesih Kilinc &bus_deinterlace_clk.common,
3400380126eSMesih Kilinc &bus_csi_clk.common,
3410380126eSMesih Kilinc &bus_tve_clk.common,
3420380126eSMesih Kilinc &bus_tvd_clk.common,
3430380126eSMesih Kilinc &bus_de_be_clk.common,
3440380126eSMesih Kilinc &bus_de_fe_clk.common,
3450380126eSMesih Kilinc &bus_codec_clk.common,
3460380126eSMesih Kilinc &bus_spdif_clk.common,
3470380126eSMesih Kilinc &bus_ir_clk.common,
3480380126eSMesih Kilinc &bus_rsb_clk.common,
3490380126eSMesih Kilinc &bus_i2s0_clk.common,
3500380126eSMesih Kilinc &bus_i2c0_clk.common,
3510380126eSMesih Kilinc &bus_i2c1_clk.common,
3520380126eSMesih Kilinc &bus_i2c2_clk.common,
3530380126eSMesih Kilinc &bus_pio_clk.common,
3540380126eSMesih Kilinc &bus_uart0_clk.common,
3550380126eSMesih Kilinc &bus_uart1_clk.common,
3560380126eSMesih Kilinc &bus_uart2_clk.common,
3570380126eSMesih Kilinc &mmc0_clk.common,
3580380126eSMesih Kilinc &mmc0_sample_clk.common,
3590380126eSMesih Kilinc &mmc0_output_clk.common,
3600380126eSMesih Kilinc &mmc1_clk.common,
3610380126eSMesih Kilinc &mmc1_sample_clk.common,
3620380126eSMesih Kilinc &mmc1_output_clk.common,
3630380126eSMesih Kilinc &i2s_clk.common,
3640380126eSMesih Kilinc &spdif_clk.common,
365*f64603c9SAndre Przywara &ir_clk.common,
3660380126eSMesih Kilinc &usb_phy0_clk.common,
3670380126eSMesih Kilinc &dram_ve_clk.common,
3680380126eSMesih Kilinc &dram_csi_clk.common,
3690380126eSMesih Kilinc &dram_deinterlace_clk.common,
3700380126eSMesih Kilinc &dram_tvd_clk.common,
3710380126eSMesih Kilinc &dram_de_fe_clk.common,
3720380126eSMesih Kilinc &dram_de_be_clk.common,
3730380126eSMesih Kilinc &de_be_clk.common,
3740380126eSMesih Kilinc &de_fe_clk.common,
3750380126eSMesih Kilinc &tcon_clk.common,
3760380126eSMesih Kilinc &deinterlace_clk.common,
3770380126eSMesih Kilinc &tve_clk2_clk.common,
3780380126eSMesih Kilinc &tve_clk1_clk.common,
3790380126eSMesih Kilinc &tvd_clk.common,
3800380126eSMesih Kilinc &csi_clk.common,
3810380126eSMesih Kilinc &ve_clk.common,
3820380126eSMesih Kilinc &codec_clk.common,
3830380126eSMesih Kilinc &avs_clk.common,
3840380126eSMesih Kilinc };
3850380126eSMesih Kilinc
3864d34497eSChen-Yu Tsai static const struct clk_hw *clk_parent_pll_audio[] = {
3874d34497eSChen-Yu Tsai &pll_audio_base_clk.common.hw
3884d34497eSChen-Yu Tsai };
3894d34497eSChen-Yu Tsai
3904d34497eSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
3914d34497eSChen-Yu Tsai clk_parent_pll_audio,
3924d34497eSChen-Yu Tsai 4, 1, CLK_SET_RATE_PARENT);
3934d34497eSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
3944d34497eSChen-Yu Tsai clk_parent_pll_audio,
3954d34497eSChen-Yu Tsai 2, 1, CLK_SET_RATE_PARENT);
3964d34497eSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
3974d34497eSChen-Yu Tsai clk_parent_pll_audio,
3984d34497eSChen-Yu Tsai 1, 1, CLK_SET_RATE_PARENT);
3994d34497eSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
4004d34497eSChen-Yu Tsai clk_parent_pll_audio,
4014d34497eSChen-Yu Tsai 1, 2, CLK_SET_RATE_PARENT);
4024d34497eSChen-Yu Tsai static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
4034d34497eSChen-Yu Tsai &pll_video_clk.common.hw,
4044d34497eSChen-Yu Tsai 1, 2, 0);
4050380126eSMesih Kilinc
4060380126eSMesih Kilinc static struct clk_hw_onecell_data suniv_hw_clks = {
4070380126eSMesih Kilinc .hws = {
4080380126eSMesih Kilinc [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
4090380126eSMesih Kilinc [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
4100380126eSMesih Kilinc [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
4110380126eSMesih Kilinc [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
4120380126eSMesih Kilinc [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
4130380126eSMesih Kilinc [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
4140380126eSMesih Kilinc [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
4150380126eSMesih Kilinc [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
4160380126eSMesih Kilinc [CLK_PLL_VE] = &pll_ve_clk.common.hw,
4170380126eSMesih Kilinc [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
4180380126eSMesih Kilinc [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
4190380126eSMesih Kilinc [CLK_CPU] = &cpu_clk.common.hw,
4200380126eSMesih Kilinc [CLK_AHB] = &ahb_clk.common.hw,
4210380126eSMesih Kilinc [CLK_APB] = &apb_clk.common.hw,
4220380126eSMesih Kilinc [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
4230380126eSMesih Kilinc [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
4240380126eSMesih Kilinc [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
4250380126eSMesih Kilinc [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
4260380126eSMesih Kilinc [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
4270380126eSMesih Kilinc [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
4280380126eSMesih Kilinc [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
4290380126eSMesih Kilinc [CLK_BUS_VE] = &bus_ve_clk.common.hw,
4300380126eSMesih Kilinc [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
4310380126eSMesih Kilinc [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
4320380126eSMesih Kilinc [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
4330380126eSMesih Kilinc [CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
4340380126eSMesih Kilinc [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
4350380126eSMesih Kilinc [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
4360380126eSMesih Kilinc [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
4370380126eSMesih Kilinc [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
4380380126eSMesih Kilinc [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
4390380126eSMesih Kilinc [CLK_BUS_IR] = &bus_ir_clk.common.hw,
4400380126eSMesih Kilinc [CLK_BUS_RSB] = &bus_rsb_clk.common.hw,
4410380126eSMesih Kilinc [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
4420380126eSMesih Kilinc [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
4430380126eSMesih Kilinc [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
4440380126eSMesih Kilinc [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
4450380126eSMesih Kilinc [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
4460380126eSMesih Kilinc [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
4470380126eSMesih Kilinc [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
4480380126eSMesih Kilinc [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
4490380126eSMesih Kilinc [CLK_MMC0] = &mmc0_clk.common.hw,
4500380126eSMesih Kilinc [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
4510380126eSMesih Kilinc [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
4520380126eSMesih Kilinc [CLK_MMC1] = &mmc1_clk.common.hw,
4530380126eSMesih Kilinc [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
4540380126eSMesih Kilinc [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
4550380126eSMesih Kilinc [CLK_I2S] = &i2s_clk.common.hw,
4560380126eSMesih Kilinc [CLK_SPDIF] = &spdif_clk.common.hw,
457*f64603c9SAndre Przywara [CLK_IR] = &ir_clk.common.hw,
4580380126eSMesih Kilinc [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
4590380126eSMesih Kilinc [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
4600380126eSMesih Kilinc [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
4610380126eSMesih Kilinc [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
4620380126eSMesih Kilinc [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
4630380126eSMesih Kilinc [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
4640380126eSMesih Kilinc [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
4650380126eSMesih Kilinc [CLK_DE_BE] = &de_be_clk.common.hw,
4660380126eSMesih Kilinc [CLK_DE_FE] = &de_fe_clk.common.hw,
4670380126eSMesih Kilinc [CLK_TCON] = &tcon_clk.common.hw,
4680380126eSMesih Kilinc [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
4690380126eSMesih Kilinc [CLK_TVE2_CLK] = &tve_clk2_clk.common.hw,
4700380126eSMesih Kilinc [CLK_TVE1_CLK] = &tve_clk1_clk.common.hw,
4710380126eSMesih Kilinc [CLK_TVD] = &tvd_clk.common.hw,
4720380126eSMesih Kilinc [CLK_CSI] = &csi_clk.common.hw,
4730380126eSMesih Kilinc [CLK_VE] = &ve_clk.common.hw,
4740380126eSMesih Kilinc [CLK_CODEC] = &codec_clk.common.hw,
4750380126eSMesih Kilinc [CLK_AVS] = &avs_clk.common.hw,
4760380126eSMesih Kilinc },
4770380126eSMesih Kilinc .num = CLK_NUMBER,
4780380126eSMesih Kilinc };
4790380126eSMesih Kilinc
4800380126eSMesih Kilinc static struct ccu_reset_map suniv_ccu_resets[] = {
4810380126eSMesih Kilinc [RST_USB_PHY0] = { 0x0cc, BIT(0) },
4820380126eSMesih Kilinc
4830380126eSMesih Kilinc [RST_BUS_DMA] = { 0x2c0, BIT(6) },
4840380126eSMesih Kilinc [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
4850380126eSMesih Kilinc [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
4860380126eSMesih Kilinc [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
4870380126eSMesih Kilinc [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
4880380126eSMesih Kilinc [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
4890380126eSMesih Kilinc [RST_BUS_OTG] = { 0x2c0, BIT(24) },
4900380126eSMesih Kilinc [RST_BUS_VE] = { 0x2c4, BIT(0) },
4910380126eSMesih Kilinc [RST_BUS_LCD] = { 0x2c4, BIT(4) },
4920380126eSMesih Kilinc [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
4930380126eSMesih Kilinc [RST_BUS_CSI] = { 0x2c4, BIT(8) },
4940380126eSMesih Kilinc [RST_BUS_TVD] = { 0x2c4, BIT(9) },
4950380126eSMesih Kilinc [RST_BUS_TVE] = { 0x2c4, BIT(10) },
4960380126eSMesih Kilinc [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
4970380126eSMesih Kilinc [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
4980380126eSMesih Kilinc [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
4990380126eSMesih Kilinc [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
5000380126eSMesih Kilinc [RST_BUS_IR] = { 0x2d0, BIT(2) },
5010380126eSMesih Kilinc [RST_BUS_RSB] = { 0x2d0, BIT(3) },
5020380126eSMesih Kilinc [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
5030380126eSMesih Kilinc [RST_BUS_I2C0] = { 0x2d0, BIT(16) },
5040380126eSMesih Kilinc [RST_BUS_I2C1] = { 0x2d0, BIT(17) },
5050380126eSMesih Kilinc [RST_BUS_I2C2] = { 0x2d0, BIT(18) },
5060380126eSMesih Kilinc [RST_BUS_UART0] = { 0x2d0, BIT(20) },
5070380126eSMesih Kilinc [RST_BUS_UART1] = { 0x2d0, BIT(21) },
5080380126eSMesih Kilinc [RST_BUS_UART2] = { 0x2d0, BIT(22) },
5090380126eSMesih Kilinc };
5100380126eSMesih Kilinc
5110380126eSMesih Kilinc static const struct sunxi_ccu_desc suniv_ccu_desc = {
5120380126eSMesih Kilinc .ccu_clks = suniv_ccu_clks,
5130380126eSMesih Kilinc .num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks),
5140380126eSMesih Kilinc
5150380126eSMesih Kilinc .hw_clks = &suniv_hw_clks,
5160380126eSMesih Kilinc
5170380126eSMesih Kilinc .resets = suniv_ccu_resets,
5180380126eSMesih Kilinc .num_resets = ARRAY_SIZE(suniv_ccu_resets),
5190380126eSMesih Kilinc };
5200380126eSMesih Kilinc
5210380126eSMesih Kilinc static struct ccu_pll_nb suniv_pll_cpu_nb = {
5220380126eSMesih Kilinc .common = &pll_cpu_clk.common,
5230380126eSMesih Kilinc /* copy from pll_cpu_clk */
5240380126eSMesih Kilinc .enable = BIT(31),
5250380126eSMesih Kilinc .lock = BIT(28),
5260380126eSMesih Kilinc };
5270380126eSMesih Kilinc
5280380126eSMesih Kilinc static struct ccu_mux_nb suniv_cpu_nb = {
5290380126eSMesih Kilinc .common = &cpu_clk.common,
5300380126eSMesih Kilinc .cm = &cpu_clk.mux,
5310380126eSMesih Kilinc .delay_us = 1, /* > 8 clock cycles at 24 MHz */
5320380126eSMesih Kilinc .bypass_index = 1, /* index of 24 MHz oscillator */
5330380126eSMesih Kilinc };
5340380126eSMesih Kilinc
suniv_f1c100s_ccu_probe(struct platform_device * pdev)5357ec03b58SSamuel Holland static int suniv_f1c100s_ccu_probe(struct platform_device *pdev)
5360380126eSMesih Kilinc {
5370380126eSMesih Kilinc void __iomem *reg;
5387ec03b58SSamuel Holland int ret;
5390380126eSMesih Kilinc u32 val;
5400380126eSMesih Kilinc
5417ec03b58SSamuel Holland reg = devm_platform_ioremap_resource(pdev, 0);
5427ec03b58SSamuel Holland if (IS_ERR(reg))
5437ec03b58SSamuel Holland return PTR_ERR(reg);
5440380126eSMesih Kilinc
5450380126eSMesih Kilinc /* Force the PLL-Audio-1x divider to 4 */
5460380126eSMesih Kilinc val = readl(reg + SUNIV_PLL_AUDIO_REG);
5470380126eSMesih Kilinc val &= ~GENMASK(19, 16);
5480380126eSMesih Kilinc writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
5490380126eSMesih Kilinc
5507ec03b58SSamuel Holland ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &suniv_ccu_desc);
5517ec03b58SSamuel Holland if (ret)
5527ec03b58SSamuel Holland return ret;
5530380126eSMesih Kilinc
5540380126eSMesih Kilinc /* Gate then ungate PLL CPU after any rate changes */
5550380126eSMesih Kilinc ccu_pll_notifier_register(&suniv_pll_cpu_nb);
5560380126eSMesih Kilinc
5570380126eSMesih Kilinc /* Reparent CPU during PLL CPU rate changes */
5580380126eSMesih Kilinc ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
5590380126eSMesih Kilinc &suniv_cpu_nb);
5607ec03b58SSamuel Holland
5617ec03b58SSamuel Holland return 0;
5620380126eSMesih Kilinc }
5637ec03b58SSamuel Holland
5647ec03b58SSamuel Holland static const struct of_device_id suniv_f1c100s_ccu_ids[] = {
5657ec03b58SSamuel Holland { .compatible = "allwinner,suniv-f1c100s-ccu" },
5667ec03b58SSamuel Holland { }
5677ec03b58SSamuel Holland };
5687ec03b58SSamuel Holland
5697ec03b58SSamuel Holland static struct platform_driver suniv_f1c100s_ccu_driver = {
5707ec03b58SSamuel Holland .probe = suniv_f1c100s_ccu_probe,
5717ec03b58SSamuel Holland .driver = {
5727ec03b58SSamuel Holland .name = "suniv-f1c100s-ccu",
5737ec03b58SSamuel Holland .suppress_bind_attrs = true,
5747ec03b58SSamuel Holland .of_match_table = suniv_f1c100s_ccu_ids,
5757ec03b58SSamuel Holland },
5767ec03b58SSamuel Holland };
5777ec03b58SSamuel Holland module_platform_driver(suniv_f1c100s_ccu_driver);
5787ec03b58SSamuel Holland
5797ec03b58SSamuel Holland MODULE_IMPORT_NS(SUNXI_CCU);
5807ec03b58SSamuel Holland MODULE_LICENSE("GPL");
581