1 /* 2 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/io.h> 16 #include <linux/of_address.h> 17 #include <linux/platform_device.h> 18 19 #include "ccu_common.h" 20 #include "ccu_reset.h" 21 22 #include "ccu_div.h" 23 #include "ccu_gate.h" 24 #include "ccu_mp.h" 25 #include "ccu_nkmp.h" 26 #include "ccu_nm.h" 27 #include "ccu_phase.h" 28 29 #include "ccu-sun9i-a80.h" 30 31 #define CCU_SUN9I_LOCK_REG 0x09c 32 33 /* 34 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However 35 * P should only be used for output frequencies lower than 228 MHz. 36 * Neither mainline Linux, U-boot, nor the vendor BSPs use these. 37 * 38 * For now we can just model it as a multiplier clock, and force P to /1. 39 */ 40 #define SUN9I_A80_PLL_C0CPUX_REG 0x000 41 #define SUN9I_A80_PLL_C1CPUX_REG 0x004 42 43 static struct ccu_mult pll_c0cpux_clk = { 44 .enable = BIT(31), 45 .lock = BIT(0), 46 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 47 .common = { 48 .reg = SUN9I_A80_PLL_C0CPUX_REG, 49 .lock_reg = CCU_SUN9I_LOCK_REG, 50 .features = CCU_FEATURE_LOCK_REG, 51 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M", 52 &ccu_mult_ops, 53 CLK_SET_RATE_UNGATE), 54 }, 55 }; 56 57 static struct ccu_mult pll_c1cpux_clk = { 58 .enable = BIT(31), 59 .lock = BIT(1), 60 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 61 .common = { 62 .reg = SUN9I_A80_PLL_C1CPUX_REG, 63 .lock_reg = CCU_SUN9I_LOCK_REG, 64 .features = CCU_FEATURE_LOCK_REG, 65 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M", 66 &ccu_mult_ops, 67 CLK_SET_RATE_UNGATE), 68 }, 69 }; 70 71 /* 72 * The Audio PLL has d1, d2 dividers in addition to the usual N, M 73 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz 74 * and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0. 75 */ 76 #define SUN9I_A80_PLL_AUDIO_REG 0x008 77 78 static struct ccu_nm pll_audio_clk = { 79 .enable = BIT(31), 80 .lock = BIT(2), 81 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 82 .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0), 83 .common = { 84 .reg = 0x008, 85 .lock_reg = CCU_SUN9I_LOCK_REG, 86 .features = CCU_FEATURE_LOCK_REG, 87 .hw.init = CLK_HW_INIT("pll-audio", "osc24M", 88 &ccu_nm_ops, CLK_SET_RATE_UNGATE), 89 }, 90 }; 91 92 /* Some PLLs are input * N / div1 / div2. Model them as NKMP with no K */ 93 static struct ccu_nkmp pll_periph0_clk = { 94 .enable = BIT(31), 95 .lock = BIT(3), 96 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 97 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 98 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 99 .common = { 100 .reg = 0x00c, 101 .lock_reg = CCU_SUN9I_LOCK_REG, 102 .features = CCU_FEATURE_LOCK_REG, 103 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 104 &ccu_nkmp_ops, 105 CLK_SET_RATE_UNGATE), 106 }, 107 }; 108 109 static struct ccu_nkmp pll_ve_clk = { 110 .enable = BIT(31), 111 .lock = BIT(4), 112 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 113 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 114 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 115 .common = { 116 .reg = 0x010, 117 .lock_reg = CCU_SUN9I_LOCK_REG, 118 .features = CCU_FEATURE_LOCK_REG, 119 .hw.init = CLK_HW_INIT("pll-ve", "osc24M", 120 &ccu_nkmp_ops, 121 CLK_SET_RATE_UNGATE), 122 }, 123 }; 124 125 static struct ccu_nkmp pll_ddr_clk = { 126 .enable = BIT(31), 127 .lock = BIT(5), 128 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 129 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 130 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 131 .common = { 132 .reg = 0x014, 133 .lock_reg = CCU_SUN9I_LOCK_REG, 134 .features = CCU_FEATURE_LOCK_REG, 135 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M", 136 &ccu_nkmp_ops, 137 CLK_SET_RATE_UNGATE), 138 }, 139 }; 140 141 static struct ccu_nm pll_video0_clk = { 142 .enable = BIT(31), 143 .lock = BIT(6), 144 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 145 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 146 .common = { 147 .reg = 0x018, 148 .lock_reg = CCU_SUN9I_LOCK_REG, 149 .features = CCU_FEATURE_LOCK_REG, 150 .hw.init = CLK_HW_INIT("pll-video0", "osc24M", 151 &ccu_nm_ops, 152 CLK_SET_RATE_UNGATE), 153 }, 154 }; 155 156 static struct ccu_nkmp pll_video1_clk = { 157 .enable = BIT(31), 158 .lock = BIT(7), 159 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 160 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 161 .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ 162 .common = { 163 .reg = 0x01c, 164 .lock_reg = CCU_SUN9I_LOCK_REG, 165 .features = CCU_FEATURE_LOCK_REG, 166 .hw.init = CLK_HW_INIT("pll-video1", "osc24M", 167 &ccu_nkmp_ops, 168 CLK_SET_RATE_UNGATE), 169 }, 170 }; 171 172 static struct ccu_nkmp pll_gpu_clk = { 173 .enable = BIT(31), 174 .lock = BIT(8), 175 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 176 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 177 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 178 .common = { 179 .reg = 0x020, 180 .lock_reg = CCU_SUN9I_LOCK_REG, 181 .features = CCU_FEATURE_LOCK_REG, 182 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", 183 &ccu_nkmp_ops, 184 CLK_SET_RATE_UNGATE), 185 }, 186 }; 187 188 static struct ccu_nkmp pll_de_clk = { 189 .enable = BIT(31), 190 .lock = BIT(9), 191 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 192 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 193 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 194 .common = { 195 .reg = 0x024, 196 .lock_reg = CCU_SUN9I_LOCK_REG, 197 .features = CCU_FEATURE_LOCK_REG, 198 .hw.init = CLK_HW_INIT("pll-de", "osc24M", 199 &ccu_nkmp_ops, 200 CLK_SET_RATE_UNGATE), 201 }, 202 }; 203 204 static struct ccu_nkmp pll_isp_clk = { 205 .enable = BIT(31), 206 .lock = BIT(10), 207 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 208 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 209 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 210 .common = { 211 .reg = 0x028, 212 .lock_reg = CCU_SUN9I_LOCK_REG, 213 .features = CCU_FEATURE_LOCK_REG, 214 .hw.init = CLK_HW_INIT("pll-isp", "osc24M", 215 &ccu_nkmp_ops, 216 CLK_SET_RATE_UNGATE), 217 }, 218 }; 219 220 static struct ccu_nkmp pll_periph1_clk = { 221 .enable = BIT(31), 222 .lock = BIT(11), 223 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 224 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 225 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 226 .common = { 227 .reg = 0x028, 228 .lock_reg = CCU_SUN9I_LOCK_REG, 229 .features = CCU_FEATURE_LOCK_REG, 230 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 231 &ccu_nkmp_ops, 232 CLK_SET_RATE_UNGATE), 233 }, 234 }; 235 236 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" }; 237 static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents, 238 0x50, 0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 239 240 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" }; 241 static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents, 242 0x50, 8, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 243 244 static struct clk_div_table axi_div_table[] = { 245 { .val = 0, .div = 1 }, 246 { .val = 1, .div = 2 }, 247 { .val = 2, .div = 3 }, 248 { .val = 3, .div = 4 }, 249 { .val = 4, .div = 4 }, 250 { .val = 5, .div = 4 }, 251 { .val = 6, .div = 4 }, 252 { .val = 7, .div = 4 }, 253 { /* Sentinel */ }, 254 }; 255 256 static SUNXI_CCU_M(atb0_clk, "atb0", "c0cpux", 0x054, 8, 2, 0); 257 258 static SUNXI_CCU_DIV_TABLE(axi0_clk, "axi0", "c0cpux", 259 0x054, 0, 3, axi_div_table, 0); 260 261 static SUNXI_CCU_M(atb1_clk, "atb1", "c1cpux", 0x058, 8, 2, 0); 262 263 static SUNXI_CCU_DIV_TABLE(axi1_clk, "axi1", "c1cpux", 264 0x058, 0, 3, axi_div_table, 0); 265 266 static const char * const gtbus_parents[] = { "osc24M", "pll-periph0", 267 "pll-periph1", "pll-periph1" }; 268 static SUNXI_CCU_M_WITH_MUX(gtbus_clk, "gtbus", gtbus_parents, 269 0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL); 270 271 static const char * const ahb_parents[] = { "gtbus", "pll-periph0", 272 "pll-periph1", "pll-periph1" }; 273 static struct ccu_div ahb0_clk = { 274 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 275 .mux = _SUNXI_CCU_MUX(24, 2), 276 .common = { 277 .reg = 0x060, 278 .hw.init = CLK_HW_INIT_PARENTS("ahb0", 279 ahb_parents, 280 &ccu_div_ops, 281 0), 282 }, 283 }; 284 285 static struct ccu_div ahb1_clk = { 286 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 287 .mux = _SUNXI_CCU_MUX(24, 2), 288 .common = { 289 .reg = 0x064, 290 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 291 ahb_parents, 292 &ccu_div_ops, 293 0), 294 }, 295 }; 296 297 static struct ccu_div ahb2_clk = { 298 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 299 .mux = _SUNXI_CCU_MUX(24, 2), 300 .common = { 301 .reg = 0x068, 302 .hw.init = CLK_HW_INIT_PARENTS("ahb2", 303 ahb_parents, 304 &ccu_div_ops, 305 0), 306 }, 307 }; 308 309 static const char * const apb_parents[] = { "osc24M", "pll-periph0" }; 310 311 static struct ccu_div apb0_clk = { 312 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 313 .mux = _SUNXI_CCU_MUX(24, 1), 314 .common = { 315 .reg = 0x070, 316 .hw.init = CLK_HW_INIT_PARENTS("apb0", 317 apb_parents, 318 &ccu_div_ops, 319 0), 320 }, 321 }; 322 323 static struct ccu_div apb1_clk = { 324 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 325 .mux = _SUNXI_CCU_MUX(24, 1), 326 .common = { 327 .reg = 0x074, 328 .hw.init = CLK_HW_INIT_PARENTS("apb1", 329 apb_parents, 330 &ccu_div_ops, 331 0), 332 }, 333 }; 334 335 static struct ccu_div cci400_clk = { 336 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 337 .mux = _SUNXI_CCU_MUX(24, 2), 338 .common = { 339 .reg = 0x078, 340 .hw.init = CLK_HW_INIT_PARENTS("cci400", 341 ahb_parents, 342 &ccu_div_ops, 343 CLK_IS_CRITICAL), 344 }, 345 }; 346 347 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", apb_parents, 348 0x080, 0, 3, 24, 2, BIT(31), 0); 349 350 static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", apb_parents, 351 0x084, 0, 3, 24, 2, BIT(31), 0); 352 353 static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" }; 354 static const struct ccu_mux_fixed_prediv out_prediv = { 355 .index = 0, .div = 750 356 }; 357 358 static struct ccu_mp out_a_clk = { 359 .enable = BIT(31), 360 .m = _SUNXI_CCU_DIV(8, 5), 361 .p = _SUNXI_CCU_DIV(20, 2), 362 .mux = { 363 .shift = 24, 364 .width = 4, 365 .fixed_predivs = &out_prediv, 366 .n_predivs = 1, 367 }, 368 .common = { 369 .reg = 0x180, 370 .features = CCU_FEATURE_FIXED_PREDIV, 371 .hw.init = CLK_HW_INIT_PARENTS("out-a", 372 out_parents, 373 &ccu_mp_ops, 374 0), 375 }, 376 }; 377 378 static struct ccu_mp out_b_clk = { 379 .enable = BIT(31), 380 .m = _SUNXI_CCU_DIV(8, 5), 381 .p = _SUNXI_CCU_DIV(20, 2), 382 .mux = { 383 .shift = 24, 384 .width = 4, 385 .fixed_predivs = &out_prediv, 386 .n_predivs = 1, 387 }, 388 .common = { 389 .reg = 0x184, 390 .features = CCU_FEATURE_FIXED_PREDIV, 391 .hw.init = CLK_HW_INIT_PARENTS("out-b", 392 out_parents, 393 &ccu_mp_ops, 394 0), 395 }, 396 }; 397 398 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" }; 399 400 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents, 401 0x400, 402 0, 4, /* M */ 403 16, 2, /* P */ 404 24, 4, /* mux */ 405 BIT(31), /* gate */ 406 0); 407 408 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents, 409 0x404, 410 0, 4, /* M */ 411 16, 2, /* P */ 412 24, 4, /* mux */ 413 BIT(31), /* gate */ 414 0); 415 416 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents, 417 0x408, 418 0, 4, /* M */ 419 16, 2, /* P */ 420 24, 4, /* mux */ 421 BIT(31), /* gate */ 422 0); 423 424 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents, 425 0x40c, 426 0, 4, /* M */ 427 16, 2, /* P */ 428 24, 4, /* mux */ 429 BIT(31), /* gate */ 430 0); 431 432 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 433 0x410, 434 0, 4, /* M */ 435 16, 2, /* P */ 436 24, 4, /* mux */ 437 BIT(31), /* gate */ 438 0); 439 440 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0", 441 0x410, 20, 3, 0); 442 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0", 443 0x410, 8, 3, 0); 444 445 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 446 0x414, 447 0, 4, /* M */ 448 16, 2, /* P */ 449 24, 4, /* mux */ 450 BIT(31), /* gate */ 451 0); 452 453 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", 454 0x414, 20, 3, 0); 455 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1", 456 0x414, 8, 3, 0); 457 458 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 459 0x418, 460 0, 4, /* M */ 461 16, 2, /* P */ 462 24, 4, /* mux */ 463 BIT(31), /* gate */ 464 0); 465 466 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2", 467 0x418, 20, 3, 0); 468 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2", 469 0x418, 8, 3, 0); 470 471 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 472 0x41c, 473 0, 4, /* M */ 474 16, 2, /* P */ 475 24, 4, /* mux */ 476 BIT(31), /* gate */ 477 0); 478 479 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3", 480 0x41c, 20, 3, 0); 481 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3", 482 0x41c, 8, 3, 0); 483 484 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 485 0x428, 486 0, 4, /* M */ 487 16, 2, /* P */ 488 24, 4, /* mux */ 489 BIT(31), /* gate */ 490 0); 491 492 static const char * const ss_parents[] = { "osc24M", "pll-periph", 493 "pll-periph1" }; 494 static const u8 ss_table[] = { 0, 1, 13 }; 495 static struct ccu_mp ss_clk = { 496 .enable = BIT(31), 497 .m = _SUNXI_CCU_DIV(0, 4), 498 .p = _SUNXI_CCU_DIV(16, 2), 499 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, ss_table), 500 .common = { 501 .reg = 0x42c, 502 .hw.init = CLK_HW_INIT_PARENTS("ss", 503 ss_parents, 504 &ccu_mp_ops, 505 0), 506 }, 507 }; 508 509 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 510 0x430, 511 0, 4, /* M */ 512 16, 2, /* P */ 513 24, 4, /* mux */ 514 BIT(31), /* gate */ 515 0); 516 517 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 518 0x434, 519 0, 4, /* M */ 520 16, 2, /* P */ 521 24, 4, /* mux */ 522 BIT(31), /* gate */ 523 0); 524 525 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 526 0x438, 527 0, 4, /* M */ 528 16, 2, /* P */ 529 24, 4, /* mux */ 530 BIT(31), /* gate */ 531 0); 532 533 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 534 0x43c, 535 0, 4, /* M */ 536 16, 2, /* P */ 537 24, 4, /* mux */ 538 BIT(31), /* gate */ 539 0); 540 541 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio", 542 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 543 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio", 544 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 545 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 546 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 547 548 static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" }; 549 static const u8 sdram_table[] = { 0, 3 }; 550 551 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(sdram_clk, "sdram", 552 sdram_parents, sdram_table, 553 0x484, 554 8, 4, /* M */ 555 12, 4, /* mux */ 556 0, /* no gate */ 557 CLK_IS_CRITICAL); 558 559 static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490, 560 0, 4, BIT(31), CLK_SET_RATE_PARENT); 561 562 static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0); 563 564 static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" }; 565 static const u8 mp_table[] = { 9, 10, 11 }; 566 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mp_clk, "mp", mp_parents, mp_table, 567 0x498, 568 0, 4, /* M */ 569 24, 4, /* mux */ 570 BIT(31), /* gate */ 571 0); 572 573 static const char * const display_parents[] = { "pll-video0", "pll-video1" }; 574 static const u8 display_table[] = { 8, 9 }; 575 576 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd0_clk, "lcd0", 577 display_parents, display_table, 578 0x49c, 579 0, 4, /* M */ 580 24, 4, /* mux */ 581 BIT(31), /* gate */ 582 CLK_SET_RATE_NO_REPARENT | 583 CLK_SET_RATE_PARENT); 584 585 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd1_clk, "lcd1", 586 display_parents, display_table, 587 0x4a0, 588 0, 4, /* M */ 589 24, 4, /* mux */ 590 BIT(31), /* gate */ 591 CLK_SET_RATE_NO_REPARENT | 592 CLK_SET_RATE_PARENT); 593 594 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0", 595 display_parents, display_table, 596 0x4a8, 597 0, 4, /* M */ 598 24, 4, /* mux */ 599 BIT(31), /* gate */ 600 CLK_SET_RATE_PARENT); 601 602 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" }; 603 static const u8 mipi_dsi1_table[] = { 0, 9 }; 604 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1", 605 mipi_dsi1_parents, mipi_dsi1_table, 606 0x4ac, 607 0, 4, /* M */ 608 24, 4, /* mux */ 609 BIT(31), /* gate */ 610 CLK_SET_RATE_PARENT); 611 612 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi", 613 display_parents, display_table, 614 0x4b0, 615 0, 4, /* M */ 616 24, 4, /* mux */ 617 BIT(31), /* gate */ 618 CLK_SET_RATE_NO_REPARENT | 619 CLK_SET_RATE_PARENT); 620 621 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0); 622 623 static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc, 624 0, 4, BIT(31), 0); 625 626 static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0, 627 0, 4, BIT(31), CLK_SET_RATE_PARENT); 628 629 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0); 630 631 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk", 632 mipi_dsi1_parents, mipi_dsi1_table, 633 0x4c4, 634 0, 4, /* M */ 635 24, 4, /* mux */ 636 BIT(31), /* gate */ 637 CLK_SET_RATE_PARENT); 638 639 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk", 640 mipi_dsi1_parents, mipi_dsi1_table, 641 0x4c8, 642 0, 4, /* M */ 643 24, 4, /* mux */ 644 BIT(31), /* gate */ 645 CLK_SET_RATE_PARENT); 646 647 static const char * const fd_parents[] = { "pll-periph0", "pll-isp" }; 648 static const u8 fd_table[] = { 1, 12 }; 649 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(fd_clk, "fd", fd_parents, fd_table, 650 0x4cc, 651 0, 4, /* M */ 652 24, 4, /* mux */ 653 BIT(31), /* gate */ 654 0); 655 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0, 656 16, 3, BIT(31), CLK_SET_RATE_PARENT); 657 658 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0); 659 660 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0, 661 0, 3, BIT(31), CLK_SET_RATE_PARENT); 662 static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4, 663 0, 3, BIT(31), CLK_SET_RATE_PARENT); 664 665 static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" }; 666 static const u8 gpu_axi_table[] = { 1, 10 }; 667 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi", 668 gpu_axi_parents, gpu_axi_table, 669 0x4f8, 670 0, 4, /* M */ 671 24, 4, /* mux */ 672 BIT(31), /* gate */ 673 CLK_SET_RATE_PARENT); 674 675 static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500, 676 0, 4, BIT(31), 0); 677 678 static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio", 679 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 680 681 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi", 682 mod0_default_parents, 0x508, 683 0, 4, /* M */ 684 24, 4, /* mux */ 685 BIT(31), /* gate */ 686 0); 687 688 static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" }; 689 static const u8 gpadc_table[] = { 0, 4, 7 }; 690 static struct ccu_mp gpadc_clk = { 691 .enable = BIT(31), 692 .m = _SUNXI_CCU_DIV(0, 4), 693 .p = _SUNXI_CCU_DIV(16, 2), 694 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, gpadc_table), 695 .common = { 696 .reg = 0x50c, 697 .hw.init = CLK_HW_INIT_PARENTS("gpadc", 698 gpadc_parents, 699 &ccu_mp_ops, 700 0), 701 }, 702 }; 703 704 static const char * const cir_tx_parents[] = { "osc24M", "osc32k" }; 705 static const u8 cir_tx_table[] = { 0, 7 }; 706 static struct ccu_mp cir_tx_clk = { 707 .enable = BIT(31), 708 .m = _SUNXI_CCU_DIV(0, 4), 709 .p = _SUNXI_CCU_DIV(16, 2), 710 .mux = _SUNXI_CCU_MUX_TABLE(24, 4, cir_tx_table), 711 .common = { 712 .reg = 0x510, 713 .hw.init = CLK_HW_INIT_PARENTS("cir-tx", 714 cir_tx_parents, 715 &ccu_mp_ops, 716 0), 717 }, 718 }; 719 720 /* AHB0 bus gates */ 721 static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0", 722 0x580, BIT(0), 0); 723 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0", 724 0x580, BIT(1), 0); 725 static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0", 726 0x580, BIT(3), 0); 727 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0", 728 0x580, BIT(5), 0); 729 static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0", 730 0x580, BIT(8), 0); 731 static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0", 732 0x580, BIT(12), 0); 733 static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0", 734 0x580, BIT(13), 0); 735 static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0", 736 0x580, BIT(14), 0); 737 static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0", 738 0x580, BIT(15), 0); 739 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0", 740 0x580, BIT(16), 0); 741 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0", 742 0x580, BIT(18), 0); 743 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0", 744 0x580, BIT(20), 0); 745 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0", 746 0x580, BIT(21), 0); 747 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0", 748 0x580, BIT(22), 0); 749 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0", 750 0x580, BIT(23), 0); 751 752 /* AHB1 bus gates */ 753 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 754 0x584, BIT(0), 0); 755 static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1", 756 0x584, BIT(1), 0); 757 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1", 758 0x584, BIT(17), 0); 759 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 760 0x584, BIT(21), 0); 761 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 762 0x584, BIT(22), 0); 763 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 764 0x584, BIT(23), 0); 765 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 766 0x584, BIT(24), 0); 767 768 /* AHB2 bus gates */ 769 static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2", 770 0x588, BIT(0), 0); 771 static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2", 772 0x588, BIT(1), 0); 773 static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2", 774 0x588, BIT(2), 0); 775 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2", 776 0x588, BIT(4), 0); 777 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2", 778 0x588, BIT(5), 0); 779 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2", 780 0x588, BIT(7), 0); 781 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2", 782 0x588, BIT(8), 0); 783 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2", 784 0x588, BIT(11), 0); 785 786 /* APB0 bus gates */ 787 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0", 788 0x590, BIT(1), 0); 789 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0", 790 0x590, BIT(5), 0); 791 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0", 792 0x590, BIT(11), 0); 793 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0", 794 0x590, BIT(12), 0); 795 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0", 796 0x590, BIT(13), 0); 797 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0", 798 0x590, BIT(15), 0); 799 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0", 800 0x590, BIT(17), 0); 801 static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0", 802 0x590, BIT(18), 0); 803 static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0", 804 0x590, BIT(19), 0); 805 806 /* APB1 bus gates */ 807 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1", 808 0x594, BIT(0), 0); 809 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1", 810 0x594, BIT(1), 0); 811 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1", 812 0x594, BIT(2), 0); 813 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1", 814 0x594, BIT(3), 0); 815 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1", 816 0x594, BIT(4), 0); 817 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1", 818 0x594, BIT(16), 0); 819 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1", 820 0x594, BIT(17), 0); 821 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1", 822 0x594, BIT(18), 0); 823 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1", 824 0x594, BIT(19), 0); 825 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1", 826 0x594, BIT(20), 0); 827 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1", 828 0x594, BIT(21), 0); 829 830 static struct ccu_common *sun9i_a80_ccu_clks[] = { 831 &pll_c0cpux_clk.common, 832 &pll_c1cpux_clk.common, 833 &pll_audio_clk.common, 834 &pll_periph0_clk.common, 835 &pll_ve_clk.common, 836 &pll_ddr_clk.common, 837 &pll_video0_clk.common, 838 &pll_video1_clk.common, 839 &pll_gpu_clk.common, 840 &pll_de_clk.common, 841 &pll_isp_clk.common, 842 &pll_periph1_clk.common, 843 &c0cpux_clk.common, 844 &c1cpux_clk.common, 845 &atb0_clk.common, 846 &axi0_clk.common, 847 &atb1_clk.common, 848 &axi1_clk.common, 849 >bus_clk.common, 850 &ahb0_clk.common, 851 &ahb1_clk.common, 852 &ahb2_clk.common, 853 &apb0_clk.common, 854 &apb1_clk.common, 855 &cci400_clk.common, 856 &ats_clk.common, 857 &trace_clk.common, 858 859 &out_a_clk.common, 860 &out_b_clk.common, 861 862 /* module clocks */ 863 &nand0_0_clk.common, 864 &nand0_1_clk.common, 865 &nand1_0_clk.common, 866 &nand1_1_clk.common, 867 &mmc0_clk.common, 868 &mmc0_sample_clk.common, 869 &mmc0_output_clk.common, 870 &mmc1_clk.common, 871 &mmc1_sample_clk.common, 872 &mmc1_output_clk.common, 873 &mmc2_clk.common, 874 &mmc2_sample_clk.common, 875 &mmc2_output_clk.common, 876 &mmc3_clk.common, 877 &mmc3_sample_clk.common, 878 &mmc3_output_clk.common, 879 &ts_clk.common, 880 &ss_clk.common, 881 &spi0_clk.common, 882 &spi1_clk.common, 883 &spi2_clk.common, 884 &spi3_clk.common, 885 &i2s0_clk.common, 886 &i2s1_clk.common, 887 &spdif_clk.common, 888 &sdram_clk.common, 889 &de_clk.common, 890 &edp_clk.common, 891 &mp_clk.common, 892 &lcd0_clk.common, 893 &lcd1_clk.common, 894 &mipi_dsi0_clk.common, 895 &mipi_dsi1_clk.common, 896 &hdmi_clk.common, 897 &hdmi_slow_clk.common, 898 &mipi_csi_clk.common, 899 &csi_isp_clk.common, 900 &csi_misc_clk.common, 901 &csi0_mclk_clk.common, 902 &csi1_mclk_clk.common, 903 &fd_clk.common, 904 &ve_clk.common, 905 &avs_clk.common, 906 &gpu_core_clk.common, 907 &gpu_memory_clk.common, 908 &gpu_axi_clk.common, 909 &sata_clk.common, 910 &ac97_clk.common, 911 &mipi_hsi_clk.common, 912 &gpadc_clk.common, 913 &cir_tx_clk.common, 914 915 /* AHB0 bus gates */ 916 &bus_fd_clk.common, 917 &bus_ve_clk.common, 918 &bus_gpu_ctrl_clk.common, 919 &bus_ss_clk.common, 920 &bus_mmc_clk.common, 921 &bus_nand0_clk.common, 922 &bus_nand1_clk.common, 923 &bus_sdram_clk.common, 924 &bus_mipi_hsi_clk.common, 925 &bus_sata_clk.common, 926 &bus_ts_clk.common, 927 &bus_spi0_clk.common, 928 &bus_spi1_clk.common, 929 &bus_spi2_clk.common, 930 &bus_spi3_clk.common, 931 932 /* AHB1 bus gates */ 933 &bus_otg_clk.common, 934 &bus_usb_clk.common, 935 &bus_gmac_clk.common, 936 &bus_msgbox_clk.common, 937 &bus_spinlock_clk.common, 938 &bus_hstimer_clk.common, 939 &bus_dma_clk.common, 940 941 /* AHB2 bus gates */ 942 &bus_lcd0_clk.common, 943 &bus_lcd1_clk.common, 944 &bus_edp_clk.common, 945 &bus_csi_clk.common, 946 &bus_hdmi_clk.common, 947 &bus_de_clk.common, 948 &bus_mp_clk.common, 949 &bus_mipi_dsi_clk.common, 950 951 /* APB0 bus gates */ 952 &bus_spdif_clk.common, 953 &bus_pio_clk.common, 954 &bus_ac97_clk.common, 955 &bus_i2s0_clk.common, 956 &bus_i2s1_clk.common, 957 &bus_lradc_clk.common, 958 &bus_gpadc_clk.common, 959 &bus_twd_clk.common, 960 &bus_cir_tx_clk.common, 961 962 /* APB1 bus gates */ 963 &bus_i2c0_clk.common, 964 &bus_i2c1_clk.common, 965 &bus_i2c2_clk.common, 966 &bus_i2c3_clk.common, 967 &bus_i2c4_clk.common, 968 &bus_uart0_clk.common, 969 &bus_uart1_clk.common, 970 &bus_uart2_clk.common, 971 &bus_uart3_clk.common, 972 &bus_uart4_clk.common, 973 &bus_uart5_clk.common, 974 }; 975 976 static struct clk_hw_onecell_data sun9i_a80_hw_clks = { 977 .hws = { 978 [CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw, 979 [CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw, 980 [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw, 981 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 982 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 983 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, 984 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 985 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 986 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 987 [CLK_PLL_DE] = &pll_de_clk.common.hw, 988 [CLK_PLL_ISP] = &pll_isp_clk.common.hw, 989 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 990 [CLK_C0CPUX] = &c0cpux_clk.common.hw, 991 [CLK_C1CPUX] = &c1cpux_clk.common.hw, 992 [CLK_ATB0] = &atb0_clk.common.hw, 993 [CLK_AXI0] = &axi0_clk.common.hw, 994 [CLK_ATB1] = &atb1_clk.common.hw, 995 [CLK_AXI1] = &axi1_clk.common.hw, 996 [CLK_GTBUS] = >bus_clk.common.hw, 997 [CLK_AHB0] = &ahb0_clk.common.hw, 998 [CLK_AHB1] = &ahb1_clk.common.hw, 999 [CLK_AHB2] = &ahb2_clk.common.hw, 1000 [CLK_APB0] = &apb0_clk.common.hw, 1001 [CLK_APB1] = &apb1_clk.common.hw, 1002 [CLK_CCI400] = &cci400_clk.common.hw, 1003 [CLK_ATS] = &ats_clk.common.hw, 1004 [CLK_TRACE] = &trace_clk.common.hw, 1005 1006 [CLK_OUT_A] = &out_a_clk.common.hw, 1007 [CLK_OUT_B] = &out_b_clk.common.hw, 1008 1009 [CLK_NAND0_0] = &nand0_0_clk.common.hw, 1010 [CLK_NAND0_1] = &nand0_1_clk.common.hw, 1011 [CLK_NAND1_0] = &nand1_0_clk.common.hw, 1012 [CLK_NAND1_1] = &nand1_1_clk.common.hw, 1013 [CLK_MMC0] = &mmc0_clk.common.hw, 1014 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 1015 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 1016 [CLK_MMC1] = &mmc1_clk.common.hw, 1017 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 1018 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 1019 [CLK_MMC2] = &mmc2_clk.common.hw, 1020 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 1021 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 1022 [CLK_MMC3] = &mmc3_clk.common.hw, 1023 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw, 1024 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw, 1025 [CLK_TS] = &ts_clk.common.hw, 1026 [CLK_SS] = &ss_clk.common.hw, 1027 [CLK_SPI0] = &spi0_clk.common.hw, 1028 [CLK_SPI1] = &spi1_clk.common.hw, 1029 [CLK_SPI2] = &spi2_clk.common.hw, 1030 [CLK_SPI3] = &spi3_clk.common.hw, 1031 [CLK_I2S0] = &i2s0_clk.common.hw, 1032 [CLK_I2S1] = &i2s1_clk.common.hw, 1033 [CLK_SPDIF] = &spdif_clk.common.hw, 1034 [CLK_SDRAM] = &sdram_clk.common.hw, 1035 [CLK_DE] = &de_clk.common.hw, 1036 [CLK_EDP] = &edp_clk.common.hw, 1037 [CLK_MP] = &mp_clk.common.hw, 1038 [CLK_LCD0] = &lcd0_clk.common.hw, 1039 [CLK_LCD1] = &lcd1_clk.common.hw, 1040 [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw, 1041 [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw, 1042 [CLK_HDMI] = &hdmi_clk.common.hw, 1043 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 1044 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, 1045 [CLK_CSI_ISP] = &csi_isp_clk.common.hw, 1046 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 1047 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 1048 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 1049 [CLK_FD] = &fd_clk.common.hw, 1050 [CLK_VE] = &ve_clk.common.hw, 1051 [CLK_AVS] = &avs_clk.common.hw, 1052 [CLK_GPU_CORE] = &gpu_core_clk.common.hw, 1053 [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw, 1054 [CLK_GPU_AXI] = &gpu_axi_clk.common.hw, 1055 [CLK_SATA] = &sata_clk.common.hw, 1056 [CLK_AC97] = &ac97_clk.common.hw, 1057 [CLK_MIPI_HSI] = &mipi_hsi_clk.common.hw, 1058 [CLK_GPADC] = &gpadc_clk.common.hw, 1059 [CLK_CIR_TX] = &cir_tx_clk.common.hw, 1060 1061 [CLK_BUS_FD] = &bus_fd_clk.common.hw, 1062 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 1063 [CLK_BUS_GPU_CTRL] = &bus_gpu_ctrl_clk.common.hw, 1064 [CLK_BUS_SS] = &bus_ss_clk.common.hw, 1065 [CLK_BUS_MMC] = &bus_mmc_clk.common.hw, 1066 [CLK_BUS_NAND0] = &bus_nand0_clk.common.hw, 1067 [CLK_BUS_NAND1] = &bus_nand1_clk.common.hw, 1068 [CLK_BUS_SDRAM] = &bus_sdram_clk.common.hw, 1069 [CLK_BUS_MIPI_HSI] = &bus_mipi_hsi_clk.common.hw, 1070 [CLK_BUS_SATA] = &bus_sata_clk.common.hw, 1071 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 1072 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 1073 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 1074 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, 1075 [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw, 1076 1077 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 1078 [CLK_BUS_USB] = &bus_usb_clk.common.hw, 1079 [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw, 1080 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 1081 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 1082 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 1083 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 1084 1085 [CLK_BUS_LCD0] = &bus_lcd0_clk.common.hw, 1086 [CLK_BUS_LCD1] = &bus_lcd1_clk.common.hw, 1087 [CLK_BUS_EDP] = &bus_edp_clk.common.hw, 1088 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 1089 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 1090 [CLK_BUS_DE] = &bus_de_clk.common.hw, 1091 [CLK_BUS_MP] = &bus_mp_clk.common.hw, 1092 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 1093 1094 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 1095 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 1096 [CLK_BUS_AC97] = &bus_ac97_clk.common.hw, 1097 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 1098 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 1099 [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw, 1100 [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw, 1101 [CLK_BUS_TWD] = &bus_twd_clk.common.hw, 1102 [CLK_BUS_CIR_TX] = &bus_cir_tx_clk.common.hw, 1103 1104 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 1105 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 1106 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 1107 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 1108 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, 1109 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 1110 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 1111 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 1112 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 1113 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 1114 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, 1115 }, 1116 .num = CLK_NUMBER, 1117 }; 1118 1119 static struct ccu_reset_map sun9i_a80_ccu_resets[] = { 1120 /* AHB0 reset controls */ 1121 [RST_BUS_FD] = { 0x5a0, BIT(0) }, 1122 [RST_BUS_VE] = { 0x5a0, BIT(1) }, 1123 [RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) }, 1124 [RST_BUS_SS] = { 0x5a0, BIT(5) }, 1125 [RST_BUS_MMC] = { 0x5a0, BIT(8) }, 1126 [RST_BUS_NAND0] = { 0x5a0, BIT(12) }, 1127 [RST_BUS_NAND1] = { 0x5a0, BIT(13) }, 1128 [RST_BUS_SDRAM] = { 0x5a0, BIT(14) }, 1129 [RST_BUS_SATA] = { 0x5a0, BIT(16) }, 1130 [RST_BUS_TS] = { 0x5a0, BIT(18) }, 1131 [RST_BUS_SPI0] = { 0x5a0, BIT(20) }, 1132 [RST_BUS_SPI1] = { 0x5a0, BIT(21) }, 1133 [RST_BUS_SPI2] = { 0x5a0, BIT(22) }, 1134 [RST_BUS_SPI3] = { 0x5a0, BIT(23) }, 1135 1136 /* AHB1 reset controls */ 1137 [RST_BUS_OTG] = { 0x5a4, BIT(0) }, 1138 [RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) }, 1139 [RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) }, 1140 [RST_BUS_GMAC] = { 0x5a4, BIT(17) }, 1141 [RST_BUS_MSGBOX] = { 0x5a4, BIT(21) }, 1142 [RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) }, 1143 [RST_BUS_HSTIMER] = { 0x5a4, BIT(23) }, 1144 [RST_BUS_DMA] = { 0x5a4, BIT(24) }, 1145 1146 /* AHB2 reset controls */ 1147 [RST_BUS_LCD0] = { 0x5a8, BIT(0) }, 1148 [RST_BUS_LCD1] = { 0x5a8, BIT(1) }, 1149 [RST_BUS_EDP] = { 0x5a8, BIT(2) }, 1150 [RST_BUS_LVDS] = { 0x5a8, BIT(3) }, 1151 [RST_BUS_CSI] = { 0x5a8, BIT(4) }, 1152 [RST_BUS_HDMI0] = { 0x5a8, BIT(5) }, 1153 [RST_BUS_HDMI1] = { 0x5a8, BIT(6) }, 1154 [RST_BUS_DE] = { 0x5a8, BIT(7) }, 1155 [RST_BUS_MP] = { 0x5a8, BIT(8) }, 1156 [RST_BUS_GPU] = { 0x5a8, BIT(9) }, 1157 [RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) }, 1158 1159 /* APB0 reset controls */ 1160 [RST_BUS_SPDIF] = { 0x5b0, BIT(1) }, 1161 [RST_BUS_AC97] = { 0x5b0, BIT(11) }, 1162 [RST_BUS_I2S0] = { 0x5b0, BIT(12) }, 1163 [RST_BUS_I2S1] = { 0x5b0, BIT(13) }, 1164 [RST_BUS_LRADC] = { 0x5b0, BIT(15) }, 1165 [RST_BUS_GPADC] = { 0x5b0, BIT(17) }, 1166 [RST_BUS_CIR_TX] = { 0x5b0, BIT(19) }, 1167 1168 /* APB1 reset controls */ 1169 [RST_BUS_I2C0] = { 0x5b4, BIT(0) }, 1170 [RST_BUS_I2C1] = { 0x5b4, BIT(1) }, 1171 [RST_BUS_I2C2] = { 0x5b4, BIT(2) }, 1172 [RST_BUS_I2C3] = { 0x5b4, BIT(3) }, 1173 [RST_BUS_I2C4] = { 0x5b4, BIT(4) }, 1174 [RST_BUS_UART0] = { 0x5b4, BIT(16) }, 1175 [RST_BUS_UART1] = { 0x5b4, BIT(17) }, 1176 [RST_BUS_UART2] = { 0x5b4, BIT(18) }, 1177 [RST_BUS_UART3] = { 0x5b4, BIT(19) }, 1178 [RST_BUS_UART4] = { 0x5b4, BIT(20) }, 1179 [RST_BUS_UART5] = { 0x5b4, BIT(21) }, 1180 }; 1181 1182 static const struct sunxi_ccu_desc sun9i_a80_ccu_desc = { 1183 .ccu_clks = sun9i_a80_ccu_clks, 1184 .num_ccu_clks = ARRAY_SIZE(sun9i_a80_ccu_clks), 1185 1186 .hw_clks = &sun9i_a80_hw_clks, 1187 1188 .resets = sun9i_a80_ccu_resets, 1189 .num_resets = ARRAY_SIZE(sun9i_a80_ccu_resets), 1190 }; 1191 1192 #define SUN9I_A80_PLL_P_SHIFT 16 1193 #define SUN9I_A80_PLL_N_SHIFT 8 1194 #define SUN9I_A80_PLL_N_WIDTH 8 1195 1196 static void sun9i_a80_cpu_pll_fixup(void __iomem *reg) 1197 { 1198 u32 val = readl(reg); 1199 1200 /* bail out if P divider is not used */ 1201 if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT))) 1202 return; 1203 1204 /* 1205 * If P is used, output should be less than 288 MHz. When we 1206 * set P to 1, we should also decrease the multiplier so the 1207 * output doesn't go out of range, but not too much such that 1208 * the multiplier stays above 12, the minimal operation value. 1209 * 1210 * To keep it simple, set the multiplier to 17, the reset value. 1211 */ 1212 val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1, 1213 SUN9I_A80_PLL_N_SHIFT); 1214 val |= 17 << SUN9I_A80_PLL_N_SHIFT; 1215 1216 /* And clear P */ 1217 val &= ~BIT(SUN9I_A80_PLL_P_SHIFT); 1218 1219 writel(val, reg); 1220 } 1221 1222 static int sun9i_a80_ccu_probe(struct platform_device *pdev) 1223 { 1224 struct resource *res; 1225 void __iomem *reg; 1226 u32 val; 1227 1228 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1229 reg = devm_ioremap_resource(&pdev->dev, res); 1230 if (IS_ERR(reg)) 1231 return PTR_ERR(reg); 1232 1233 /* Enforce d1 = 0, d2 = 0 for Audio PLL */ 1234 val = readl(reg + SUN9I_A80_PLL_AUDIO_REG); 1235 val &= (BIT(16) & BIT(18)); 1236 writel(val, reg + SUN9I_A80_PLL_AUDIO_REG); 1237 1238 /* Enforce P = 1 for both CPU cluster PLLs */ 1239 sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C0CPUX_REG); 1240 sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C1CPUX_REG); 1241 1242 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc); 1243 } 1244 1245 static const struct of_device_id sun9i_a80_ccu_ids[] = { 1246 { .compatible = "allwinner,sun9i-a80-ccu" }, 1247 { } 1248 }; 1249 1250 static struct platform_driver sun9i_a80_ccu_driver = { 1251 .probe = sun9i_a80_ccu_probe, 1252 .driver = { 1253 .name = "sun9i-a80-ccu", 1254 .of_match_table = sun9i_a80_ccu_ids, 1255 }, 1256 }; 1257 builtin_platform_driver(sun9i_a80_ccu_driver); 1258