1 /* 2 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of_address.h> 17 #include <linux/platform_device.h> 18 19 #include "ccu_common.h" 20 #include "ccu_gate.h" 21 #include "ccu_reset.h" 22 23 #include "ccu-sun9i-a80-usb.h" 24 25 static const struct clk_parent_data clk_parent_hosc[] = { 26 { .fw_name = "hosc" }, 27 }; 28 29 static const struct clk_parent_data clk_parent_bus[] = { 30 { .fw_name = "bus" }, 31 }; 32 33 static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0); 34 static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0); 35 static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0); 36 static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0); 37 static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0); 38 39 static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0); 40 static SUNXI_CCU_GATE_DATA(usb1_hsic_clk, "usb1-hsic", clk_parent_hosc, 0x4, BIT(2), 0); 41 static SUNXI_CCU_GATE_DATA(usb1_phy_clk, "usb1-phy", clk_parent_hosc, 0x4, BIT(3), 0); 42 static SUNXI_CCU_GATE_DATA(usb2_hsic_clk, "usb2-hsic", clk_parent_hosc, 0x4, BIT(4), 0); 43 static SUNXI_CCU_GATE_DATA(usb2_phy_clk, "usb2-phy", clk_parent_hosc, 0x4, BIT(5), 0); 44 static SUNXI_CCU_GATE_DATA(usb_hsic_clk, "usb-hsic", clk_parent_hosc, 0x4, BIT(10), 0); 45 46 static struct ccu_common *sun9i_a80_usb_clks[] = { 47 &bus_hci0_clk.common, 48 &usb_ohci0_clk.common, 49 &bus_hci1_clk.common, 50 &bus_hci2_clk.common, 51 &usb_ohci2_clk.common, 52 53 &usb0_phy_clk.common, 54 &usb1_hsic_clk.common, 55 &usb1_phy_clk.common, 56 &usb2_hsic_clk.common, 57 &usb2_phy_clk.common, 58 &usb_hsic_clk.common, 59 }; 60 61 static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = { 62 .hws = { 63 [CLK_BUS_HCI0] = &bus_hci0_clk.common.hw, 64 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 65 [CLK_BUS_HCI1] = &bus_hci1_clk.common.hw, 66 [CLK_BUS_HCI2] = &bus_hci2_clk.common.hw, 67 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, 68 69 [CLK_USB0_PHY] = &usb0_phy_clk.common.hw, 70 [CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw, 71 [CLK_USB1_PHY] = &usb1_phy_clk.common.hw, 72 [CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw, 73 [CLK_USB2_PHY] = &usb2_phy_clk.common.hw, 74 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 75 }, 76 .num = CLK_NUMBER, 77 }; 78 79 static struct ccu_reset_map sun9i_a80_usb_resets[] = { 80 [RST_USB0_HCI] = { 0x0, BIT(17) }, 81 [RST_USB1_HCI] = { 0x0, BIT(18) }, 82 [RST_USB2_HCI] = { 0x0, BIT(19) }, 83 84 [RST_USB0_PHY] = { 0x4, BIT(17) }, 85 [RST_USB1_HSIC] = { 0x4, BIT(18) }, 86 [RST_USB1_PHY] = { 0x4, BIT(19) }, 87 [RST_USB2_HSIC] = { 0x4, BIT(20) }, 88 [RST_USB2_PHY] = { 0x4, BIT(21) }, 89 }; 90 91 static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = { 92 .ccu_clks = sun9i_a80_usb_clks, 93 .num_ccu_clks = ARRAY_SIZE(sun9i_a80_usb_clks), 94 95 .hw_clks = &sun9i_a80_usb_hw_clks, 96 97 .resets = sun9i_a80_usb_resets, 98 .num_resets = ARRAY_SIZE(sun9i_a80_usb_resets), 99 }; 100 101 static int sun9i_a80_usb_clk_probe(struct platform_device *pdev) 102 { 103 struct resource *res; 104 struct clk *bus_clk; 105 void __iomem *reg; 106 int ret; 107 108 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 109 reg = devm_ioremap_resource(&pdev->dev, res); 110 if (IS_ERR(reg)) 111 return PTR_ERR(reg); 112 113 bus_clk = devm_clk_get(&pdev->dev, "bus"); 114 if (IS_ERR(bus_clk)) { 115 ret = PTR_ERR(bus_clk); 116 if (ret != -EPROBE_DEFER) 117 dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret); 118 return ret; 119 } 120 121 /* The bus clock needs to be enabled for us to access the registers */ 122 ret = clk_prepare_enable(bus_clk); 123 if (ret) { 124 dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret); 125 return ret; 126 } 127 128 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, 129 &sun9i_a80_usb_clk_desc); 130 if (ret) 131 goto err_disable_clk; 132 133 return 0; 134 135 err_disable_clk: 136 clk_disable_unprepare(bus_clk); 137 return ret; 138 } 139 140 static const struct of_device_id sun9i_a80_usb_clk_ids[] = { 141 { .compatible = "allwinner,sun9i-a80-usb-clks" }, 142 { } 143 }; 144 145 static struct platform_driver sun9i_a80_usb_clk_driver = { 146 .probe = sun9i_a80_usb_clk_probe, 147 .driver = { 148 .name = "sun9i-a80-usb-clks", 149 .of_match_table = sun9i_a80_usb_clk_ids, 150 }, 151 }; 152 builtin_platform_driver(sun9i_a80_usb_clk_driver); 153