1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
4  *
5  * Based on ccu-sun8i-h3.h, which is:
6  * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
7  */
8 
9 #ifndef _CCU_SUN8I_V3S_H_
10 #define _CCU_SUN8I_V3S_H_
11 
12 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
13 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
14 
15 #define CLK_PLL_CPU		0
16 #define CLK_PLL_AUDIO_BASE	1
17 #define CLK_PLL_AUDIO		2
18 #define CLK_PLL_AUDIO_2X	3
19 #define CLK_PLL_AUDIO_4X	4
20 #define CLK_PLL_AUDIO_8X	5
21 #define CLK_PLL_VIDEO		6
22 #define CLK_PLL_VE		7
23 #define CLK_PLL_DDR0		8
24 #define CLK_PLL_PERIPH0		9
25 #define CLK_PLL_PERIPH0_2X	10
26 #define CLK_PLL_ISP		11
27 #define CLK_PLL_PERIPH1		12
28 /* Reserve one number for not implemented and not used PLL_DDR1 */
29 
30 /* The CPU clock is exported */
31 
32 #define CLK_AXI			15
33 #define CLK_AHB1		16
34 #define CLK_APB1		17
35 #define CLK_APB2		18
36 #define CLK_AHB2		19
37 
38 /* All the bus gates are exported */
39 
40 /* The first bunch of module clocks are exported */
41 
42 #define CLK_DRAM		58
43 
44 /* All the DRAM gates are exported */
45 
46 /* Some more module clocks are exported */
47 
48 #define CLK_MBUS		72
49 
50 /* And the GPU module clock is exported */
51 
52 #define CLK_PLL_DDR1		74
53 
54 #endif /* _CCU_SUN8I_V3S_H_ */
55