1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 4 * 5 * Based on ccu-sun8i-h3.c, which is: 6 * Copyright (c) 2016 Maxime Ripard. All rights reserved. 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/io.h> 11 #include <linux/of_address.h> 12 13 #include "ccu_common.h" 14 #include "ccu_reset.h" 15 16 #include "ccu_div.h" 17 #include "ccu_gate.h" 18 #include "ccu_mp.h" 19 #include "ccu_mult.h" 20 #include "ccu_nk.h" 21 #include "ccu_nkm.h" 22 #include "ccu_nkmp.h" 23 #include "ccu_nm.h" 24 #include "ccu_phase.h" 25 26 #include "ccu-sun8i-v3s.h" 27 28 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", 29 "osc24M", 0x000, 30 8, 5, /* N */ 31 4, 2, /* K */ 32 0, 2, /* M */ 33 16, 2, /* P */ 34 BIT(31), /* gate */ 35 BIT(28), /* lock */ 36 0); 37 38 /* 39 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 40 * the base (2x, 4x and 8x), and one variable divider (the one true 41 * pll audio). 42 * 43 * We don't have any need for the variable divider for now, so we just 44 * hardcode it to match with the clock names 45 */ 46 #define SUN8I_V3S_PLL_AUDIO_REG 0x008 47 48 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 49 "osc24M", 0x008, 50 8, 7, /* N */ 51 0, 5, /* M */ 52 BIT(31), /* gate */ 53 BIT(28), /* lock */ 54 0); 55 56 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 57 "osc24M", 0x0010, 58 8, 7, /* N */ 59 0, 4, /* M */ 60 BIT(24), /* frac enable */ 61 BIT(25), /* frac select */ 62 270000000, /* frac rate 0 */ 63 297000000, /* frac rate 1 */ 64 BIT(31), /* gate */ 65 BIT(28), /* lock */ 66 0); 67 68 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 69 "osc24M", 0x0018, 70 8, 7, /* N */ 71 0, 4, /* M */ 72 BIT(24), /* frac enable */ 73 BIT(25), /* frac select */ 74 270000000, /* frac rate 0 */ 75 297000000, /* frac rate 1 */ 76 BIT(31), /* gate */ 77 BIT(28), /* lock */ 78 0); 79 80 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 81 "osc24M", 0x020, 82 8, 5, /* N */ 83 4, 2, /* K */ 84 0, 2, /* M */ 85 BIT(31), /* gate */ 86 BIT(28), /* lock */ 87 0); 88 89 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", 90 "osc24M", 0x028, 91 8, 5, /* N */ 92 4, 2, /* K */ 93 BIT(31), /* gate */ 94 BIT(28), /* lock */ 95 2, /* post-div */ 96 0); 97 98 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp", 99 "osc24M", 0x002c, 100 8, 7, /* N */ 101 0, 4, /* M */ 102 BIT(24), /* frac enable */ 103 BIT(25), /* frac select */ 104 270000000, /* frac rate 0 */ 105 297000000, /* frac rate 1 */ 106 BIT(31), /* gate */ 107 BIT(28), /* lock */ 108 0); 109 110 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", 111 "osc24M", 0x044, 112 8, 5, /* N */ 113 4, 2, /* K */ 114 BIT(31), /* gate */ 115 BIT(28), /* lock */ 116 2, /* post-div */ 117 0); 118 119 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 120 "osc24M", 0x04c, 121 8, 7, /* N */ 122 0, 2, /* M */ 123 BIT(31), /* gate */ 124 BIT(28), /* lock */ 125 0); 126 127 static const char * const cpu_parents[] = { "osc32k", "osc24M", 128 "pll-cpu", "pll-cpu" }; 129 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 130 0x050, 16, 2, CLK_IS_CRITICAL); 131 132 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0); 133 134 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 135 "axi", "pll-periph0" }; 136 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 137 { .index = 3, .shift = 6, .width = 2 }, 138 }; 139 static struct ccu_div ahb1_clk = { 140 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 141 142 .mux = { 143 .shift = 12, 144 .width = 2, 145 146 .var_predivs = ahb1_predivs, 147 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 148 }, 149 150 .common = { 151 .reg = 0x054, 152 .features = CCU_FEATURE_VARIABLE_PREDIV, 153 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 154 ahb1_parents, 155 &ccu_div_ops, 156 0), 157 }, 158 }; 159 160 static struct clk_div_table apb1_div_table[] = { 161 { .val = 0, .div = 2 }, 162 { .val = 1, .div = 2 }, 163 { .val = 2, .div = 4 }, 164 { .val = 3, .div = 8 }, 165 { /* Sentinel */ }, 166 }; 167 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 168 0x054, 8, 2, apb1_div_table, 0); 169 170 static const char * const apb2_parents[] = { "osc32k", "osc24M", 171 "pll-periph0", "pll-periph0" }; 172 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 173 0, 5, /* M */ 174 16, 2, /* P */ 175 24, 2, /* mux */ 176 0); 177 178 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" }; 179 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { 180 { .index = 1, .div = 2 }, 181 }; 182 static struct ccu_mux ahb2_clk = { 183 .mux = { 184 .shift = 0, 185 .width = 1, 186 .fixed_predivs = ahb2_fixed_predivs, 187 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), 188 }, 189 190 .common = { 191 .reg = 0x05c, 192 .features = CCU_FEATURE_FIXED_PREDIV, 193 .hw.init = CLK_HW_INIT_PARENTS("ahb2", 194 ahb2_parents, 195 &ccu_mux_ops, 196 0), 197 }, 198 }; 199 200 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 201 0x060, BIT(5), 0); 202 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 203 0x060, BIT(6), 0); 204 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 205 0x060, BIT(8), 0); 206 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 207 0x060, BIT(9), 0); 208 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 209 0x060, BIT(10), 0); 210 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 211 0x060, BIT(14), 0); 212 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 213 0x060, BIT(17), 0); 214 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 215 0x060, BIT(19), 0); 216 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 217 0x060, BIT(20), 0); 218 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 219 0x060, BIT(24), 0); 220 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 221 0x060, BIT(26), 0); 222 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 223 0x060, BIT(29), 0); 224 225 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 226 0x064, BIT(0), 0); 227 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 228 0x064, BIT(4), 0); 229 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 230 0x064, BIT(8), 0); 231 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 232 0x064, BIT(12), 0); 233 234 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 235 0x068, BIT(0), 0); 236 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 237 0x068, BIT(5), 0); 238 239 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 240 0x06c, BIT(0), 0); 241 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 242 0x06c, BIT(1), 0); 243 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 244 0x06c, BIT(16), 0); 245 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 246 0x06c, BIT(17), 0); 247 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 248 0x06c, BIT(18), 0); 249 250 static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1", 251 0x070, BIT(0), 0); 252 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 253 0x070, BIT(7), 0); 254 255 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 256 "pll-periph1" }; 257 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 258 0, 4, /* M */ 259 16, 2, /* P */ 260 24, 2, /* mux */ 261 BIT(31), /* gate */ 262 0); 263 264 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 265 0x088, 20, 3, 0); 266 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 267 0x088, 8, 3, 0); 268 269 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 270 0, 4, /* M */ 271 16, 2, /* P */ 272 24, 2, /* mux */ 273 BIT(31), /* gate */ 274 0); 275 276 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 277 0x08c, 20, 3, 0); 278 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 279 0x08c, 8, 3, 0); 280 281 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 282 0, 4, /* M */ 283 16, 2, /* P */ 284 24, 2, /* mux */ 285 BIT(31), /* gate */ 286 0); 287 288 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", 289 0x090, 20, 3, 0); 290 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", 291 0x090, 8, 3, 0); 292 293 static const char * const ce_parents[] = { "osc24M", "pll-periph0", }; 294 295 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c, 296 0, 4, /* M */ 297 16, 2, /* P */ 298 24, 2, /* mux */ 299 BIT(31), /* gate */ 300 0); 301 302 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 303 0, 4, /* M */ 304 16, 2, /* P */ 305 24, 2, /* mux */ 306 BIT(31), /* gate */ 307 0); 308 309 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 310 0x0cc, BIT(8), 0); 311 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 312 0x0cc, BIT(16), 0); 313 314 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1", 315 "pll-periph0-2x" }; 316 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 317 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); 318 319 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 320 0x100, BIT(0), 0); 321 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 322 0x100, BIT(1), 0); 323 static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram", 324 0x100, BIT(17), 0); 325 static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", 326 0x100, BIT(18), 0); 327 328 static const char * const de_parents[] = { "pll-video", "pll-periph0" }; 329 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 330 0x104, 0, 4, 24, 2, BIT(31), 331 CLK_SET_RATE_PARENT); 332 333 static const char * const tcon_parents[] = { "pll-video" }; 334 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, 335 0x118, 0, 4, 24, 3, BIT(31), 0); 336 337 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 338 0x130, BIT(31), 0); 339 340 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", 341 "pll-periph0", "pll-periph1" }; 342 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 343 0x130, 0, 5, 8, 3, BIT(15), 0); 344 345 static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" }; 346 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents, 347 0x134, 16, 4, 24, 3, BIT(31), 0); 348 349 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents, 350 0x134, 0, 5, 8, 3, BIT(15), 0); 351 352 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 353 0x13c, 16, 3, BIT(31), 0); 354 355 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 356 0x140, BIT(31), CLK_SET_RATE_PARENT); 357 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 358 0x144, BIT(31), 0); 359 360 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 361 "pll-ddr" }; 362 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 363 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 364 365 static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0", 366 "pll-isp" }; 367 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents, 368 0x16c, 0, 3, 24, 2, BIT(31), 0); 369 370 static struct ccu_common *sun8i_v3s_ccu_clks[] = { 371 &pll_cpu_clk.common, 372 &pll_audio_base_clk.common, 373 &pll_video_clk.common, 374 &pll_ve_clk.common, 375 &pll_ddr0_clk.common, 376 &pll_periph0_clk.common, 377 &pll_isp_clk.common, 378 &pll_periph1_clk.common, 379 &pll_ddr1_clk.common, 380 &cpu_clk.common, 381 &axi_clk.common, 382 &ahb1_clk.common, 383 &apb1_clk.common, 384 &apb2_clk.common, 385 &ahb2_clk.common, 386 &bus_ce_clk.common, 387 &bus_dma_clk.common, 388 &bus_mmc0_clk.common, 389 &bus_mmc1_clk.common, 390 &bus_mmc2_clk.common, 391 &bus_dram_clk.common, 392 &bus_emac_clk.common, 393 &bus_hstimer_clk.common, 394 &bus_spi0_clk.common, 395 &bus_otg_clk.common, 396 &bus_ehci0_clk.common, 397 &bus_ohci0_clk.common, 398 &bus_ve_clk.common, 399 &bus_tcon0_clk.common, 400 &bus_csi_clk.common, 401 &bus_de_clk.common, 402 &bus_codec_clk.common, 403 &bus_pio_clk.common, 404 &bus_i2c0_clk.common, 405 &bus_i2c1_clk.common, 406 &bus_uart0_clk.common, 407 &bus_uart1_clk.common, 408 &bus_uart2_clk.common, 409 &bus_ephy_clk.common, 410 &bus_dbg_clk.common, 411 &mmc0_clk.common, 412 &mmc0_sample_clk.common, 413 &mmc0_output_clk.common, 414 &mmc1_clk.common, 415 &mmc1_sample_clk.common, 416 &mmc1_output_clk.common, 417 &mmc2_clk.common, 418 &mmc2_sample_clk.common, 419 &mmc2_output_clk.common, 420 &ce_clk.common, 421 &spi0_clk.common, 422 &usb_phy0_clk.common, 423 &usb_ohci0_clk.common, 424 &dram_clk.common, 425 &dram_ve_clk.common, 426 &dram_csi_clk.common, 427 &dram_ohci_clk.common, 428 &dram_ehci_clk.common, 429 &de_clk.common, 430 &tcon_clk.common, 431 &csi_misc_clk.common, 432 &csi0_mclk_clk.common, 433 &csi1_sclk_clk.common, 434 &csi1_mclk_clk.common, 435 &ve_clk.common, 436 &ac_dig_clk.common, 437 &avs_clk.common, 438 &mbus_clk.common, 439 &mipi_csi_clk.common, 440 }; 441 442 static const struct clk_hw *clk_parent_pll_audio[] = { 443 &pll_audio_base_clk.common.hw 444 }; 445 446 /* We hardcode the divider to 4 for now */ 447 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", 448 clk_parent_pll_audio, 449 4, 1, CLK_SET_RATE_PARENT); 450 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", 451 clk_parent_pll_audio, 452 2, 1, CLK_SET_RATE_PARENT); 453 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", 454 clk_parent_pll_audio, 455 1, 1, CLK_SET_RATE_PARENT); 456 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", 457 clk_parent_pll_audio, 458 1, 2, CLK_SET_RATE_PARENT); 459 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x", 460 &pll_periph0_clk.common.hw, 461 1, 2, 0); 462 463 static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { 464 .hws = { 465 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 466 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 467 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 468 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 469 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 470 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 471 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 472 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 473 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 474 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 475 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 476 [CLK_PLL_ISP] = &pll_isp_clk.common.hw, 477 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 478 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 479 [CLK_CPU] = &cpu_clk.common.hw, 480 [CLK_AXI] = &axi_clk.common.hw, 481 [CLK_AHB1] = &ahb1_clk.common.hw, 482 [CLK_APB1] = &apb1_clk.common.hw, 483 [CLK_APB2] = &apb2_clk.common.hw, 484 [CLK_AHB2] = &ahb2_clk.common.hw, 485 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 486 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 487 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 488 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 489 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 490 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 491 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 492 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 493 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 494 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 495 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 496 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 497 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 498 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 499 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 500 [CLK_BUS_DE] = &bus_de_clk.common.hw, 501 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 502 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 503 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 504 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 505 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 506 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 507 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 508 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, 509 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 510 [CLK_MMC0] = &mmc0_clk.common.hw, 511 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 512 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 513 [CLK_MMC1] = &mmc1_clk.common.hw, 514 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 515 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 516 [CLK_MMC2] = &mmc2_clk.common.hw, 517 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 518 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 519 [CLK_CE] = &ce_clk.common.hw, 520 [CLK_SPI0] = &spi0_clk.common.hw, 521 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 522 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 523 [CLK_DRAM] = &dram_clk.common.hw, 524 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 525 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 526 [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw, 527 [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw, 528 [CLK_DE] = &de_clk.common.hw, 529 [CLK_TCON0] = &tcon_clk.common.hw, 530 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 531 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 532 [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, 533 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 534 [CLK_VE] = &ve_clk.common.hw, 535 [CLK_AC_DIG] = &ac_dig_clk.common.hw, 536 [CLK_AVS] = &avs_clk.common.hw, 537 [CLK_MBUS] = &mbus_clk.common.hw, 538 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, 539 }, 540 .num = CLK_NUMBER, 541 }; 542 543 static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { 544 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 545 546 [RST_MBUS] = { 0x0fc, BIT(31) }, 547 548 [RST_BUS_CE] = { 0x2c0, BIT(5) }, 549 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 550 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 551 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 552 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 553 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 554 [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 555 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 556 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 557 [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 558 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, 559 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, 560 561 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 562 [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, 563 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 564 [RST_BUS_DE] = { 0x2c4, BIT(12) }, 565 [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 566 567 [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, 568 569 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 570 571 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 572 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 573 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 574 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 575 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 576 }; 577 578 static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { 579 .ccu_clks = sun8i_v3s_ccu_clks, 580 .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), 581 582 .hw_clks = &sun8i_v3s_hw_clks, 583 584 .resets = sun8i_v3s_ccu_resets, 585 .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets), 586 }; 587 588 static void __init sun8i_v3s_ccu_setup(struct device_node *node) 589 { 590 void __iomem *reg; 591 u32 val; 592 593 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 594 if (IS_ERR(reg)) { 595 pr_err("%pOF: Could not map the clock registers\n", node); 596 return; 597 } 598 599 /* Force the PLL-Audio-1x divider to 4 */ 600 val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG); 601 val &= ~GENMASK(19, 16); 602 writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG); 603 604 sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc); 605 } 606 CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu", 607 sun8i_v3s_ccu_setup); 608