19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2d0f11d14SIcenowy Zheng /* 3d0f11d14SIcenowy Zheng * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 4d0f11d14SIcenowy Zheng * 5d0f11d14SIcenowy Zheng * Based on ccu-sun8i-h3.c, which is: 6d0f11d14SIcenowy Zheng * Copyright (c) 2016 Maxime Ripard. All rights reserved. 7d0f11d14SIcenowy Zheng */ 8d0f11d14SIcenowy Zheng 9d0f11d14SIcenowy Zheng #include <linux/clk-provider.h> 1062e59c4eSStephen Boyd #include <linux/io.h> 11*7ec03b58SSamuel Holland #include <linux/module.h> 12*7ec03b58SSamuel Holland #include <linux/of_device.h> 13*7ec03b58SSamuel Holland #include <linux/platform_device.h> 14d0f11d14SIcenowy Zheng 15d0f11d14SIcenowy Zheng #include "ccu_common.h" 16d0f11d14SIcenowy Zheng #include "ccu_reset.h" 17d0f11d14SIcenowy Zheng 18d0f11d14SIcenowy Zheng #include "ccu_div.h" 19d0f11d14SIcenowy Zheng #include "ccu_gate.h" 20d0f11d14SIcenowy Zheng #include "ccu_mp.h" 21d0f11d14SIcenowy Zheng #include "ccu_mult.h" 22d0f11d14SIcenowy Zheng #include "ccu_nk.h" 23d0f11d14SIcenowy Zheng #include "ccu_nkm.h" 24d0f11d14SIcenowy Zheng #include "ccu_nkmp.h" 25d0f11d14SIcenowy Zheng #include "ccu_nm.h" 26d0f11d14SIcenowy Zheng #include "ccu_phase.h" 27d0f11d14SIcenowy Zheng 28d0f11d14SIcenowy Zheng #include "ccu-sun8i-v3s.h" 29d0f11d14SIcenowy Zheng 30d0f11d14SIcenowy Zheng static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", 31d0f11d14SIcenowy Zheng "osc24M", 0x000, 32d0f11d14SIcenowy Zheng 8, 5, /* N */ 33d0f11d14SIcenowy Zheng 4, 2, /* K */ 34d0f11d14SIcenowy Zheng 0, 2, /* M */ 35d0f11d14SIcenowy Zheng 16, 2, /* P */ 36d0f11d14SIcenowy Zheng BIT(31), /* gate */ 37d0f11d14SIcenowy Zheng BIT(28), /* lock */ 38d0f11d14SIcenowy Zheng 0); 39d0f11d14SIcenowy Zheng 40d0f11d14SIcenowy Zheng /* 41d0f11d14SIcenowy Zheng * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 42d0f11d14SIcenowy Zheng * the base (2x, 4x and 8x), and one variable divider (the one true 43d0f11d14SIcenowy Zheng * pll audio). 44d0f11d14SIcenowy Zheng * 4546060be6STobias Schramm * With sigma-delta modulation for fractional-N on the audio PLL, 4646060be6STobias Schramm * we have to use specific dividers. This means the variable divider 4746060be6STobias Schramm * can no longer be used, as the audio codec requests the exact clock 4846060be6STobias Schramm * rates we support through this mechanism. So we now hard code the 4946060be6STobias Schramm * variable divider to 1. This means the clock rates will no longer 5046060be6STobias Schramm * match the clock names. 51d0f11d14SIcenowy Zheng */ 52d0f11d14SIcenowy Zheng #define SUN8I_V3S_PLL_AUDIO_REG 0x008 53d0f11d14SIcenowy Zheng 5446060be6STobias Schramm static struct ccu_sdm_setting pll_audio_sdm_table[] = { 5546060be6STobias Schramm { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 5646060be6STobias Schramm { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 5746060be6STobias Schramm }; 5846060be6STobias Schramm 5946060be6STobias Schramm static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 60d0f11d14SIcenowy Zheng "osc24M", 0x008, 61d0f11d14SIcenowy Zheng 8, 7, /* N */ 62d0f11d14SIcenowy Zheng 0, 5, /* M */ 6346060be6STobias Schramm pll_audio_sdm_table, BIT(24), 6446060be6STobias Schramm 0x284, BIT(31), 65d0f11d14SIcenowy Zheng BIT(31), /* gate */ 66d0f11d14SIcenowy Zheng BIT(28), /* lock */ 6746060be6STobias Schramm CLK_SET_RATE_UNGATE); 68d0f11d14SIcenowy Zheng 69d0f11d14SIcenowy Zheng static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 70d0f11d14SIcenowy Zheng "osc24M", 0x0010, 71d0f11d14SIcenowy Zheng 8, 7, /* N */ 72d0f11d14SIcenowy Zheng 0, 4, /* M */ 73d0f11d14SIcenowy Zheng BIT(24), /* frac enable */ 74d0f11d14SIcenowy Zheng BIT(25), /* frac select */ 75d0f11d14SIcenowy Zheng 270000000, /* frac rate 0 */ 76d0f11d14SIcenowy Zheng 297000000, /* frac rate 1 */ 77d0f11d14SIcenowy Zheng BIT(31), /* gate */ 78d0f11d14SIcenowy Zheng BIT(28), /* lock */ 79d0f11d14SIcenowy Zheng 0); 80d0f11d14SIcenowy Zheng 81d0f11d14SIcenowy Zheng static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 82d0f11d14SIcenowy Zheng "osc24M", 0x0018, 83d0f11d14SIcenowy Zheng 8, 7, /* N */ 84d0f11d14SIcenowy Zheng 0, 4, /* M */ 85d0f11d14SIcenowy Zheng BIT(24), /* frac enable */ 86d0f11d14SIcenowy Zheng BIT(25), /* frac select */ 87d0f11d14SIcenowy Zheng 270000000, /* frac rate 0 */ 88d0f11d14SIcenowy Zheng 297000000, /* frac rate 1 */ 89d0f11d14SIcenowy Zheng BIT(31), /* gate */ 90d0f11d14SIcenowy Zheng BIT(28), /* lock */ 91d0f11d14SIcenowy Zheng 0); 92d0f11d14SIcenowy Zheng 93c5ed9475SIcenowy Zheng static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 94d0f11d14SIcenowy Zheng "osc24M", 0x020, 95d0f11d14SIcenowy Zheng 8, 5, /* N */ 96d0f11d14SIcenowy Zheng 4, 2, /* K */ 97d0f11d14SIcenowy Zheng 0, 2, /* M */ 98d0f11d14SIcenowy Zheng BIT(31), /* gate */ 99d0f11d14SIcenowy Zheng BIT(28), /* lock */ 100d0f11d14SIcenowy Zheng 0); 101d0f11d14SIcenowy Zheng 102d0f11d14SIcenowy Zheng static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", 103d0f11d14SIcenowy Zheng "osc24M", 0x028, 104d0f11d14SIcenowy Zheng 8, 5, /* N */ 105d0f11d14SIcenowy Zheng 4, 2, /* K */ 106d0f11d14SIcenowy Zheng BIT(31), /* gate */ 107d0f11d14SIcenowy Zheng BIT(28), /* lock */ 108d0f11d14SIcenowy Zheng 2, /* post-div */ 109d0f11d14SIcenowy Zheng 0); 110d0f11d14SIcenowy Zheng 111d0f11d14SIcenowy Zheng static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp", 112d0f11d14SIcenowy Zheng "osc24M", 0x002c, 113d0f11d14SIcenowy Zheng 8, 7, /* N */ 114d0f11d14SIcenowy Zheng 0, 4, /* M */ 115d0f11d14SIcenowy Zheng BIT(24), /* frac enable */ 116d0f11d14SIcenowy Zheng BIT(25), /* frac select */ 117d0f11d14SIcenowy Zheng 270000000, /* frac rate 0 */ 118d0f11d14SIcenowy Zheng 297000000, /* frac rate 1 */ 119d0f11d14SIcenowy Zheng BIT(31), /* gate */ 120d0f11d14SIcenowy Zheng BIT(28), /* lock */ 121d0f11d14SIcenowy Zheng 0); 122d0f11d14SIcenowy Zheng 123d0f11d14SIcenowy Zheng static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", 124d0f11d14SIcenowy Zheng "osc24M", 0x044, 125d0f11d14SIcenowy Zheng 8, 5, /* N */ 126d0f11d14SIcenowy Zheng 4, 2, /* K */ 127d0f11d14SIcenowy Zheng BIT(31), /* gate */ 128d0f11d14SIcenowy Zheng BIT(28), /* lock */ 129d0f11d14SIcenowy Zheng 2, /* post-div */ 130d0f11d14SIcenowy Zheng 0); 131d0f11d14SIcenowy Zheng 132c5ed9475SIcenowy Zheng static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 133c5ed9475SIcenowy Zheng "osc24M", 0x04c, 134c5ed9475SIcenowy Zheng 8, 7, /* N */ 135c5ed9475SIcenowy Zheng 0, 2, /* M */ 136c5ed9475SIcenowy Zheng BIT(31), /* gate */ 137c5ed9475SIcenowy Zheng BIT(28), /* lock */ 138c5ed9475SIcenowy Zheng 0); 139c5ed9475SIcenowy Zheng 140d0f11d14SIcenowy Zheng static const char * const cpu_parents[] = { "osc32k", "osc24M", 141d0f11d14SIcenowy Zheng "pll-cpu", "pll-cpu" }; 142d0f11d14SIcenowy Zheng static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 143d0f11d14SIcenowy Zheng 0x050, 16, 2, CLK_IS_CRITICAL); 144d0f11d14SIcenowy Zheng 145d0f11d14SIcenowy Zheng static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0); 146d0f11d14SIcenowy Zheng 147d0f11d14SIcenowy Zheng static const char * const ahb1_parents[] = { "osc32k", "osc24M", 148d0f11d14SIcenowy Zheng "axi", "pll-periph0" }; 14913e0dde8SChen-Yu Tsai static const struct ccu_mux_var_prediv ahb1_predivs[] = { 15013e0dde8SChen-Yu Tsai { .index = 3, .shift = 6, .width = 2 }, 15113e0dde8SChen-Yu Tsai }; 152d0f11d14SIcenowy Zheng static struct ccu_div ahb1_clk = { 153d0f11d14SIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 154d0f11d14SIcenowy Zheng 155d0f11d14SIcenowy Zheng .mux = { 156d0f11d14SIcenowy Zheng .shift = 12, 157d0f11d14SIcenowy Zheng .width = 2, 158d0f11d14SIcenowy Zheng 15913e0dde8SChen-Yu Tsai .var_predivs = ahb1_predivs, 16013e0dde8SChen-Yu Tsai .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 161d0f11d14SIcenowy Zheng }, 162d0f11d14SIcenowy Zheng 163d0f11d14SIcenowy Zheng .common = { 164d0f11d14SIcenowy Zheng .reg = 0x054, 165d0f11d14SIcenowy Zheng .features = CCU_FEATURE_VARIABLE_PREDIV, 166d0f11d14SIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("ahb1", 167d0f11d14SIcenowy Zheng ahb1_parents, 168d0f11d14SIcenowy Zheng &ccu_div_ops, 169d0f11d14SIcenowy Zheng 0), 170d0f11d14SIcenowy Zheng }, 171d0f11d14SIcenowy Zheng }; 172d0f11d14SIcenowy Zheng 173d0f11d14SIcenowy Zheng static struct clk_div_table apb1_div_table[] = { 174d0f11d14SIcenowy Zheng { .val = 0, .div = 2 }, 175d0f11d14SIcenowy Zheng { .val = 1, .div = 2 }, 176d0f11d14SIcenowy Zheng { .val = 2, .div = 4 }, 177d0f11d14SIcenowy Zheng { .val = 3, .div = 8 }, 178d0f11d14SIcenowy Zheng { /* Sentinel */ }, 179d0f11d14SIcenowy Zheng }; 180d0f11d14SIcenowy Zheng static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 181d0f11d14SIcenowy Zheng 0x054, 8, 2, apb1_div_table, 0); 182d0f11d14SIcenowy Zheng 183d0f11d14SIcenowy Zheng static const char * const apb2_parents[] = { "osc32k", "osc24M", 184d0f11d14SIcenowy Zheng "pll-periph0", "pll-periph0" }; 185d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 186d0f11d14SIcenowy Zheng 0, 5, /* M */ 187d0f11d14SIcenowy Zheng 16, 2, /* P */ 188d0f11d14SIcenowy Zheng 24, 2, /* mux */ 189d0f11d14SIcenowy Zheng 0); 190d0f11d14SIcenowy Zheng 191d0f11d14SIcenowy Zheng static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" }; 192d0f11d14SIcenowy Zheng static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { 193d0f11d14SIcenowy Zheng { .index = 1, .div = 2 }, 194d0f11d14SIcenowy Zheng }; 195d0f11d14SIcenowy Zheng static struct ccu_mux ahb2_clk = { 196d0f11d14SIcenowy Zheng .mux = { 197d0f11d14SIcenowy Zheng .shift = 0, 198d0f11d14SIcenowy Zheng .width = 1, 199d0f11d14SIcenowy Zheng .fixed_predivs = ahb2_fixed_predivs, 200d0f11d14SIcenowy Zheng .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), 201d0f11d14SIcenowy Zheng }, 202d0f11d14SIcenowy Zheng 203d0f11d14SIcenowy Zheng .common = { 204d0f11d14SIcenowy Zheng .reg = 0x05c, 205d0f11d14SIcenowy Zheng .features = CCU_FEATURE_FIXED_PREDIV, 206d0f11d14SIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("ahb2", 207d0f11d14SIcenowy Zheng ahb2_parents, 208d0f11d14SIcenowy Zheng &ccu_mux_ops, 209d0f11d14SIcenowy Zheng 0), 210d0f11d14SIcenowy Zheng }, 211d0f11d14SIcenowy Zheng }; 212d0f11d14SIcenowy Zheng 213d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 214d0f11d14SIcenowy Zheng 0x060, BIT(5), 0); 215d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 216d0f11d14SIcenowy Zheng 0x060, BIT(6), 0); 217d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 218d0f11d14SIcenowy Zheng 0x060, BIT(8), 0); 219d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 220d0f11d14SIcenowy Zheng 0x060, BIT(9), 0); 221d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 222d0f11d14SIcenowy Zheng 0x060, BIT(10), 0); 223d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 224d0f11d14SIcenowy Zheng 0x060, BIT(14), 0); 225d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 226d0f11d14SIcenowy Zheng 0x060, BIT(17), 0); 227d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 228d0f11d14SIcenowy Zheng 0x060, BIT(19), 0); 229d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 230d0f11d14SIcenowy Zheng 0x060, BIT(20), 0); 231d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 232d0f11d14SIcenowy Zheng 0x060, BIT(24), 0); 233d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 234d0f11d14SIcenowy Zheng 0x060, BIT(26), 0); 235d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 236d0f11d14SIcenowy Zheng 0x060, BIT(29), 0); 237d0f11d14SIcenowy Zheng 238d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 239d0f11d14SIcenowy Zheng 0x064, BIT(0), 0); 240d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 241d0f11d14SIcenowy Zheng 0x064, BIT(4), 0); 242d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 243d0f11d14SIcenowy Zheng 0x064, BIT(8), 0); 244d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 245d0f11d14SIcenowy Zheng 0x064, BIT(12), 0); 246d0f11d14SIcenowy Zheng 247d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 248d0f11d14SIcenowy Zheng 0x068, BIT(0), 0); 249d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 250d0f11d14SIcenowy Zheng 0x068, BIT(5), 0); 2510ed4c252SIcenowy Zheng static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 2520ed4c252SIcenowy Zheng 0x068, BIT(12), 0); 253d0f11d14SIcenowy Zheng 254d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 255d0f11d14SIcenowy Zheng 0x06c, BIT(0), 0); 256d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 257d0f11d14SIcenowy Zheng 0x06c, BIT(1), 0); 258d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 259d0f11d14SIcenowy Zheng 0x06c, BIT(16), 0); 260d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 261d0f11d14SIcenowy Zheng 0x06c, BIT(17), 0); 262d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 263d0f11d14SIcenowy Zheng 0x06c, BIT(18), 0); 264d0f11d14SIcenowy Zheng 265d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1", 266d0f11d14SIcenowy Zheng 0x070, BIT(0), 0); 267d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 268d0f11d14SIcenowy Zheng 0x070, BIT(7), 0); 269d0f11d14SIcenowy Zheng 270d0f11d14SIcenowy Zheng static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 271d0f11d14SIcenowy Zheng "pll-periph1" }; 272d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 273d0f11d14SIcenowy Zheng 0, 4, /* M */ 274d0f11d14SIcenowy Zheng 16, 2, /* P */ 275d0f11d14SIcenowy Zheng 24, 2, /* mux */ 276d0f11d14SIcenowy Zheng BIT(31), /* gate */ 277d0f11d14SIcenowy Zheng 0); 278d0f11d14SIcenowy Zheng 279d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 280d0f11d14SIcenowy Zheng 0x088, 20, 3, 0); 281d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 282d0f11d14SIcenowy Zheng 0x088, 8, 3, 0); 283d0f11d14SIcenowy Zheng 284d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 285d0f11d14SIcenowy Zheng 0, 4, /* M */ 286d0f11d14SIcenowy Zheng 16, 2, /* P */ 287d0f11d14SIcenowy Zheng 24, 2, /* mux */ 288d0f11d14SIcenowy Zheng BIT(31), /* gate */ 289d0f11d14SIcenowy Zheng 0); 290d0f11d14SIcenowy Zheng 291d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 292d0f11d14SIcenowy Zheng 0x08c, 20, 3, 0); 293d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 294d0f11d14SIcenowy Zheng 0x08c, 8, 3, 0); 295d0f11d14SIcenowy Zheng 296d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 297d0f11d14SIcenowy Zheng 0, 4, /* M */ 298d0f11d14SIcenowy Zheng 16, 2, /* P */ 299d0f11d14SIcenowy Zheng 24, 2, /* mux */ 300d0f11d14SIcenowy Zheng BIT(31), /* gate */ 301d0f11d14SIcenowy Zheng 0); 302d0f11d14SIcenowy Zheng 303d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", 304d0f11d14SIcenowy Zheng 0x090, 20, 3, 0); 305d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", 306d0f11d14SIcenowy Zheng 0x090, 8, 3, 0); 307d0f11d14SIcenowy Zheng 308d0f11d14SIcenowy Zheng static const char * const ce_parents[] = { "osc24M", "pll-periph0", }; 309d0f11d14SIcenowy Zheng 310d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c, 311d0f11d14SIcenowy Zheng 0, 4, /* M */ 312d0f11d14SIcenowy Zheng 16, 2, /* P */ 313d0f11d14SIcenowy Zheng 24, 2, /* mux */ 314d0f11d14SIcenowy Zheng BIT(31), /* gate */ 315d0f11d14SIcenowy Zheng 0); 316d0f11d14SIcenowy Zheng 317d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 318d0f11d14SIcenowy Zheng 0, 4, /* M */ 319d0f11d14SIcenowy Zheng 16, 2, /* P */ 320d0f11d14SIcenowy Zheng 24, 2, /* mux */ 321d0f11d14SIcenowy Zheng BIT(31), /* gate */ 322d0f11d14SIcenowy Zheng 0); 323d0f11d14SIcenowy Zheng 3240ed4c252SIcenowy Zheng static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 3250ed4c252SIcenowy Zheng "pll-audio-2x", "pll-audio" }; 3260ed4c252SIcenowy Zheng static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 3270ed4c252SIcenowy Zheng 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 3280ed4c252SIcenowy Zheng 329d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 330d0f11d14SIcenowy Zheng 0x0cc, BIT(8), 0); 331d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 332d0f11d14SIcenowy Zheng 0x0cc, BIT(16), 0); 333d0f11d14SIcenowy Zheng 334c5ed9475SIcenowy Zheng static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1", 335c5ed9475SIcenowy Zheng "pll-periph0-2x" }; 336d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 337d0f11d14SIcenowy Zheng 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); 338d0f11d14SIcenowy Zheng 339d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 340d0f11d14SIcenowy Zheng 0x100, BIT(0), 0); 341d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 342d0f11d14SIcenowy Zheng 0x100, BIT(1), 0); 343d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram", 344d0f11d14SIcenowy Zheng 0x100, BIT(17), 0); 345d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", 346d0f11d14SIcenowy Zheng 0x100, BIT(18), 0); 347d0f11d14SIcenowy Zheng 348d0f11d14SIcenowy Zheng static const char * const de_parents[] = { "pll-video", "pll-periph0" }; 349d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 350ab65e04dSJernej Skrabec 0x104, 0, 4, 24, 2, BIT(31), 351ab65e04dSJernej Skrabec CLK_SET_RATE_PARENT); 352d0f11d14SIcenowy Zheng 353d0f11d14SIcenowy Zheng static const char * const tcon_parents[] = { "pll-video" }; 354d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, 355d0f11d14SIcenowy Zheng 0x118, 0, 4, 24, 3, BIT(31), 0); 356d0f11d14SIcenowy Zheng 357d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 358d0f11d14SIcenowy Zheng 0x130, BIT(31), 0); 359d0f11d14SIcenowy Zheng 360d0f11d14SIcenowy Zheng static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", 361d0f11d14SIcenowy Zheng "pll-periph0", "pll-periph1" }; 362d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 363d0f11d14SIcenowy Zheng 0x130, 0, 5, 8, 3, BIT(15), 0); 364d0f11d14SIcenowy Zheng 365d0f11d14SIcenowy Zheng static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" }; 366d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents, 367d0f11d14SIcenowy Zheng 0x134, 16, 4, 24, 3, BIT(31), 0); 368d0f11d14SIcenowy Zheng 369d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents, 370d0f11d14SIcenowy Zheng 0x134, 0, 5, 8, 3, BIT(15), 0); 371d0f11d14SIcenowy Zheng 372d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 373d0f11d14SIcenowy Zheng 0x13c, 16, 3, BIT(31), 0); 374d0f11d14SIcenowy Zheng 375d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 376d0f11d14SIcenowy Zheng 0x140, BIT(31), CLK_SET_RATE_PARENT); 377d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 378d0f11d14SIcenowy Zheng 0x144, BIT(31), 0); 379d0f11d14SIcenowy Zheng 380d0f11d14SIcenowy Zheng static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 381d0f11d14SIcenowy Zheng "pll-ddr" }; 382d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 383d0f11d14SIcenowy Zheng 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 384d0f11d14SIcenowy Zheng 385d0f11d14SIcenowy Zheng static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0", 386d0f11d14SIcenowy Zheng "pll-isp" }; 387d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents, 388d0f11d14SIcenowy Zheng 0x16c, 0, 3, 24, 2, BIT(31), 0); 389d0f11d14SIcenowy Zheng 390d0f11d14SIcenowy Zheng static struct ccu_common *sun8i_v3s_ccu_clks[] = { 391d0f11d14SIcenowy Zheng &pll_cpu_clk.common, 392d0f11d14SIcenowy Zheng &pll_audio_base_clk.common, 393d0f11d14SIcenowy Zheng &pll_video_clk.common, 394d0f11d14SIcenowy Zheng &pll_ve_clk.common, 395c5ed9475SIcenowy Zheng &pll_ddr0_clk.common, 396d0f11d14SIcenowy Zheng &pll_periph0_clk.common, 397d0f11d14SIcenowy Zheng &pll_isp_clk.common, 398d0f11d14SIcenowy Zheng &pll_periph1_clk.common, 399c5ed9475SIcenowy Zheng &pll_ddr1_clk.common, 400d0f11d14SIcenowy Zheng &cpu_clk.common, 401d0f11d14SIcenowy Zheng &axi_clk.common, 402d0f11d14SIcenowy Zheng &ahb1_clk.common, 403d0f11d14SIcenowy Zheng &apb1_clk.common, 404d0f11d14SIcenowy Zheng &apb2_clk.common, 405d0f11d14SIcenowy Zheng &ahb2_clk.common, 406d0f11d14SIcenowy Zheng &bus_ce_clk.common, 407d0f11d14SIcenowy Zheng &bus_dma_clk.common, 408d0f11d14SIcenowy Zheng &bus_mmc0_clk.common, 409d0f11d14SIcenowy Zheng &bus_mmc1_clk.common, 410d0f11d14SIcenowy Zheng &bus_mmc2_clk.common, 411d0f11d14SIcenowy Zheng &bus_dram_clk.common, 412d0f11d14SIcenowy Zheng &bus_emac_clk.common, 413d0f11d14SIcenowy Zheng &bus_hstimer_clk.common, 414d0f11d14SIcenowy Zheng &bus_spi0_clk.common, 415d0f11d14SIcenowy Zheng &bus_otg_clk.common, 416d0f11d14SIcenowy Zheng &bus_ehci0_clk.common, 417d0f11d14SIcenowy Zheng &bus_ohci0_clk.common, 418d0f11d14SIcenowy Zheng &bus_ve_clk.common, 419d0f11d14SIcenowy Zheng &bus_tcon0_clk.common, 420d0f11d14SIcenowy Zheng &bus_csi_clk.common, 421d0f11d14SIcenowy Zheng &bus_de_clk.common, 422d0f11d14SIcenowy Zheng &bus_codec_clk.common, 423d0f11d14SIcenowy Zheng &bus_pio_clk.common, 424d0f11d14SIcenowy Zheng &bus_i2c0_clk.common, 425d0f11d14SIcenowy Zheng &bus_i2c1_clk.common, 426d0f11d14SIcenowy Zheng &bus_uart0_clk.common, 427d0f11d14SIcenowy Zheng &bus_uart1_clk.common, 428d0f11d14SIcenowy Zheng &bus_uart2_clk.common, 429d0f11d14SIcenowy Zheng &bus_ephy_clk.common, 430d0f11d14SIcenowy Zheng &bus_dbg_clk.common, 431d0f11d14SIcenowy Zheng &mmc0_clk.common, 432d0f11d14SIcenowy Zheng &mmc0_sample_clk.common, 433d0f11d14SIcenowy Zheng &mmc0_output_clk.common, 434d0f11d14SIcenowy Zheng &mmc1_clk.common, 435d0f11d14SIcenowy Zheng &mmc1_sample_clk.common, 436d0f11d14SIcenowy Zheng &mmc1_output_clk.common, 437d0f11d14SIcenowy Zheng &mmc2_clk.common, 438d0f11d14SIcenowy Zheng &mmc2_sample_clk.common, 439d0f11d14SIcenowy Zheng &mmc2_output_clk.common, 440d0f11d14SIcenowy Zheng &ce_clk.common, 441d0f11d14SIcenowy Zheng &spi0_clk.common, 442d0f11d14SIcenowy Zheng &usb_phy0_clk.common, 443d0f11d14SIcenowy Zheng &usb_ohci0_clk.common, 444d0f11d14SIcenowy Zheng &dram_clk.common, 445d0f11d14SIcenowy Zheng &dram_ve_clk.common, 446d0f11d14SIcenowy Zheng &dram_csi_clk.common, 447d0f11d14SIcenowy Zheng &dram_ohci_clk.common, 448d0f11d14SIcenowy Zheng &dram_ehci_clk.common, 449d0f11d14SIcenowy Zheng &de_clk.common, 450d0f11d14SIcenowy Zheng &tcon_clk.common, 451d0f11d14SIcenowy Zheng &csi_misc_clk.common, 452d0f11d14SIcenowy Zheng &csi0_mclk_clk.common, 453d0f11d14SIcenowy Zheng &csi1_sclk_clk.common, 454d0f11d14SIcenowy Zheng &csi1_mclk_clk.common, 455d0f11d14SIcenowy Zheng &ve_clk.common, 456d0f11d14SIcenowy Zheng &ac_dig_clk.common, 457d0f11d14SIcenowy Zheng &avs_clk.common, 458d0f11d14SIcenowy Zheng &mbus_clk.common, 459d0f11d14SIcenowy Zheng &mipi_csi_clk.common, 460d0f11d14SIcenowy Zheng }; 461d0f11d14SIcenowy Zheng 462707f6013SChen-Yu Tsai static const struct clk_hw *clk_parent_pll_audio[] = { 463707f6013SChen-Yu Tsai &pll_audio_base_clk.common.hw 464707f6013SChen-Yu Tsai }; 465707f6013SChen-Yu Tsai 4660ed4c252SIcenowy Zheng static struct ccu_common *sun8i_v3_ccu_clks[] = { 4670ed4c252SIcenowy Zheng &pll_cpu_clk.common, 4680ed4c252SIcenowy Zheng &pll_audio_base_clk.common, 4690ed4c252SIcenowy Zheng &pll_video_clk.common, 4700ed4c252SIcenowy Zheng &pll_ve_clk.common, 4710ed4c252SIcenowy Zheng &pll_ddr0_clk.common, 4720ed4c252SIcenowy Zheng &pll_periph0_clk.common, 4730ed4c252SIcenowy Zheng &pll_isp_clk.common, 4740ed4c252SIcenowy Zheng &pll_periph1_clk.common, 4750ed4c252SIcenowy Zheng &pll_ddr1_clk.common, 4760ed4c252SIcenowy Zheng &cpu_clk.common, 4770ed4c252SIcenowy Zheng &axi_clk.common, 4780ed4c252SIcenowy Zheng &ahb1_clk.common, 4790ed4c252SIcenowy Zheng &apb1_clk.common, 4800ed4c252SIcenowy Zheng &apb2_clk.common, 4810ed4c252SIcenowy Zheng &ahb2_clk.common, 4820ed4c252SIcenowy Zheng &bus_ce_clk.common, 4830ed4c252SIcenowy Zheng &bus_dma_clk.common, 4840ed4c252SIcenowy Zheng &bus_mmc0_clk.common, 4850ed4c252SIcenowy Zheng &bus_mmc1_clk.common, 4860ed4c252SIcenowy Zheng &bus_mmc2_clk.common, 4870ed4c252SIcenowy Zheng &bus_dram_clk.common, 4880ed4c252SIcenowy Zheng &bus_emac_clk.common, 4890ed4c252SIcenowy Zheng &bus_hstimer_clk.common, 4900ed4c252SIcenowy Zheng &bus_spi0_clk.common, 4910ed4c252SIcenowy Zheng &bus_otg_clk.common, 4920ed4c252SIcenowy Zheng &bus_ehci0_clk.common, 4930ed4c252SIcenowy Zheng &bus_ohci0_clk.common, 4940ed4c252SIcenowy Zheng &bus_ve_clk.common, 4950ed4c252SIcenowy Zheng &bus_tcon0_clk.common, 4960ed4c252SIcenowy Zheng &bus_csi_clk.common, 4970ed4c252SIcenowy Zheng &bus_de_clk.common, 4980ed4c252SIcenowy Zheng &bus_codec_clk.common, 4990ed4c252SIcenowy Zheng &bus_pio_clk.common, 5000ed4c252SIcenowy Zheng &bus_i2s0_clk.common, 5010ed4c252SIcenowy Zheng &bus_i2c0_clk.common, 5020ed4c252SIcenowy Zheng &bus_i2c1_clk.common, 5030ed4c252SIcenowy Zheng &bus_uart0_clk.common, 5040ed4c252SIcenowy Zheng &bus_uart1_clk.common, 5050ed4c252SIcenowy Zheng &bus_uart2_clk.common, 5060ed4c252SIcenowy Zheng &bus_ephy_clk.common, 5070ed4c252SIcenowy Zheng &bus_dbg_clk.common, 5080ed4c252SIcenowy Zheng &mmc0_clk.common, 5090ed4c252SIcenowy Zheng &mmc0_sample_clk.common, 5100ed4c252SIcenowy Zheng &mmc0_output_clk.common, 5110ed4c252SIcenowy Zheng &mmc1_clk.common, 5120ed4c252SIcenowy Zheng &mmc1_sample_clk.common, 5130ed4c252SIcenowy Zheng &mmc1_output_clk.common, 5140ed4c252SIcenowy Zheng &mmc2_clk.common, 5150ed4c252SIcenowy Zheng &mmc2_sample_clk.common, 5160ed4c252SIcenowy Zheng &mmc2_output_clk.common, 5170ed4c252SIcenowy Zheng &ce_clk.common, 5180ed4c252SIcenowy Zheng &spi0_clk.common, 5190ed4c252SIcenowy Zheng &i2s0_clk.common, 5200ed4c252SIcenowy Zheng &usb_phy0_clk.common, 5210ed4c252SIcenowy Zheng &usb_ohci0_clk.common, 5220ed4c252SIcenowy Zheng &dram_clk.common, 5230ed4c252SIcenowy Zheng &dram_ve_clk.common, 5240ed4c252SIcenowy Zheng &dram_csi_clk.common, 5250ed4c252SIcenowy Zheng &dram_ohci_clk.common, 5260ed4c252SIcenowy Zheng &dram_ehci_clk.common, 5270ed4c252SIcenowy Zheng &de_clk.common, 5280ed4c252SIcenowy Zheng &tcon_clk.common, 5290ed4c252SIcenowy Zheng &csi_misc_clk.common, 5300ed4c252SIcenowy Zheng &csi0_mclk_clk.common, 5310ed4c252SIcenowy Zheng &csi1_sclk_clk.common, 5320ed4c252SIcenowy Zheng &csi1_mclk_clk.common, 5330ed4c252SIcenowy Zheng &ve_clk.common, 5340ed4c252SIcenowy Zheng &ac_dig_clk.common, 5350ed4c252SIcenowy Zheng &avs_clk.common, 5360ed4c252SIcenowy Zheng &mbus_clk.common, 5370ed4c252SIcenowy Zheng &mipi_csi_clk.common, 5380ed4c252SIcenowy Zheng }; 5390ed4c252SIcenowy Zheng 54046060be6STobias Schramm /* We hardcode the divider to 1 for SDM support */ 541707f6013SChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", 542707f6013SChen-Yu Tsai clk_parent_pll_audio, 54346060be6STobias Schramm 1, 1, CLK_SET_RATE_PARENT); 544707f6013SChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", 545707f6013SChen-Yu Tsai clk_parent_pll_audio, 546707f6013SChen-Yu Tsai 2, 1, CLK_SET_RATE_PARENT); 547707f6013SChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", 548707f6013SChen-Yu Tsai clk_parent_pll_audio, 549707f6013SChen-Yu Tsai 1, 1, CLK_SET_RATE_PARENT); 550707f6013SChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", 551707f6013SChen-Yu Tsai clk_parent_pll_audio, 552707f6013SChen-Yu Tsai 1, 2, CLK_SET_RATE_PARENT); 553707f6013SChen-Yu Tsai static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x", 554707f6013SChen-Yu Tsai &pll_periph0_clk.common.hw, 555707f6013SChen-Yu Tsai 1, 2, 0); 556d0f11d14SIcenowy Zheng 557d0f11d14SIcenowy Zheng static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { 558d0f11d14SIcenowy Zheng .hws = { 559d0f11d14SIcenowy Zheng [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 560d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 561d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 562d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 563d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 564d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 565d0f11d14SIcenowy Zheng [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 566d0f11d14SIcenowy Zheng [CLK_PLL_VE] = &pll_ve_clk.common.hw, 567c5ed9475SIcenowy Zheng [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 568d0f11d14SIcenowy Zheng [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 569d0f11d14SIcenowy Zheng [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 570d0f11d14SIcenowy Zheng [CLK_PLL_ISP] = &pll_isp_clk.common.hw, 571d0f11d14SIcenowy Zheng [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 572c5ed9475SIcenowy Zheng [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 573d0f11d14SIcenowy Zheng [CLK_CPU] = &cpu_clk.common.hw, 574d0f11d14SIcenowy Zheng [CLK_AXI] = &axi_clk.common.hw, 575d0f11d14SIcenowy Zheng [CLK_AHB1] = &ahb1_clk.common.hw, 576d0f11d14SIcenowy Zheng [CLK_APB1] = &apb1_clk.common.hw, 577d0f11d14SIcenowy Zheng [CLK_APB2] = &apb2_clk.common.hw, 578d0f11d14SIcenowy Zheng [CLK_AHB2] = &ahb2_clk.common.hw, 579d0f11d14SIcenowy Zheng [CLK_BUS_CE] = &bus_ce_clk.common.hw, 580d0f11d14SIcenowy Zheng [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 581d0f11d14SIcenowy Zheng [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 582d0f11d14SIcenowy Zheng [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 583d0f11d14SIcenowy Zheng [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 584d0f11d14SIcenowy Zheng [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 585d0f11d14SIcenowy Zheng [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 586d0f11d14SIcenowy Zheng [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 587d0f11d14SIcenowy Zheng [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 588d0f11d14SIcenowy Zheng [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 589d0f11d14SIcenowy Zheng [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 590d0f11d14SIcenowy Zheng [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 591d0f11d14SIcenowy Zheng [CLK_BUS_VE] = &bus_ve_clk.common.hw, 592d0f11d14SIcenowy Zheng [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 593d0f11d14SIcenowy Zheng [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 594d0f11d14SIcenowy Zheng [CLK_BUS_DE] = &bus_de_clk.common.hw, 595d0f11d14SIcenowy Zheng [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 596d0f11d14SIcenowy Zheng [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 597d0f11d14SIcenowy Zheng [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 598d0f11d14SIcenowy Zheng [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 599d0f11d14SIcenowy Zheng [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 600d0f11d14SIcenowy Zheng [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 601d0f11d14SIcenowy Zheng [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 602d0f11d14SIcenowy Zheng [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, 603d0f11d14SIcenowy Zheng [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 604d0f11d14SIcenowy Zheng [CLK_MMC0] = &mmc0_clk.common.hw, 605d0f11d14SIcenowy Zheng [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 606d0f11d14SIcenowy Zheng [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 607d0f11d14SIcenowy Zheng [CLK_MMC1] = &mmc1_clk.common.hw, 608d0f11d14SIcenowy Zheng [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 609d0f11d14SIcenowy Zheng [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 61072009960SIcenowy Zheng [CLK_MMC2] = &mmc2_clk.common.hw, 61172009960SIcenowy Zheng [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 61272009960SIcenowy Zheng [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 613d0f11d14SIcenowy Zheng [CLK_CE] = &ce_clk.common.hw, 614d0f11d14SIcenowy Zheng [CLK_SPI0] = &spi0_clk.common.hw, 615d0f11d14SIcenowy Zheng [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 616d0f11d14SIcenowy Zheng [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 617d0f11d14SIcenowy Zheng [CLK_DRAM] = &dram_clk.common.hw, 618d0f11d14SIcenowy Zheng [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 619d0f11d14SIcenowy Zheng [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 620d0f11d14SIcenowy Zheng [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw, 621d0f11d14SIcenowy Zheng [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw, 622d0f11d14SIcenowy Zheng [CLK_DE] = &de_clk.common.hw, 623d0f11d14SIcenowy Zheng [CLK_TCON0] = &tcon_clk.common.hw, 624d0f11d14SIcenowy Zheng [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 625d0f11d14SIcenowy Zheng [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 626d0f11d14SIcenowy Zheng [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, 627d0f11d14SIcenowy Zheng [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 628d0f11d14SIcenowy Zheng [CLK_VE] = &ve_clk.common.hw, 629d0f11d14SIcenowy Zheng [CLK_AC_DIG] = &ac_dig_clk.common.hw, 630d0f11d14SIcenowy Zheng [CLK_AVS] = &avs_clk.common.hw, 631d0f11d14SIcenowy Zheng [CLK_MBUS] = &mbus_clk.common.hw, 632d0f11d14SIcenowy Zheng [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, 633d0f11d14SIcenowy Zheng }, 6344ff40d14SYunhao Tian .num = CLK_PLL_DDR1 + 1, 635d0f11d14SIcenowy Zheng }; 636d0f11d14SIcenowy Zheng 6370ed4c252SIcenowy Zheng static struct clk_hw_onecell_data sun8i_v3_hw_clks = { 6380ed4c252SIcenowy Zheng .hws = { 6390ed4c252SIcenowy Zheng [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 6400ed4c252SIcenowy Zheng [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 6410ed4c252SIcenowy Zheng [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 6420ed4c252SIcenowy Zheng [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 6430ed4c252SIcenowy Zheng [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 6440ed4c252SIcenowy Zheng [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 6450ed4c252SIcenowy Zheng [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 6460ed4c252SIcenowy Zheng [CLK_PLL_VE] = &pll_ve_clk.common.hw, 6470ed4c252SIcenowy Zheng [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 6480ed4c252SIcenowy Zheng [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 6490ed4c252SIcenowy Zheng [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 6500ed4c252SIcenowy Zheng [CLK_PLL_ISP] = &pll_isp_clk.common.hw, 6510ed4c252SIcenowy Zheng [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 6520ed4c252SIcenowy Zheng [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 6530ed4c252SIcenowy Zheng [CLK_CPU] = &cpu_clk.common.hw, 6540ed4c252SIcenowy Zheng [CLK_AXI] = &axi_clk.common.hw, 6550ed4c252SIcenowy Zheng [CLK_AHB1] = &ahb1_clk.common.hw, 6560ed4c252SIcenowy Zheng [CLK_APB1] = &apb1_clk.common.hw, 6570ed4c252SIcenowy Zheng [CLK_APB2] = &apb2_clk.common.hw, 6580ed4c252SIcenowy Zheng [CLK_AHB2] = &ahb2_clk.common.hw, 6590ed4c252SIcenowy Zheng [CLK_BUS_CE] = &bus_ce_clk.common.hw, 6600ed4c252SIcenowy Zheng [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 6610ed4c252SIcenowy Zheng [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 6620ed4c252SIcenowy Zheng [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 6630ed4c252SIcenowy Zheng [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 6640ed4c252SIcenowy Zheng [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 6650ed4c252SIcenowy Zheng [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 6660ed4c252SIcenowy Zheng [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 6670ed4c252SIcenowy Zheng [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 6680ed4c252SIcenowy Zheng [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 6690ed4c252SIcenowy Zheng [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 6700ed4c252SIcenowy Zheng [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 6710ed4c252SIcenowy Zheng [CLK_BUS_VE] = &bus_ve_clk.common.hw, 6720ed4c252SIcenowy Zheng [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 6730ed4c252SIcenowy Zheng [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 6740ed4c252SIcenowy Zheng [CLK_BUS_DE] = &bus_de_clk.common.hw, 6750ed4c252SIcenowy Zheng [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 6760ed4c252SIcenowy Zheng [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 6770ed4c252SIcenowy Zheng [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 6780ed4c252SIcenowy Zheng [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 6790ed4c252SIcenowy Zheng [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 6800ed4c252SIcenowy Zheng [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 6810ed4c252SIcenowy Zheng [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 6820ed4c252SIcenowy Zheng [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 6830ed4c252SIcenowy Zheng [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, 6840ed4c252SIcenowy Zheng [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 6850ed4c252SIcenowy Zheng [CLK_MMC0] = &mmc0_clk.common.hw, 6860ed4c252SIcenowy Zheng [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 6870ed4c252SIcenowy Zheng [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 6880ed4c252SIcenowy Zheng [CLK_MMC1] = &mmc1_clk.common.hw, 6890ed4c252SIcenowy Zheng [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 6900ed4c252SIcenowy Zheng [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 6910ed4c252SIcenowy Zheng [CLK_MMC2] = &mmc2_clk.common.hw, 6920ed4c252SIcenowy Zheng [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 6930ed4c252SIcenowy Zheng [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 6940ed4c252SIcenowy Zheng [CLK_CE] = &ce_clk.common.hw, 6950ed4c252SIcenowy Zheng [CLK_SPI0] = &spi0_clk.common.hw, 6960ed4c252SIcenowy Zheng [CLK_I2S0] = &i2s0_clk.common.hw, 6970ed4c252SIcenowy Zheng [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 6980ed4c252SIcenowy Zheng [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 6990ed4c252SIcenowy Zheng [CLK_DRAM] = &dram_clk.common.hw, 7000ed4c252SIcenowy Zheng [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 7010ed4c252SIcenowy Zheng [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 7020ed4c252SIcenowy Zheng [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw, 7030ed4c252SIcenowy Zheng [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw, 7040ed4c252SIcenowy Zheng [CLK_DE] = &de_clk.common.hw, 7050ed4c252SIcenowy Zheng [CLK_TCON0] = &tcon_clk.common.hw, 7060ed4c252SIcenowy Zheng [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 7070ed4c252SIcenowy Zheng [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 7080ed4c252SIcenowy Zheng [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, 7090ed4c252SIcenowy Zheng [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 7100ed4c252SIcenowy Zheng [CLK_VE] = &ve_clk.common.hw, 7110ed4c252SIcenowy Zheng [CLK_AC_DIG] = &ac_dig_clk.common.hw, 7120ed4c252SIcenowy Zheng [CLK_AVS] = &avs_clk.common.hw, 7130ed4c252SIcenowy Zheng [CLK_MBUS] = &mbus_clk.common.hw, 7140ed4c252SIcenowy Zheng [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, 7150ed4c252SIcenowy Zheng }, 7164ff40d14SYunhao Tian .num = CLK_I2S0 + 1, 7170ed4c252SIcenowy Zheng }; 7180ed4c252SIcenowy Zheng 719d0f11d14SIcenowy Zheng static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { 720d0f11d14SIcenowy Zheng [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 721d0f11d14SIcenowy Zheng 722d0f11d14SIcenowy Zheng [RST_MBUS] = { 0x0fc, BIT(31) }, 723d0f11d14SIcenowy Zheng 724d0f11d14SIcenowy Zheng [RST_BUS_CE] = { 0x2c0, BIT(5) }, 725d0f11d14SIcenowy Zheng [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 726d0f11d14SIcenowy Zheng [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 727d0f11d14SIcenowy Zheng [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 728d0f11d14SIcenowy Zheng [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 729d0f11d14SIcenowy Zheng [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 730d0f11d14SIcenowy Zheng [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 731d0f11d14SIcenowy Zheng [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 732d0f11d14SIcenowy Zheng [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 7337ffc781eSYong Deng [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 734d0f11d14SIcenowy Zheng [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, 735d0f11d14SIcenowy Zheng [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, 736d0f11d14SIcenowy Zheng 737d0f11d14SIcenowy Zheng [RST_BUS_VE] = { 0x2c4, BIT(0) }, 7385c59801fSPaul Kocialkowski [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, 739d0f11d14SIcenowy Zheng [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 740d0f11d14SIcenowy Zheng [RST_BUS_DE] = { 0x2c4, BIT(12) }, 741d0f11d14SIcenowy Zheng [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 742d0f11d14SIcenowy Zheng 743d0f11d14SIcenowy Zheng [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, 744d0f11d14SIcenowy Zheng 745d0f11d14SIcenowy Zheng [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 746d0f11d14SIcenowy Zheng 747d0f11d14SIcenowy Zheng [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 748d0f11d14SIcenowy Zheng [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 749d0f11d14SIcenowy Zheng [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 750d0f11d14SIcenowy Zheng [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 751d0f11d14SIcenowy Zheng [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 752d0f11d14SIcenowy Zheng }; 753d0f11d14SIcenowy Zheng 7540ed4c252SIcenowy Zheng static struct ccu_reset_map sun8i_v3_ccu_resets[] = { 7550ed4c252SIcenowy Zheng [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 7560ed4c252SIcenowy Zheng 7570ed4c252SIcenowy Zheng [RST_MBUS] = { 0x0fc, BIT(31) }, 7580ed4c252SIcenowy Zheng 7590ed4c252SIcenowy Zheng [RST_BUS_CE] = { 0x2c0, BIT(5) }, 7600ed4c252SIcenowy Zheng [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 7610ed4c252SIcenowy Zheng [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 7620ed4c252SIcenowy Zheng [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 7630ed4c252SIcenowy Zheng [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 7640ed4c252SIcenowy Zheng [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 7650ed4c252SIcenowy Zheng [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 7660ed4c252SIcenowy Zheng [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 7670ed4c252SIcenowy Zheng [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 7680ed4c252SIcenowy Zheng [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 7690ed4c252SIcenowy Zheng [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, 7700ed4c252SIcenowy Zheng [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, 7710ed4c252SIcenowy Zheng 7720ed4c252SIcenowy Zheng [RST_BUS_VE] = { 0x2c4, BIT(0) }, 7730ed4c252SIcenowy Zheng [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, 7740ed4c252SIcenowy Zheng [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 7750ed4c252SIcenowy Zheng [RST_BUS_DE] = { 0x2c4, BIT(12) }, 7760ed4c252SIcenowy Zheng [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 7770ed4c252SIcenowy Zheng 7780ed4c252SIcenowy Zheng [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, 7790ed4c252SIcenowy Zheng 7800ed4c252SIcenowy Zheng [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 7810ed4c252SIcenowy Zheng [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 7820ed4c252SIcenowy Zheng 7830ed4c252SIcenowy Zheng [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 7840ed4c252SIcenowy Zheng [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 7850ed4c252SIcenowy Zheng [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 7860ed4c252SIcenowy Zheng [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 7870ed4c252SIcenowy Zheng [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 7880ed4c252SIcenowy Zheng }; 7890ed4c252SIcenowy Zheng 790d0f11d14SIcenowy Zheng static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { 791d0f11d14SIcenowy Zheng .ccu_clks = sun8i_v3s_ccu_clks, 792d0f11d14SIcenowy Zheng .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), 793d0f11d14SIcenowy Zheng 794d0f11d14SIcenowy Zheng .hw_clks = &sun8i_v3s_hw_clks, 795d0f11d14SIcenowy Zheng 796d0f11d14SIcenowy Zheng .resets = sun8i_v3s_ccu_resets, 797d0f11d14SIcenowy Zheng .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets), 798d0f11d14SIcenowy Zheng }; 799d0f11d14SIcenowy Zheng 8000ed4c252SIcenowy Zheng static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = { 8010ed4c252SIcenowy Zheng .ccu_clks = sun8i_v3_ccu_clks, 8020ed4c252SIcenowy Zheng .num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks), 8030ed4c252SIcenowy Zheng 8040ed4c252SIcenowy Zheng .hw_clks = &sun8i_v3_hw_clks, 8050ed4c252SIcenowy Zheng 8060ed4c252SIcenowy Zheng .resets = sun8i_v3_ccu_resets, 8070ed4c252SIcenowy Zheng .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets), 8080ed4c252SIcenowy Zheng }; 8090ed4c252SIcenowy Zheng 810*7ec03b58SSamuel Holland static int sun8i_v3s_ccu_probe(struct platform_device *pdev) 811d0f11d14SIcenowy Zheng { 812*7ec03b58SSamuel Holland const struct sunxi_ccu_desc *desc; 813d0f11d14SIcenowy Zheng void __iomem *reg; 814d0f11d14SIcenowy Zheng u32 val; 815d0f11d14SIcenowy Zheng 816*7ec03b58SSamuel Holland desc = of_device_get_match_data(&pdev->dev); 817*7ec03b58SSamuel Holland if (!desc) 818*7ec03b58SSamuel Holland return -EINVAL; 819*7ec03b58SSamuel Holland 820*7ec03b58SSamuel Holland reg = devm_platform_ioremap_resource(pdev, 0); 821*7ec03b58SSamuel Holland if (IS_ERR(reg)) 822*7ec03b58SSamuel Holland return PTR_ERR(reg); 823d0f11d14SIcenowy Zheng 82447e4dc4eSTobias Schramm /* Force the PLL-Audio-1x divider to 1 */ 825d0f11d14SIcenowy Zheng val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG); 826d0f11d14SIcenowy Zheng val &= ~GENMASK(19, 16); 82747e4dc4eSTobias Schramm writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG); 828d0f11d14SIcenowy Zheng 829*7ec03b58SSamuel Holland return devm_sunxi_ccu_probe(&pdev->dev, reg, desc); 830d0f11d14SIcenowy Zheng } 8310ed4c252SIcenowy Zheng 832*7ec03b58SSamuel Holland static const struct of_device_id sun8i_v3s_ccu_ids[] = { 8330ed4c252SIcenowy Zheng { 834*7ec03b58SSamuel Holland .compatible = "allwinner,sun8i-v3-ccu", 835*7ec03b58SSamuel Holland .data = &sun8i_v3_ccu_desc, 836*7ec03b58SSamuel Holland }, 8370ed4c252SIcenowy Zheng { 838*7ec03b58SSamuel Holland .compatible = "allwinner,sun8i-v3s-ccu", 839*7ec03b58SSamuel Holland .data = &sun8i_v3s_ccu_desc, 840*7ec03b58SSamuel Holland }, 841*7ec03b58SSamuel Holland { } 842*7ec03b58SSamuel Holland }; 8430ed4c252SIcenowy Zheng 844*7ec03b58SSamuel Holland static struct platform_driver sun8i_v3s_ccu_driver = { 845*7ec03b58SSamuel Holland .probe = sun8i_v3s_ccu_probe, 846*7ec03b58SSamuel Holland .driver = { 847*7ec03b58SSamuel Holland .name = "sun8i-v3s-ccu", 848*7ec03b58SSamuel Holland .suppress_bind_attrs = true, 849*7ec03b58SSamuel Holland .of_match_table = sun8i_v3s_ccu_ids, 850*7ec03b58SSamuel Holland }, 851*7ec03b58SSamuel Holland }; 852*7ec03b58SSamuel Holland module_platform_driver(sun8i_v3s_ccu_driver); 8530ed4c252SIcenowy Zheng 854*7ec03b58SSamuel Holland MODULE_IMPORT_NS(SUNXI_CCU); 855*7ec03b58SSamuel Holland MODULE_LICENSE("GPL"); 856