1d0f11d14SIcenowy Zheng /* 2d0f11d14SIcenowy Zheng * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3d0f11d14SIcenowy Zheng * 4d0f11d14SIcenowy Zheng * Based on ccu-sun8i-h3.c, which is: 5d0f11d14SIcenowy Zheng * Copyright (c) 2016 Maxime Ripard. All rights reserved. 6d0f11d14SIcenowy Zheng * 7d0f11d14SIcenowy Zheng * This software is licensed under the terms of the GNU General Public 8d0f11d14SIcenowy Zheng * License version 2, as published by the Free Software Foundation, and 9d0f11d14SIcenowy Zheng * may be copied, distributed, and modified under those terms. 10d0f11d14SIcenowy Zheng * 11d0f11d14SIcenowy Zheng * This program is distributed in the hope that it will be useful, 12d0f11d14SIcenowy Zheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 13d0f11d14SIcenowy Zheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14d0f11d14SIcenowy Zheng * GNU General Public License for more details. 15d0f11d14SIcenowy Zheng */ 16d0f11d14SIcenowy Zheng 17d0f11d14SIcenowy Zheng #include <linux/clk-provider.h> 18d0f11d14SIcenowy Zheng #include <linux/of_address.h> 19d0f11d14SIcenowy Zheng 20d0f11d14SIcenowy Zheng #include "ccu_common.h" 21d0f11d14SIcenowy Zheng #include "ccu_reset.h" 22d0f11d14SIcenowy Zheng 23d0f11d14SIcenowy Zheng #include "ccu_div.h" 24d0f11d14SIcenowy Zheng #include "ccu_gate.h" 25d0f11d14SIcenowy Zheng #include "ccu_mp.h" 26d0f11d14SIcenowy Zheng #include "ccu_mult.h" 27d0f11d14SIcenowy Zheng #include "ccu_nk.h" 28d0f11d14SIcenowy Zheng #include "ccu_nkm.h" 29d0f11d14SIcenowy Zheng #include "ccu_nkmp.h" 30d0f11d14SIcenowy Zheng #include "ccu_nm.h" 31d0f11d14SIcenowy Zheng #include "ccu_phase.h" 32d0f11d14SIcenowy Zheng 33d0f11d14SIcenowy Zheng #include "ccu-sun8i-v3s.h" 34d0f11d14SIcenowy Zheng 35d0f11d14SIcenowy Zheng static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", 36d0f11d14SIcenowy Zheng "osc24M", 0x000, 37d0f11d14SIcenowy Zheng 8, 5, /* N */ 38d0f11d14SIcenowy Zheng 4, 2, /* K */ 39d0f11d14SIcenowy Zheng 0, 2, /* M */ 40d0f11d14SIcenowy Zheng 16, 2, /* P */ 41d0f11d14SIcenowy Zheng BIT(31), /* gate */ 42d0f11d14SIcenowy Zheng BIT(28), /* lock */ 43d0f11d14SIcenowy Zheng 0); 44d0f11d14SIcenowy Zheng 45d0f11d14SIcenowy Zheng /* 46d0f11d14SIcenowy Zheng * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 47d0f11d14SIcenowy Zheng * the base (2x, 4x and 8x), and one variable divider (the one true 48d0f11d14SIcenowy Zheng * pll audio). 49d0f11d14SIcenowy Zheng * 50d0f11d14SIcenowy Zheng * We don't have any need for the variable divider for now, so we just 51d0f11d14SIcenowy Zheng * hardcode it to match with the clock names 52d0f11d14SIcenowy Zheng */ 53d0f11d14SIcenowy Zheng #define SUN8I_V3S_PLL_AUDIO_REG 0x008 54d0f11d14SIcenowy Zheng 55d0f11d14SIcenowy Zheng static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 56d0f11d14SIcenowy Zheng "osc24M", 0x008, 57d0f11d14SIcenowy Zheng 8, 7, /* N */ 58d0f11d14SIcenowy Zheng 0, 5, /* M */ 59d0f11d14SIcenowy Zheng BIT(31), /* gate */ 60d0f11d14SIcenowy Zheng BIT(28), /* lock */ 61d0f11d14SIcenowy Zheng 0); 62d0f11d14SIcenowy Zheng 63d0f11d14SIcenowy Zheng static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 64d0f11d14SIcenowy Zheng "osc24M", 0x0010, 65d0f11d14SIcenowy Zheng 8, 7, /* N */ 66d0f11d14SIcenowy Zheng 0, 4, /* M */ 67d0f11d14SIcenowy Zheng BIT(24), /* frac enable */ 68d0f11d14SIcenowy Zheng BIT(25), /* frac select */ 69d0f11d14SIcenowy Zheng 270000000, /* frac rate 0 */ 70d0f11d14SIcenowy Zheng 297000000, /* frac rate 1 */ 71d0f11d14SIcenowy Zheng BIT(31), /* gate */ 72d0f11d14SIcenowy Zheng BIT(28), /* lock */ 73d0f11d14SIcenowy Zheng 0); 74d0f11d14SIcenowy Zheng 75d0f11d14SIcenowy Zheng static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 76d0f11d14SIcenowy Zheng "osc24M", 0x0018, 77d0f11d14SIcenowy Zheng 8, 7, /* N */ 78d0f11d14SIcenowy Zheng 0, 4, /* M */ 79d0f11d14SIcenowy Zheng BIT(24), /* frac enable */ 80d0f11d14SIcenowy Zheng BIT(25), /* frac select */ 81d0f11d14SIcenowy Zheng 270000000, /* frac rate 0 */ 82d0f11d14SIcenowy Zheng 297000000, /* frac rate 1 */ 83d0f11d14SIcenowy Zheng BIT(31), /* gate */ 84d0f11d14SIcenowy Zheng BIT(28), /* lock */ 85d0f11d14SIcenowy Zheng 0); 86d0f11d14SIcenowy Zheng 87d0f11d14SIcenowy Zheng static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", 88d0f11d14SIcenowy Zheng "osc24M", 0x020, 89d0f11d14SIcenowy Zheng 8, 5, /* N */ 90d0f11d14SIcenowy Zheng 4, 2, /* K */ 91d0f11d14SIcenowy Zheng 0, 2, /* M */ 92d0f11d14SIcenowy Zheng BIT(31), /* gate */ 93d0f11d14SIcenowy Zheng BIT(28), /* lock */ 94d0f11d14SIcenowy Zheng 0); 95d0f11d14SIcenowy Zheng 96d0f11d14SIcenowy Zheng static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", 97d0f11d14SIcenowy Zheng "osc24M", 0x028, 98d0f11d14SIcenowy Zheng 8, 5, /* N */ 99d0f11d14SIcenowy Zheng 4, 2, /* K */ 100d0f11d14SIcenowy Zheng BIT(31), /* gate */ 101d0f11d14SIcenowy Zheng BIT(28), /* lock */ 102d0f11d14SIcenowy Zheng 2, /* post-div */ 103d0f11d14SIcenowy Zheng 0); 104d0f11d14SIcenowy Zheng 105d0f11d14SIcenowy Zheng static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp", 106d0f11d14SIcenowy Zheng "osc24M", 0x002c, 107d0f11d14SIcenowy Zheng 8, 7, /* N */ 108d0f11d14SIcenowy Zheng 0, 4, /* M */ 109d0f11d14SIcenowy Zheng BIT(24), /* frac enable */ 110d0f11d14SIcenowy Zheng BIT(25), /* frac select */ 111d0f11d14SIcenowy Zheng 270000000, /* frac rate 0 */ 112d0f11d14SIcenowy Zheng 297000000, /* frac rate 1 */ 113d0f11d14SIcenowy Zheng BIT(31), /* gate */ 114d0f11d14SIcenowy Zheng BIT(28), /* lock */ 115d0f11d14SIcenowy Zheng 0); 116d0f11d14SIcenowy Zheng 117d0f11d14SIcenowy Zheng static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", 118d0f11d14SIcenowy Zheng "osc24M", 0x044, 119d0f11d14SIcenowy Zheng 8, 5, /* N */ 120d0f11d14SIcenowy Zheng 4, 2, /* K */ 121d0f11d14SIcenowy Zheng BIT(31), /* gate */ 122d0f11d14SIcenowy Zheng BIT(28), /* lock */ 123d0f11d14SIcenowy Zheng 2, /* post-div */ 124d0f11d14SIcenowy Zheng 0); 125d0f11d14SIcenowy Zheng 126d0f11d14SIcenowy Zheng static const char * const cpu_parents[] = { "osc32k", "osc24M", 127d0f11d14SIcenowy Zheng "pll-cpu", "pll-cpu" }; 128d0f11d14SIcenowy Zheng static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 129d0f11d14SIcenowy Zheng 0x050, 16, 2, CLK_IS_CRITICAL); 130d0f11d14SIcenowy Zheng 131d0f11d14SIcenowy Zheng static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0); 132d0f11d14SIcenowy Zheng 133d0f11d14SIcenowy Zheng static const char * const ahb1_parents[] = { "osc32k", "osc24M", 134d0f11d14SIcenowy Zheng "axi", "pll-periph0" }; 13513e0dde8SChen-Yu Tsai static const struct ccu_mux_var_prediv ahb1_predivs[] = { 13613e0dde8SChen-Yu Tsai { .index = 3, .shift = 6, .width = 2 }, 13713e0dde8SChen-Yu Tsai }; 138d0f11d14SIcenowy Zheng static struct ccu_div ahb1_clk = { 139d0f11d14SIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 140d0f11d14SIcenowy Zheng 141d0f11d14SIcenowy Zheng .mux = { 142d0f11d14SIcenowy Zheng .shift = 12, 143d0f11d14SIcenowy Zheng .width = 2, 144d0f11d14SIcenowy Zheng 14513e0dde8SChen-Yu Tsai .var_predivs = ahb1_predivs, 14613e0dde8SChen-Yu Tsai .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 147d0f11d14SIcenowy Zheng }, 148d0f11d14SIcenowy Zheng 149d0f11d14SIcenowy Zheng .common = { 150d0f11d14SIcenowy Zheng .reg = 0x054, 151d0f11d14SIcenowy Zheng .features = CCU_FEATURE_VARIABLE_PREDIV, 152d0f11d14SIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("ahb1", 153d0f11d14SIcenowy Zheng ahb1_parents, 154d0f11d14SIcenowy Zheng &ccu_div_ops, 155d0f11d14SIcenowy Zheng 0), 156d0f11d14SIcenowy Zheng }, 157d0f11d14SIcenowy Zheng }; 158d0f11d14SIcenowy Zheng 159d0f11d14SIcenowy Zheng static struct clk_div_table apb1_div_table[] = { 160d0f11d14SIcenowy Zheng { .val = 0, .div = 2 }, 161d0f11d14SIcenowy Zheng { .val = 1, .div = 2 }, 162d0f11d14SIcenowy Zheng { .val = 2, .div = 4 }, 163d0f11d14SIcenowy Zheng { .val = 3, .div = 8 }, 164d0f11d14SIcenowy Zheng { /* Sentinel */ }, 165d0f11d14SIcenowy Zheng }; 166d0f11d14SIcenowy Zheng static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 167d0f11d14SIcenowy Zheng 0x054, 8, 2, apb1_div_table, 0); 168d0f11d14SIcenowy Zheng 169d0f11d14SIcenowy Zheng static const char * const apb2_parents[] = { "osc32k", "osc24M", 170d0f11d14SIcenowy Zheng "pll-periph0", "pll-periph0" }; 171d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 172d0f11d14SIcenowy Zheng 0, 5, /* M */ 173d0f11d14SIcenowy Zheng 16, 2, /* P */ 174d0f11d14SIcenowy Zheng 24, 2, /* mux */ 175d0f11d14SIcenowy Zheng 0); 176d0f11d14SIcenowy Zheng 177d0f11d14SIcenowy Zheng static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" }; 178d0f11d14SIcenowy Zheng static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { 179d0f11d14SIcenowy Zheng { .index = 1, .div = 2 }, 180d0f11d14SIcenowy Zheng }; 181d0f11d14SIcenowy Zheng static struct ccu_mux ahb2_clk = { 182d0f11d14SIcenowy Zheng .mux = { 183d0f11d14SIcenowy Zheng .shift = 0, 184d0f11d14SIcenowy Zheng .width = 1, 185d0f11d14SIcenowy Zheng .fixed_predivs = ahb2_fixed_predivs, 186d0f11d14SIcenowy Zheng .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), 187d0f11d14SIcenowy Zheng }, 188d0f11d14SIcenowy Zheng 189d0f11d14SIcenowy Zheng .common = { 190d0f11d14SIcenowy Zheng .reg = 0x05c, 191d0f11d14SIcenowy Zheng .features = CCU_FEATURE_FIXED_PREDIV, 192d0f11d14SIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("ahb2", 193d0f11d14SIcenowy Zheng ahb2_parents, 194d0f11d14SIcenowy Zheng &ccu_mux_ops, 195d0f11d14SIcenowy Zheng 0), 196d0f11d14SIcenowy Zheng }, 197d0f11d14SIcenowy Zheng }; 198d0f11d14SIcenowy Zheng 199d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 200d0f11d14SIcenowy Zheng 0x060, BIT(5), 0); 201d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 202d0f11d14SIcenowy Zheng 0x060, BIT(6), 0); 203d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 204d0f11d14SIcenowy Zheng 0x060, BIT(8), 0); 205d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 206d0f11d14SIcenowy Zheng 0x060, BIT(9), 0); 207d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 208d0f11d14SIcenowy Zheng 0x060, BIT(10), 0); 209d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 210d0f11d14SIcenowy Zheng 0x060, BIT(14), 0); 211d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 212d0f11d14SIcenowy Zheng 0x060, BIT(17), 0); 213d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 214d0f11d14SIcenowy Zheng 0x060, BIT(19), 0); 215d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 216d0f11d14SIcenowy Zheng 0x060, BIT(20), 0); 217d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 218d0f11d14SIcenowy Zheng 0x060, BIT(24), 0); 219d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 220d0f11d14SIcenowy Zheng 0x060, BIT(26), 0); 221d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 222d0f11d14SIcenowy Zheng 0x060, BIT(29), 0); 223d0f11d14SIcenowy Zheng 224d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 225d0f11d14SIcenowy Zheng 0x064, BIT(0), 0); 226d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 227d0f11d14SIcenowy Zheng 0x064, BIT(4), 0); 228d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 229d0f11d14SIcenowy Zheng 0x064, BIT(8), 0); 230d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 231d0f11d14SIcenowy Zheng 0x064, BIT(12), 0); 232d0f11d14SIcenowy Zheng 233d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 234d0f11d14SIcenowy Zheng 0x068, BIT(0), 0); 235d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 236d0f11d14SIcenowy Zheng 0x068, BIT(5), 0); 237d0f11d14SIcenowy Zheng 238d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 239d0f11d14SIcenowy Zheng 0x06c, BIT(0), 0); 240d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 241d0f11d14SIcenowy Zheng 0x06c, BIT(1), 0); 242d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 243d0f11d14SIcenowy Zheng 0x06c, BIT(16), 0); 244d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 245d0f11d14SIcenowy Zheng 0x06c, BIT(17), 0); 246d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 247d0f11d14SIcenowy Zheng 0x06c, BIT(18), 0); 248d0f11d14SIcenowy Zheng 249d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1", 250d0f11d14SIcenowy Zheng 0x070, BIT(0), 0); 251d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 252d0f11d14SIcenowy Zheng 0x070, BIT(7), 0); 253d0f11d14SIcenowy Zheng 254d0f11d14SIcenowy Zheng static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 255d0f11d14SIcenowy Zheng "pll-periph1" }; 256d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 257d0f11d14SIcenowy Zheng 0, 4, /* M */ 258d0f11d14SIcenowy Zheng 16, 2, /* P */ 259d0f11d14SIcenowy Zheng 24, 2, /* mux */ 260d0f11d14SIcenowy Zheng BIT(31), /* gate */ 261d0f11d14SIcenowy Zheng 0); 262d0f11d14SIcenowy Zheng 263d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 264d0f11d14SIcenowy Zheng 0x088, 20, 3, 0); 265d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 266d0f11d14SIcenowy Zheng 0x088, 8, 3, 0); 267d0f11d14SIcenowy Zheng 268d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 269d0f11d14SIcenowy Zheng 0, 4, /* M */ 270d0f11d14SIcenowy Zheng 16, 2, /* P */ 271d0f11d14SIcenowy Zheng 24, 2, /* mux */ 272d0f11d14SIcenowy Zheng BIT(31), /* gate */ 273d0f11d14SIcenowy Zheng 0); 274d0f11d14SIcenowy Zheng 275d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 276d0f11d14SIcenowy Zheng 0x08c, 20, 3, 0); 277d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 278d0f11d14SIcenowy Zheng 0x08c, 8, 3, 0); 279d0f11d14SIcenowy Zheng 280d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 281d0f11d14SIcenowy Zheng 0, 4, /* M */ 282d0f11d14SIcenowy Zheng 16, 2, /* P */ 283d0f11d14SIcenowy Zheng 24, 2, /* mux */ 284d0f11d14SIcenowy Zheng BIT(31), /* gate */ 285d0f11d14SIcenowy Zheng 0); 286d0f11d14SIcenowy Zheng 287d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", 288d0f11d14SIcenowy Zheng 0x090, 20, 3, 0); 289d0f11d14SIcenowy Zheng static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", 290d0f11d14SIcenowy Zheng 0x090, 8, 3, 0); 291d0f11d14SIcenowy Zheng 292d0f11d14SIcenowy Zheng static const char * const ce_parents[] = { "osc24M", "pll-periph0", }; 293d0f11d14SIcenowy Zheng 294d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c, 295d0f11d14SIcenowy Zheng 0, 4, /* M */ 296d0f11d14SIcenowy Zheng 16, 2, /* P */ 297d0f11d14SIcenowy Zheng 24, 2, /* mux */ 298d0f11d14SIcenowy Zheng BIT(31), /* gate */ 299d0f11d14SIcenowy Zheng 0); 300d0f11d14SIcenowy Zheng 301d0f11d14SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 302d0f11d14SIcenowy Zheng 0, 4, /* M */ 303d0f11d14SIcenowy Zheng 16, 2, /* P */ 304d0f11d14SIcenowy Zheng 24, 2, /* mux */ 305d0f11d14SIcenowy Zheng BIT(31), /* gate */ 306d0f11d14SIcenowy Zheng 0); 307d0f11d14SIcenowy Zheng 308d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 309d0f11d14SIcenowy Zheng 0x0cc, BIT(8), 0); 310d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 311d0f11d14SIcenowy Zheng 0x0cc, BIT(16), 0); 312d0f11d14SIcenowy Zheng 313d0f11d14SIcenowy Zheng static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" }; 314d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 315d0f11d14SIcenowy Zheng 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); 316d0f11d14SIcenowy Zheng 317d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 318d0f11d14SIcenowy Zheng 0x100, BIT(0), 0); 319d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 320d0f11d14SIcenowy Zheng 0x100, BIT(1), 0); 321d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram", 322d0f11d14SIcenowy Zheng 0x100, BIT(17), 0); 323d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", 324d0f11d14SIcenowy Zheng 0x100, BIT(18), 0); 325d0f11d14SIcenowy Zheng 326d0f11d14SIcenowy Zheng static const char * const de_parents[] = { "pll-video", "pll-periph0" }; 327d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 328d0f11d14SIcenowy Zheng 0x104, 0, 4, 24, 2, BIT(31), 0); 329d0f11d14SIcenowy Zheng 330d0f11d14SIcenowy Zheng static const char * const tcon_parents[] = { "pll-video" }; 331d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, 332d0f11d14SIcenowy Zheng 0x118, 0, 4, 24, 3, BIT(31), 0); 333d0f11d14SIcenowy Zheng 334d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 335d0f11d14SIcenowy Zheng 0x130, BIT(31), 0); 336d0f11d14SIcenowy Zheng 337d0f11d14SIcenowy Zheng static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", 338d0f11d14SIcenowy Zheng "pll-periph0", "pll-periph1" }; 339d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 340d0f11d14SIcenowy Zheng 0x130, 0, 5, 8, 3, BIT(15), 0); 341d0f11d14SIcenowy Zheng 342d0f11d14SIcenowy Zheng static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" }; 343d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents, 344d0f11d14SIcenowy Zheng 0x134, 16, 4, 24, 3, BIT(31), 0); 345d0f11d14SIcenowy Zheng 346d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents, 347d0f11d14SIcenowy Zheng 0x134, 0, 5, 8, 3, BIT(15), 0); 348d0f11d14SIcenowy Zheng 349d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 350d0f11d14SIcenowy Zheng 0x13c, 16, 3, BIT(31), 0); 351d0f11d14SIcenowy Zheng 352d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 353d0f11d14SIcenowy Zheng 0x140, BIT(31), CLK_SET_RATE_PARENT); 354d0f11d14SIcenowy Zheng static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 355d0f11d14SIcenowy Zheng 0x144, BIT(31), 0); 356d0f11d14SIcenowy Zheng 357d0f11d14SIcenowy Zheng static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 358d0f11d14SIcenowy Zheng "pll-ddr" }; 359d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 360d0f11d14SIcenowy Zheng 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 361d0f11d14SIcenowy Zheng 362d0f11d14SIcenowy Zheng static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0", 363d0f11d14SIcenowy Zheng "pll-isp" }; 364d0f11d14SIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents, 365d0f11d14SIcenowy Zheng 0x16c, 0, 3, 24, 2, BIT(31), 0); 366d0f11d14SIcenowy Zheng 367d0f11d14SIcenowy Zheng static struct ccu_common *sun8i_v3s_ccu_clks[] = { 368d0f11d14SIcenowy Zheng &pll_cpu_clk.common, 369d0f11d14SIcenowy Zheng &pll_audio_base_clk.common, 370d0f11d14SIcenowy Zheng &pll_video_clk.common, 371d0f11d14SIcenowy Zheng &pll_ve_clk.common, 372d0f11d14SIcenowy Zheng &pll_ddr_clk.common, 373d0f11d14SIcenowy Zheng &pll_periph0_clk.common, 374d0f11d14SIcenowy Zheng &pll_isp_clk.common, 375d0f11d14SIcenowy Zheng &pll_periph1_clk.common, 376d0f11d14SIcenowy Zheng &cpu_clk.common, 377d0f11d14SIcenowy Zheng &axi_clk.common, 378d0f11d14SIcenowy Zheng &ahb1_clk.common, 379d0f11d14SIcenowy Zheng &apb1_clk.common, 380d0f11d14SIcenowy Zheng &apb2_clk.common, 381d0f11d14SIcenowy Zheng &ahb2_clk.common, 382d0f11d14SIcenowy Zheng &bus_ce_clk.common, 383d0f11d14SIcenowy Zheng &bus_dma_clk.common, 384d0f11d14SIcenowy Zheng &bus_mmc0_clk.common, 385d0f11d14SIcenowy Zheng &bus_mmc1_clk.common, 386d0f11d14SIcenowy Zheng &bus_mmc2_clk.common, 387d0f11d14SIcenowy Zheng &bus_dram_clk.common, 388d0f11d14SIcenowy Zheng &bus_emac_clk.common, 389d0f11d14SIcenowy Zheng &bus_hstimer_clk.common, 390d0f11d14SIcenowy Zheng &bus_spi0_clk.common, 391d0f11d14SIcenowy Zheng &bus_otg_clk.common, 392d0f11d14SIcenowy Zheng &bus_ehci0_clk.common, 393d0f11d14SIcenowy Zheng &bus_ohci0_clk.common, 394d0f11d14SIcenowy Zheng &bus_ve_clk.common, 395d0f11d14SIcenowy Zheng &bus_tcon0_clk.common, 396d0f11d14SIcenowy Zheng &bus_csi_clk.common, 397d0f11d14SIcenowy Zheng &bus_de_clk.common, 398d0f11d14SIcenowy Zheng &bus_codec_clk.common, 399d0f11d14SIcenowy Zheng &bus_pio_clk.common, 400d0f11d14SIcenowy Zheng &bus_i2c0_clk.common, 401d0f11d14SIcenowy Zheng &bus_i2c1_clk.common, 402d0f11d14SIcenowy Zheng &bus_uart0_clk.common, 403d0f11d14SIcenowy Zheng &bus_uart1_clk.common, 404d0f11d14SIcenowy Zheng &bus_uart2_clk.common, 405d0f11d14SIcenowy Zheng &bus_ephy_clk.common, 406d0f11d14SIcenowy Zheng &bus_dbg_clk.common, 407d0f11d14SIcenowy Zheng &mmc0_clk.common, 408d0f11d14SIcenowy Zheng &mmc0_sample_clk.common, 409d0f11d14SIcenowy Zheng &mmc0_output_clk.common, 410d0f11d14SIcenowy Zheng &mmc1_clk.common, 411d0f11d14SIcenowy Zheng &mmc1_sample_clk.common, 412d0f11d14SIcenowy Zheng &mmc1_output_clk.common, 413d0f11d14SIcenowy Zheng &mmc2_clk.common, 414d0f11d14SIcenowy Zheng &mmc2_sample_clk.common, 415d0f11d14SIcenowy Zheng &mmc2_output_clk.common, 416d0f11d14SIcenowy Zheng &ce_clk.common, 417d0f11d14SIcenowy Zheng &spi0_clk.common, 418d0f11d14SIcenowy Zheng &usb_phy0_clk.common, 419d0f11d14SIcenowy Zheng &usb_ohci0_clk.common, 420d0f11d14SIcenowy Zheng &dram_clk.common, 421d0f11d14SIcenowy Zheng &dram_ve_clk.common, 422d0f11d14SIcenowy Zheng &dram_csi_clk.common, 423d0f11d14SIcenowy Zheng &dram_ohci_clk.common, 424d0f11d14SIcenowy Zheng &dram_ehci_clk.common, 425d0f11d14SIcenowy Zheng &de_clk.common, 426d0f11d14SIcenowy Zheng &tcon_clk.common, 427d0f11d14SIcenowy Zheng &csi_misc_clk.common, 428d0f11d14SIcenowy Zheng &csi0_mclk_clk.common, 429d0f11d14SIcenowy Zheng &csi1_sclk_clk.common, 430d0f11d14SIcenowy Zheng &csi1_mclk_clk.common, 431d0f11d14SIcenowy Zheng &ve_clk.common, 432d0f11d14SIcenowy Zheng &ac_dig_clk.common, 433d0f11d14SIcenowy Zheng &avs_clk.common, 434d0f11d14SIcenowy Zheng &mbus_clk.common, 435d0f11d14SIcenowy Zheng &mipi_csi_clk.common, 436d0f11d14SIcenowy Zheng }; 437d0f11d14SIcenowy Zheng 438d0f11d14SIcenowy Zheng /* We hardcode the divider to 4 for now */ 439d0f11d14SIcenowy Zheng static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 440d0f11d14SIcenowy Zheng "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 441d0f11d14SIcenowy Zheng static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 442d0f11d14SIcenowy Zheng "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 443d0f11d14SIcenowy Zheng static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 444d0f11d14SIcenowy Zheng "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 445d0f11d14SIcenowy Zheng static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 446d0f11d14SIcenowy Zheng "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 447d0f11d14SIcenowy Zheng static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", 448d0f11d14SIcenowy Zheng "pll-periph0", 1, 2, 0); 449d0f11d14SIcenowy Zheng 450d0f11d14SIcenowy Zheng static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { 451d0f11d14SIcenowy Zheng .hws = { 452d0f11d14SIcenowy Zheng [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 453d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 454d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 455d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 456d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 457d0f11d14SIcenowy Zheng [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 458d0f11d14SIcenowy Zheng [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 459d0f11d14SIcenowy Zheng [CLK_PLL_VE] = &pll_ve_clk.common.hw, 460d0f11d14SIcenowy Zheng [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, 461d0f11d14SIcenowy Zheng [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 462d0f11d14SIcenowy Zheng [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 463d0f11d14SIcenowy Zheng [CLK_PLL_ISP] = &pll_isp_clk.common.hw, 464d0f11d14SIcenowy Zheng [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 465d0f11d14SIcenowy Zheng [CLK_CPU] = &cpu_clk.common.hw, 466d0f11d14SIcenowy Zheng [CLK_AXI] = &axi_clk.common.hw, 467d0f11d14SIcenowy Zheng [CLK_AHB1] = &ahb1_clk.common.hw, 468d0f11d14SIcenowy Zheng [CLK_APB1] = &apb1_clk.common.hw, 469d0f11d14SIcenowy Zheng [CLK_APB2] = &apb2_clk.common.hw, 470d0f11d14SIcenowy Zheng [CLK_AHB2] = &ahb2_clk.common.hw, 471d0f11d14SIcenowy Zheng [CLK_BUS_CE] = &bus_ce_clk.common.hw, 472d0f11d14SIcenowy Zheng [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 473d0f11d14SIcenowy Zheng [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 474d0f11d14SIcenowy Zheng [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 475d0f11d14SIcenowy Zheng [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 476d0f11d14SIcenowy Zheng [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 477d0f11d14SIcenowy Zheng [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 478d0f11d14SIcenowy Zheng [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 479d0f11d14SIcenowy Zheng [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 480d0f11d14SIcenowy Zheng [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 481d0f11d14SIcenowy Zheng [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 482d0f11d14SIcenowy Zheng [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 483d0f11d14SIcenowy Zheng [CLK_BUS_VE] = &bus_ve_clk.common.hw, 484d0f11d14SIcenowy Zheng [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 485d0f11d14SIcenowy Zheng [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 486d0f11d14SIcenowy Zheng [CLK_BUS_DE] = &bus_de_clk.common.hw, 487d0f11d14SIcenowy Zheng [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 488d0f11d14SIcenowy Zheng [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 489d0f11d14SIcenowy Zheng [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 490d0f11d14SIcenowy Zheng [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 491d0f11d14SIcenowy Zheng [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 492d0f11d14SIcenowy Zheng [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 493d0f11d14SIcenowy Zheng [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 494d0f11d14SIcenowy Zheng [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, 495d0f11d14SIcenowy Zheng [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 496d0f11d14SIcenowy Zheng [CLK_MMC0] = &mmc0_clk.common.hw, 497d0f11d14SIcenowy Zheng [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 498d0f11d14SIcenowy Zheng [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 499d0f11d14SIcenowy Zheng [CLK_MMC1] = &mmc1_clk.common.hw, 500d0f11d14SIcenowy Zheng [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 501d0f11d14SIcenowy Zheng [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 502d0f11d14SIcenowy Zheng [CLK_CE] = &ce_clk.common.hw, 503d0f11d14SIcenowy Zheng [CLK_SPI0] = &spi0_clk.common.hw, 504d0f11d14SIcenowy Zheng [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 505d0f11d14SIcenowy Zheng [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 506d0f11d14SIcenowy Zheng [CLK_DRAM] = &dram_clk.common.hw, 507d0f11d14SIcenowy Zheng [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 508d0f11d14SIcenowy Zheng [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 509d0f11d14SIcenowy Zheng [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw, 510d0f11d14SIcenowy Zheng [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw, 511d0f11d14SIcenowy Zheng [CLK_DE] = &de_clk.common.hw, 512d0f11d14SIcenowy Zheng [CLK_TCON0] = &tcon_clk.common.hw, 513d0f11d14SIcenowy Zheng [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 514d0f11d14SIcenowy Zheng [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 515d0f11d14SIcenowy Zheng [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, 516d0f11d14SIcenowy Zheng [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 517d0f11d14SIcenowy Zheng [CLK_VE] = &ve_clk.common.hw, 518d0f11d14SIcenowy Zheng [CLK_AC_DIG] = &ac_dig_clk.common.hw, 519d0f11d14SIcenowy Zheng [CLK_AVS] = &avs_clk.common.hw, 520d0f11d14SIcenowy Zheng [CLK_MBUS] = &mbus_clk.common.hw, 521d0f11d14SIcenowy Zheng [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, 522d0f11d14SIcenowy Zheng }, 523d0f11d14SIcenowy Zheng .num = CLK_NUMBER, 524d0f11d14SIcenowy Zheng }; 525d0f11d14SIcenowy Zheng 526d0f11d14SIcenowy Zheng static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { 527d0f11d14SIcenowy Zheng [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 528d0f11d14SIcenowy Zheng 529d0f11d14SIcenowy Zheng [RST_MBUS] = { 0x0fc, BIT(31) }, 530d0f11d14SIcenowy Zheng 531d0f11d14SIcenowy Zheng [RST_BUS_CE] = { 0x2c0, BIT(5) }, 532d0f11d14SIcenowy Zheng [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 533d0f11d14SIcenowy Zheng [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 534d0f11d14SIcenowy Zheng [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 535d0f11d14SIcenowy Zheng [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 536d0f11d14SIcenowy Zheng [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 537d0f11d14SIcenowy Zheng [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 538d0f11d14SIcenowy Zheng [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 539d0f11d14SIcenowy Zheng [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 5407ffc781eSYong Deng [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 541d0f11d14SIcenowy Zheng [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, 542d0f11d14SIcenowy Zheng [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, 543d0f11d14SIcenowy Zheng 544d0f11d14SIcenowy Zheng [RST_BUS_VE] = { 0x2c4, BIT(0) }, 545d0f11d14SIcenowy Zheng [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, 546d0f11d14SIcenowy Zheng [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 547d0f11d14SIcenowy Zheng [RST_BUS_DE] = { 0x2c4, BIT(12) }, 548d0f11d14SIcenowy Zheng [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 549d0f11d14SIcenowy Zheng 550d0f11d14SIcenowy Zheng [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, 551d0f11d14SIcenowy Zheng 552d0f11d14SIcenowy Zheng [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 553d0f11d14SIcenowy Zheng 554d0f11d14SIcenowy Zheng [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 555d0f11d14SIcenowy Zheng [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 556d0f11d14SIcenowy Zheng [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 557d0f11d14SIcenowy Zheng [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 558d0f11d14SIcenowy Zheng [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 559d0f11d14SIcenowy Zheng }; 560d0f11d14SIcenowy Zheng 561d0f11d14SIcenowy Zheng static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { 562d0f11d14SIcenowy Zheng .ccu_clks = sun8i_v3s_ccu_clks, 563d0f11d14SIcenowy Zheng .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), 564d0f11d14SIcenowy Zheng 565d0f11d14SIcenowy Zheng .hw_clks = &sun8i_v3s_hw_clks, 566d0f11d14SIcenowy Zheng 567d0f11d14SIcenowy Zheng .resets = sun8i_v3s_ccu_resets, 568d0f11d14SIcenowy Zheng .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets), 569d0f11d14SIcenowy Zheng }; 570d0f11d14SIcenowy Zheng 571d0f11d14SIcenowy Zheng static void __init sun8i_v3s_ccu_setup(struct device_node *node) 572d0f11d14SIcenowy Zheng { 573d0f11d14SIcenowy Zheng void __iomem *reg; 574d0f11d14SIcenowy Zheng u32 val; 575d0f11d14SIcenowy Zheng 576d0f11d14SIcenowy Zheng reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 577d0f11d14SIcenowy Zheng if (IS_ERR(reg)) { 578d0f11d14SIcenowy Zheng pr_err("%s: Could not map the clock registers\n", 579d0f11d14SIcenowy Zheng of_node_full_name(node)); 580d0f11d14SIcenowy Zheng return; 581d0f11d14SIcenowy Zheng } 582d0f11d14SIcenowy Zheng 583d0f11d14SIcenowy Zheng /* Force the PLL-Audio-1x divider to 4 */ 584d0f11d14SIcenowy Zheng val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG); 585d0f11d14SIcenowy Zheng val &= ~GENMASK(19, 16); 586d0f11d14SIcenowy Zheng writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG); 587d0f11d14SIcenowy Zheng 588d0f11d14SIcenowy Zheng sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc); 589d0f11d14SIcenowy Zheng } 590d0f11d14SIcenowy Zheng CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu", 591d0f11d14SIcenowy Zheng sun8i_v3s_ccu_setup); 592