1 /*
2  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 
17 #include "ccu_common.h"
18 #include "ccu_reset.h"
19 
20 #include "ccu_div.h"
21 #include "ccu_gate.h"
22 #include "ccu_mp.h"
23 #include "ccu_mult.h"
24 #include "ccu_nk.h"
25 #include "ccu_nkm.h"
26 #include "ccu_nkmp.h"
27 #include "ccu_nm.h"
28 #include "ccu_phase.h"
29 
30 #include "ccu-sun8i-r40.h"
31 
32 /* TODO: The result of N*K is required to be in [10, 88] range. */
33 static struct ccu_nkmp pll_cpu_clk = {
34 	.enable		= BIT(31),
35 	.lock		= BIT(28),
36 	.n		= _SUNXI_CCU_MULT(8, 5),
37 	.k		= _SUNXI_CCU_MULT(4, 2),
38 	.m		= _SUNXI_CCU_DIV(0, 2),
39 	.p		= _SUNXI_CCU_DIV_MAX(16, 2, 4),
40 	.common		= {
41 		.reg		= 0x000,
42 		.hw.init	= CLK_HW_INIT("pll-cpu",
43 					      "osc24M",
44 					      &ccu_nkmp_ops,
45 					      CLK_SET_RATE_UNGATE),
46 	},
47 };
48 
49 /*
50  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
51  * the base (2x, 4x and 8x), and one variable divider (the one true
52  * pll audio).
53  *
54  * We don't have any need for the variable divider for now, so we just
55  * hardcode it to match with the clock names
56  */
57 #define SUN8I_R40_PLL_AUDIO_REG	0x008
58 
59 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
60 				   "osc24M", 0x008,
61 				   8, 7,	/* N */
62 				   0, 5,	/* M */
63 				   BIT(31),	/* gate */
64 				   BIT(28),	/* lock */
65 				   CLK_SET_RATE_UNGATE);
66 
67 /* TODO: The result of N/M is required to be in [8, 25] range. */
68 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
69 					"osc24M", 0x0010,
70 					8, 7,		/* N */
71 					0, 4,		/* M */
72 					BIT(24),	/* frac enable */
73 					BIT(25),	/* frac select */
74 					270000000,	/* frac rate 0 */
75 					297000000,	/* frac rate 1 */
76 					BIT(31),	/* gate */
77 					BIT(28),	/* lock */
78 					CLK_SET_RATE_UNGATE);
79 
80 /* TODO: The result of N/M is required to be in [8, 25] range. */
81 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
82 					"osc24M", 0x0018,
83 					8, 7,		/* N */
84 					0, 4,		/* M */
85 					BIT(24),	/* frac enable */
86 					BIT(25),	/* frac select */
87 					270000000,	/* frac rate 0 */
88 					297000000,	/* frac rate 1 */
89 					BIT(31),	/* gate */
90 					BIT(28),	/* lock */
91 					CLK_SET_RATE_UNGATE);
92 
93 /* TODO: The result of N*K is required to be in [10, 77] range. */
94 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
95 				    "osc24M", 0x020,
96 				    8, 5,	/* N */
97 				    4, 2,	/* K */
98 				    0, 2,	/* M */
99 				    BIT(31),	/* gate */
100 				    BIT(28),	/* lock */
101 				    CLK_SET_RATE_UNGATE);
102 
103 /* TODO: The result of N*K is required to be in [21, 58] range. */
104 static struct ccu_nk pll_periph0_clk = {
105 	.enable		= BIT(31),
106 	.lock		= BIT(28),
107 	.n		= _SUNXI_CCU_MULT(8, 5),
108 	.k		= _SUNXI_CCU_MULT(4, 2),
109 	.fixed_post_div	= 2,
110 	.common		= {
111 		.reg		= 0x028,
112 		.features	= CCU_FEATURE_FIXED_POSTDIV,
113 		.hw.init	= CLK_HW_INIT("pll-periph0", "osc24M",
114 					      &ccu_nk_ops,
115 					      CLK_SET_RATE_UNGATE),
116 	},
117 };
118 
119 static struct ccu_div pll_periph0_sata_clk = {
120 	.enable		= BIT(24),
121 	.div		= _SUNXI_CCU_DIV(0, 2),
122 	/*
123 	 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
124 	 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
125 	 * 6/2 = 3.
126 	 */
127 	.fixed_post_div	= 3,
128 	.common		= {
129 		.reg		= 0x028,
130 		.features	= CCU_FEATURE_FIXED_POSTDIV,
131 		.hw.init	= CLK_HW_INIT("pll-periph0-sata",
132 					      "pll-periph0",
133 					      &ccu_div_ops, 0),
134 	},
135 };
136 
137 /* TODO: The result of N*K is required to be in [21, 58] range. */
138 static struct ccu_nk pll_periph1_clk = {
139 	.enable		= BIT(31),
140 	.lock		= BIT(28),
141 	.n		= _SUNXI_CCU_MULT(8, 5),
142 	.k		= _SUNXI_CCU_MULT(4, 2),
143 	.fixed_post_div	= 2,
144 	.common		= {
145 		.reg		= 0x02c,
146 		.features	= CCU_FEATURE_FIXED_POSTDIV,
147 		.hw.init	= CLK_HW_INIT("pll-periph1", "osc24M",
148 					      &ccu_nk_ops,
149 					      CLK_SET_RATE_UNGATE),
150 	},
151 };
152 
153 /* TODO: The result of N/M is required to be in [8, 25] range. */
154 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
155 					"osc24M", 0x030,
156 					8, 7,		/* N */
157 					0, 4,		/* M */
158 					BIT(24),	/* frac enable */
159 					BIT(25),	/* frac select */
160 					270000000,	/* frac rate 0 */
161 					297000000,	/* frac rate 1 */
162 					BIT(31),	/* gate */
163 					BIT(28),	/* lock */
164 					CLK_SET_RATE_UNGATE);
165 
166 static struct ccu_nkm pll_sata_clk = {
167 	.enable		= BIT(31),
168 	.lock		= BIT(28),
169 	.n		= _SUNXI_CCU_MULT(8, 5),
170 	.k		= _SUNXI_CCU_MULT(4, 2),
171 	.m		= _SUNXI_CCU_DIV(0, 2),
172 	.fixed_post_div	= 6,
173 	.common		= {
174 		.reg		= 0x034,
175 		.features	= CCU_FEATURE_FIXED_POSTDIV,
176 		.hw.init	= CLK_HW_INIT("pll-sata", "osc24M",
177 					      &ccu_nkm_ops,
178 					      CLK_SET_RATE_UNGATE),
179 	},
180 };
181 
182 static const char * const pll_sata_out_parents[] = { "pll-sata",
183 						     "pll-periph0-sata" };
184 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
185 			       pll_sata_out_parents, 0x034,
186 			       30, 1,	/* mux */
187 			       BIT(14),	/* gate */
188 			       CLK_SET_RATE_PARENT);
189 
190 /* TODO: The result of N/M is required to be in [8, 25] range. */
191 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
192 					"osc24M", 0x038,
193 					8, 7,		/* N */
194 					0, 4,		/* M */
195 					BIT(24),	/* frac enable */
196 					BIT(25),	/* frac select */
197 					270000000,	/* frac rate 0 */
198 					297000000,	/* frac rate 1 */
199 					BIT(31),	/* gate */
200 					BIT(28),	/* lock */
201 					CLK_SET_RATE_UNGATE);
202 
203 /*
204  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
205  *
206  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
207  * integer / fractional clock with switchable multipliers and dividers.
208  * This is not supported here. We hardcode the PLL to MIPI mode.
209  *
210  * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
211  * which cannot be implemented now.
212  */
213 #define SUN8I_R40_PLL_MIPI_REG	0x040
214 
215 static const char * const pll_mipi_parents[] = { "pll-video0" };
216 static struct ccu_nkm pll_mipi_clk = {
217 	.enable	= BIT(31) | BIT(23) | BIT(22),
218 	.lock	= BIT(28),
219 	.n	= _SUNXI_CCU_MULT(8, 4),
220 	.k	= _SUNXI_CCU_MULT_MIN(4, 2, 2),
221 	.m	= _SUNXI_CCU_DIV(0, 4),
222 	.mux	= _SUNXI_CCU_MUX(21, 1),
223 	.common	= {
224 		.reg		= 0x040,
225 		.hw.init	= CLK_HW_INIT_PARENTS("pll-mipi",
226 						      pll_mipi_parents,
227 						      &ccu_nkm_ops,
228 						      CLK_SET_RATE_UNGATE)
229 	},
230 };
231 
232 /* TODO: The result of N/M is required to be in [8, 25] range. */
233 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
234 					"osc24M", 0x048,
235 					8, 7,		/* N */
236 					0, 4,		/* M */
237 					BIT(24),	/* frac enable */
238 					BIT(25),	/* frac select */
239 					270000000,	/* frac rate 0 */
240 					297000000,	/* frac rate 1 */
241 					BIT(31),	/* gate */
242 					BIT(28),	/* lock */
243 					CLK_SET_RATE_UNGATE);
244 
245 /* TODO: The N factor is required to be in [16, 75] range. */
246 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
247 				   "osc24M", 0x04c,
248 				   8, 7,	/* N */
249 				   0, 2,	/* M */
250 				   BIT(31),	/* gate */
251 				   BIT(28),	/* lock */
252 				   CLK_SET_RATE_UNGATE);
253 
254 static const char * const cpu_parents[] = { "osc32k", "osc24M",
255 					     "pll-cpu", "pll-cpu" };
256 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
257 		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
258 
259 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
260 
261 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
262 					     "axi", "pll-periph0" };
263 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
264 	{ .index = 3, .shift = 6, .width = 2 },
265 };
266 static struct ccu_div ahb1_clk = {
267 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
268 
269 	.mux		= {
270 		.shift	= 12,
271 		.width	= 2,
272 
273 		.var_predivs	= ahb1_predivs,
274 		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
275 	},
276 
277 	.common		= {
278 		.reg		= 0x054,
279 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
280 		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
281 						      ahb1_parents,
282 						      &ccu_div_ops,
283 						      0),
284 	},
285 };
286 
287 static struct clk_div_table apb1_div_table[] = {
288 	{ .val = 0, .div = 2 },
289 	{ .val = 1, .div = 2 },
290 	{ .val = 2, .div = 4 },
291 	{ .val = 3, .div = 8 },
292 	{ /* Sentinel */ },
293 };
294 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
295 			   0x054, 8, 2, apb1_div_table, 0);
296 
297 static const char * const apb2_parents[] = { "osc32k", "osc24M",
298 					     "pll-periph0-2x",
299 					     "pll-periph0-2x" };
300 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
301 			     0, 5,	/* M */
302 			     16, 2,	/* P */
303 			     24, 2,	/* mux */
304 			     0);
305 
306 static SUNXI_CCU_GATE(bus_mipi_dsi_clk,	"bus-mipi-dsi",	"ahb1",
307 		      0x060, BIT(1), 0);
308 static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
309 		      0x060, BIT(5), 0);
310 static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
311 		      0x060, BIT(6), 0);
312 static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
313 		      0x060, BIT(8), 0);
314 static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
315 		      0x060, BIT(9), 0);
316 static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
317 		      0x060, BIT(10), 0);
318 static SUNXI_CCU_GATE(bus_mmc3_clk,	"bus-mmc3",	"ahb1",
319 		      0x060, BIT(11), 0);
320 static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
321 		      0x060, BIT(13), 0);
322 static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
323 		      0x060, BIT(14), 0);
324 static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb1",
325 		      0x060, BIT(17), 0);
326 static SUNXI_CCU_GATE(bus_ts_clk,	"bus-ts",	"ahb1",
327 		      0x060, BIT(18), 0);
328 static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
329 		      0x060, BIT(19), 0);
330 static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
331 		      0x060, BIT(20), 0);
332 static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
333 		      0x060, BIT(21), 0);
334 static SUNXI_CCU_GATE(bus_spi2_clk,	"bus-spi2",	"ahb1",
335 		      0x060, BIT(22), 0);
336 static SUNXI_CCU_GATE(bus_spi3_clk,	"bus-spi3",	"ahb1",
337 		      0x060, BIT(23), 0);
338 static SUNXI_CCU_GATE(bus_sata_clk,	"bus-sata",	"ahb1",
339 		      0x060, BIT(24), 0);
340 static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
341 		      0x060, BIT(25), 0);
342 static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
343 		      0x060, BIT(26), 0);
344 static SUNXI_CCU_GATE(bus_ehci1_clk,	"bus-ehci1",	"ahb1",
345 		      0x060, BIT(27), 0);
346 static SUNXI_CCU_GATE(bus_ehci2_clk,	"bus-ehci2",	"ahb1",
347 		      0x060, BIT(28), 0);
348 static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
349 		      0x060, BIT(29), 0);
350 static SUNXI_CCU_GATE(bus_ohci1_clk,	"bus-ohci1",	"ahb1",
351 		      0x060, BIT(30), 0);
352 static SUNXI_CCU_GATE(bus_ohci2_clk,	"bus-ohci2",	"ahb1",
353 		      0x060, BIT(31), 0);
354 
355 static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
356 		      0x064, BIT(0), 0);
357 static SUNXI_CCU_GATE(bus_mp_clk,	"bus-mp",	"ahb1",
358 		      0x064, BIT(2), 0);
359 static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb1",
360 		      0x064, BIT(5), 0);
361 static SUNXI_CCU_GATE(bus_csi0_clk,	"bus-csi0",	"ahb1",
362 		      0x064, BIT(8), 0);
363 static SUNXI_CCU_GATE(bus_csi1_clk,	"bus-csi1",	"ahb1",
364 		      0x064, BIT(9), 0);
365 static SUNXI_CCU_GATE(bus_hdmi0_clk,	"bus-hdmi0",	"ahb1",
366 		      0x064, BIT(10), 0);
367 static SUNXI_CCU_GATE(bus_hdmi1_clk,	"bus-hdmi1",	"ahb1",
368 		      0x064, BIT(11), 0);
369 static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
370 		      0x064, BIT(12), 0);
371 static SUNXI_CCU_GATE(bus_tve0_clk,	"bus-tve0",	"ahb1",
372 		      0x064, BIT(13), 0);
373 static SUNXI_CCU_GATE(bus_tve1_clk,	"bus-tve1",	"ahb1",
374 		      0x064, BIT(14), 0);
375 static SUNXI_CCU_GATE(bus_tve_top_clk,	"bus-tve-top",	"ahb1",
376 		      0x064, BIT(15), 0);
377 static SUNXI_CCU_GATE(bus_gmac_clk,	"bus-gmac",	"ahb1",
378 		      0x064, BIT(17), 0);
379 static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
380 		      0x064, BIT(20), 0);
381 static SUNXI_CCU_GATE(bus_tvd0_clk,	"bus-tvd0",	"ahb1",
382 		      0x064, BIT(21), 0);
383 static SUNXI_CCU_GATE(bus_tvd1_clk,	"bus-tvd1",	"ahb1",
384 		      0x064, BIT(22), 0);
385 static SUNXI_CCU_GATE(bus_tvd2_clk,	"bus-tvd2",	"ahb1",
386 		      0x064, BIT(23), 0);
387 static SUNXI_CCU_GATE(bus_tvd3_clk,	"bus-tvd3",	"ahb1",
388 		      0x064, BIT(24), 0);
389 static SUNXI_CCU_GATE(bus_tvd_top_clk,	"bus-tvd-top",	"ahb1",
390 		      0x064, BIT(25), 0);
391 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk,	"bus-tcon-lcd0",	"ahb1",
392 		      0x064, BIT(26), 0);
393 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk,	"bus-tcon-lcd1",	"ahb1",
394 		      0x064, BIT(27), 0);
395 static SUNXI_CCU_GATE(bus_tcon_tv0_clk,	"bus-tcon-tv0",	"ahb1",
396 		      0x064, BIT(28), 0);
397 static SUNXI_CCU_GATE(bus_tcon_tv1_clk,	"bus-tcon-tv1",	"ahb1",
398 		      0x064, BIT(29), 0);
399 static SUNXI_CCU_GATE(bus_tcon_top_clk,	"bus-tcon-top",	"ahb1",
400 		      0x064, BIT(30), 0);
401 
402 static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
403 		      0x068, BIT(0), 0);
404 static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb1",
405 		      0x068, BIT(1), 0);
406 static SUNXI_CCU_GATE(bus_ac97_clk,	"bus-ac97",	"apb1",
407 		      0x068, BIT(2), 0);
408 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
409 		      0x068, BIT(5), 0);
410 static SUNXI_CCU_GATE(bus_ir0_clk,	"bus-ir0",	"apb1",
411 		      0x068, BIT(6), 0);
412 static SUNXI_CCU_GATE(bus_ir1_clk,	"bus-ir1",	"apb1",
413 		      0x068, BIT(7), 0);
414 static SUNXI_CCU_GATE(bus_ths_clk,	"bus-ths",	"apb1",
415 		      0x068, BIT(8), 0);
416 static SUNXI_CCU_GATE(bus_keypad_clk,	"bus-keypad",	"apb1",
417 		      0x068, BIT(10), 0);
418 static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
419 		      0x068, BIT(12), 0);
420 static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
421 		      0x068, BIT(13), 0);
422 static SUNXI_CCU_GATE(bus_i2s2_clk,	"bus-i2s2",	"apb1",
423 		      0x068, BIT(14), 0);
424 
425 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
426 		      0x06c, BIT(0), 0);
427 static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
428 		      0x06c, BIT(1), 0);
429 static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
430 		      0x06c, BIT(2), 0);
431 static SUNXI_CCU_GATE(bus_i2c3_clk,	"bus-i2c3",	"apb2",
432 		      0x06c, BIT(3), 0);
433 /*
434  * In datasheet here's "Reserved", however the gate exists in BSP soucre
435  * code.
436  */
437 static SUNXI_CCU_GATE(bus_can_clk,	"bus-can",	"apb2",
438 		      0x06c, BIT(4), 0);
439 static SUNXI_CCU_GATE(bus_scr_clk,	"bus-scr",	"apb2",
440 		      0x06c, BIT(5), 0);
441 static SUNXI_CCU_GATE(bus_ps20_clk,	"bus-ps20",	"apb2",
442 		      0x06c, BIT(6), 0);
443 static SUNXI_CCU_GATE(bus_ps21_clk,	"bus-ps21",	"apb2",
444 		      0x06c, BIT(7), 0);
445 static SUNXI_CCU_GATE(bus_i2c4_clk,	"bus-i2c4",	"apb2",
446 		      0x06c, BIT(15), 0);
447 static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
448 		      0x06c, BIT(16), 0);
449 static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
450 		      0x06c, BIT(17), 0);
451 static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
452 		      0x06c, BIT(18), 0);
453 static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
454 		      0x06c, BIT(19), 0);
455 static SUNXI_CCU_GATE(bus_uart4_clk,	"bus-uart4",	"apb2",
456 		      0x06c, BIT(20), 0);
457 static SUNXI_CCU_GATE(bus_uart5_clk,	"bus-uart5",	"apb2",
458 		      0x06c, BIT(21), 0);
459 static SUNXI_CCU_GATE(bus_uart6_clk,	"bus-uart6",	"apb2",
460 		      0x06c, BIT(22), 0);
461 static SUNXI_CCU_GATE(bus_uart7_clk,	"bus-uart7",	"apb2",
462 		      0x06c, BIT(23), 0);
463 
464 static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
465 		      0x070, BIT(7), 0);
466 
467 static const char * const ths_parents[] = { "osc24M" };
468 static struct ccu_div ths_clk = {
469 	.enable	= BIT(31),
470 	.div	= _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
471 	.mux	= _SUNXI_CCU_MUX(24, 2),
472 	.common	= {
473 		.reg		= 0x074,
474 		.hw.init	= CLK_HW_INIT_PARENTS("ths",
475 						      ths_parents,
476 						      &ccu_div_ops,
477 						      0),
478 	},
479 };
480 
481 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
482 						     "pll-periph1" };
483 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
484 				  0, 4,		/* M */
485 				  16, 2,	/* P */
486 				  24, 2,	/* mux */
487 				  BIT(31),	/* gate */
488 				  0);
489 
490 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
491 				  0, 4,		/* M */
492 				  16, 2,	/* P */
493 				  24, 2,	/* mux */
494 				  BIT(31),	/* gate */
495 				  0);
496 
497 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
498 				  0, 4,		/* M */
499 				  16, 2,	/* P */
500 				  24, 2,	/* mux */
501 				  BIT(31),	/* gate */
502 				  0);
503 
504 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
505 				  0, 4,		/* M */
506 				  16, 2,	/* P */
507 				  24, 2,	/* mux */
508 				  BIT(31),	/* gate */
509 				  0);
510 
511 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
512 				  0, 4,		/* M */
513 				  16, 2,	/* P */
514 				  24, 2,	/* mux */
515 				  BIT(31),	/* gate */
516 				  0);
517 
518 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
519 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
520 				  0, 4,		/* M */
521 				  16, 2,	/* P */
522 				  24, 4,	/* mux */
523 				  BIT(31),	/* gate */
524 				  0);
525 
526 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
527 					   "pll-periph1-2x" };
528 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
529 				  0, 4,		/* M */
530 				  16, 2,	/* P */
531 				  24, 2,	/* mux */
532 				  BIT(31),	/* gate */
533 				  0);
534 
535 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
536 				  0, 4,		/* M */
537 				  16, 2,	/* P */
538 				  24, 2,	/* mux */
539 				  BIT(31),	/* gate */
540 				  0);
541 
542 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
543 				  0, 4,		/* M */
544 				  16, 2,	/* P */
545 				  24, 2,	/* mux */
546 				  BIT(31),	/* gate */
547 				  0);
548 
549 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
550 				  0, 4,		/* M */
551 				  16, 2,	/* P */
552 				  24, 2,	/* mux */
553 				  BIT(31),	/* gate */
554 				  0);
555 
556 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
557 				  0, 4,		/* M */
558 				  16, 2,	/* P */
559 				  24, 2,	/* mux */
560 				  BIT(31),	/* gate */
561 				  0);
562 
563 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
564 					    "pll-audio-2x", "pll-audio" };
565 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
566 			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
567 
568 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
569 			       0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
570 
571 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
572 			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
573 
574 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
575 			       0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
576 
577 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
578 			       0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
579 
580 static const char * const keypad_parents[] = { "osc24M", "osc32k" };
581 static const u8 keypad_table[] = { 0, 2 };
582 static struct ccu_mp keypad_clk = {
583 	.enable	= BIT(31),
584 	.m	= _SUNXI_CCU_DIV(0, 5),
585 	.p	= _SUNXI_CCU_DIV(16, 2),
586 	.mux	= _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
587 	.common	= {
588 		.reg		= 0x0c4,
589 		.hw.init	= CLK_HW_INIT_PARENTS("keypad",
590 						      keypad_parents,
591 						      &ccu_mp_ops,
592 						      0),
593 	}
594 };
595 
596 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
597 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
598 			       0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
599 
600 /*
601  * There are 3 OHCI 12M clock source selection bits in this register.
602  * We will force them to 0 (12M divided from 48M).
603  */
604 #define SUN8I_R40_USB_CLK_REG	0x0cc
605 
606 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
607 		      0x0cc, BIT(8), 0);
608 static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
609 		      0x0cc, BIT(9), 0);
610 static SUNXI_CCU_GATE(usb_phy2_clk,	"usb-phy2",	"osc24M",
611 		      0x0cc, BIT(10), 0);
612 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc12M",
613 		      0x0cc, BIT(16), 0);
614 static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"osc12M",
615 		      0x0cc, BIT(17), 0);
616 static SUNXI_CCU_GATE(usb_ohci2_clk,	"usb-ohci2",	"osc12M",
617 		      0x0cc, BIT(18), 0);
618 
619 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
620 					   "pll-periph1", "osc32k" };
621 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
622 				  0, 4,		/* M */
623 				  16, 2,	/* P */
624 				  24, 2,	/* mux */
625 				  BIT(31),	/* gate */
626 				  0);
627 
628 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
629 				  0, 4,		/* M */
630 				  16, 2,	/* P */
631 				  24, 2,	/* mux */
632 				  BIT(31),	/* gate */
633 				  0);
634 
635 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
636 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
637 			    0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
638 
639 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
640 		      0x100, BIT(0), 0);
641 static SUNXI_CCU_GATE(dram_csi0_clk,	"dram-csi0",	"dram",
642 		      0x100, BIT(1), 0);
643 static SUNXI_CCU_GATE(dram_csi1_clk,	"dram-csi1",	"dram",
644 		      0x100, BIT(2), 0);
645 static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
646 		      0x100, BIT(3), 0);
647 static SUNXI_CCU_GATE(dram_tvd_clk,	"dram-tvd",	"dram",
648 		      0x100, BIT(4), 0);
649 static SUNXI_CCU_GATE(dram_mp_clk,	"dram-mp",	"dram",
650 		      0x100, BIT(5), 0);
651 static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",	"dram",
652 		      0x100, BIT(6), 0);
653 
654 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
655 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
656 				 0x104, 0, 4, 24, 3, BIT(31), 0);
657 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
658 				 0x108, 0, 4, 24, 3, BIT(31), 0);
659 
660 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
661 					     "pll-video0-2x", "pll-video1-2x",
662 					     "pll-mipi" };
663 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
664 			       0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
665 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
666 			       0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
667 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
668 				 0x118, 0, 4, 24, 3, BIT(31), 0);
669 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
670 				 0x11c, 0, 4, 24, 3, BIT(31), 0);
671 
672 static const char * const deinterlace_parents[] = { "pll-periph0",
673 						    "pll-periph1" };
674 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
675 				 deinterlace_parents, 0x124, 0, 4, 24, 3,
676 				 BIT(31), 0);
677 
678 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
679 						 "pll-periph1" };
680 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
681 				 0x130, 0, 5, 8, 3, BIT(15), 0);
682 
683 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
684 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
685 				 0x134, 16, 4, 24, 3, BIT(31), 0);
686 
687 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
688 				 0x134, 0, 5, 8, 3, BIT(15), 0);
689 
690 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
691 			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
692 
693 static SUNXI_CCU_GATE(codec_clk,	"codec",	"pll-audio",
694 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
695 static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
696 		      0x144, BIT(31), 0);
697 
698 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
699 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
700 				 0x150, 0, 4, 24, 2, BIT(31), 0);
701 
702 static SUNXI_CCU_GATE(hdmi_slow_clk,	"hdmi-slow",	"osc24M",
703 		      0x154, BIT(31), 0);
704 
705 /*
706  * In the SoC's user manual, the P factor is mentioned, but not used in
707  * the frequency formula.
708  *
709  * Here the factor is included, according to the BSP kernel source,
710  * which contains the P factor of this clock.
711  */
712 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
713 					     "pll-ddr0" };
714 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
715 				  0, 4,		/* M */
716 				  16, 2,	/* P */
717 				  24, 2,	/* mux */
718 				  BIT(31),	/* gate */
719 				  CLK_IS_CRITICAL);
720 
721 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
722 						 "pll-periph0" };
723 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
724 				 0x168, 0, 4, 8, 2, BIT(15), 0);
725 
726 static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
727 				 0x180, 0, 4, 24, 3, BIT(31), 0);
728 static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
729 				 0x184, 0, 4, 24, 3, BIT(31), 0);
730 
731 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
732 					    "pll-video0-2x", "pll-video1-2x" };
733 static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
734 				 0x188, 0, 4, 24, 3, BIT(31), 0);
735 static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
736 				 0x18c, 0, 4, 24, 3, BIT(31), 0);
737 static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
738 				 0x190, 0, 4, 24, 3, BIT(31), 0);
739 static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
740 				 0x194, 0, 4, 24, 3, BIT(31), 0);
741 
742 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
743 			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
744 
745 static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
746 static const struct ccu_mux_fixed_prediv out_predivs[] = {
747 	{ .index = 0, .div = 750, },
748 };
749 
750 static struct ccu_mp outa_clk = {
751 	.enable	= BIT(31),
752 	.m	= _SUNXI_CCU_DIV(8, 5),
753 	.p	= _SUNXI_CCU_DIV(20, 2),
754 	.mux	= {
755 		.shift		= 24,
756 		.width		= 2,
757 		.fixed_predivs	= out_predivs,
758 		.n_predivs	= ARRAY_SIZE(out_predivs),
759 	},
760 	.common	= {
761 		.reg		= 0x1f0,
762 		.features	= CCU_FEATURE_FIXED_PREDIV,
763 		.hw.init	= CLK_HW_INIT_PARENTS("outa", out_parents,
764 						      &ccu_mp_ops, 0),
765 	}
766 };
767 
768 static struct ccu_mp outb_clk = {
769 	.enable	= BIT(31),
770 	.m	= _SUNXI_CCU_DIV(8, 5),
771 	.p	= _SUNXI_CCU_DIV(20, 2),
772 	.mux	= {
773 		.shift		= 24,
774 		.width		= 2,
775 		.fixed_predivs	= out_predivs,
776 		.n_predivs	= ARRAY_SIZE(out_predivs),
777 	},
778 	.common	= {
779 		.reg		= 0x1f4,
780 		.features	= CCU_FEATURE_FIXED_PREDIV,
781 		.hw.init	= CLK_HW_INIT_PARENTS("outb", out_parents,
782 						      &ccu_mp_ops, 0),
783 	}
784 };
785 
786 static struct ccu_common *sun8i_r40_ccu_clks[] = {
787 	&pll_cpu_clk.common,
788 	&pll_audio_base_clk.common,
789 	&pll_video0_clk.common,
790 	&pll_ve_clk.common,
791 	&pll_ddr0_clk.common,
792 	&pll_periph0_clk.common,
793 	&pll_periph0_sata_clk.common,
794 	&pll_periph1_clk.common,
795 	&pll_video1_clk.common,
796 	&pll_sata_clk.common,
797 	&pll_sata_out_clk.common,
798 	&pll_gpu_clk.common,
799 	&pll_mipi_clk.common,
800 	&pll_de_clk.common,
801 	&pll_ddr1_clk.common,
802 	&cpu_clk.common,
803 	&axi_clk.common,
804 	&ahb1_clk.common,
805 	&apb1_clk.common,
806 	&apb2_clk.common,
807 	&bus_mipi_dsi_clk.common,
808 	&bus_ce_clk.common,
809 	&bus_dma_clk.common,
810 	&bus_mmc0_clk.common,
811 	&bus_mmc1_clk.common,
812 	&bus_mmc2_clk.common,
813 	&bus_mmc3_clk.common,
814 	&bus_nand_clk.common,
815 	&bus_dram_clk.common,
816 	&bus_emac_clk.common,
817 	&bus_ts_clk.common,
818 	&bus_hstimer_clk.common,
819 	&bus_spi0_clk.common,
820 	&bus_spi1_clk.common,
821 	&bus_spi2_clk.common,
822 	&bus_spi3_clk.common,
823 	&bus_sata_clk.common,
824 	&bus_otg_clk.common,
825 	&bus_ehci0_clk.common,
826 	&bus_ehci1_clk.common,
827 	&bus_ehci2_clk.common,
828 	&bus_ohci0_clk.common,
829 	&bus_ohci1_clk.common,
830 	&bus_ohci2_clk.common,
831 	&bus_ve_clk.common,
832 	&bus_mp_clk.common,
833 	&bus_deinterlace_clk.common,
834 	&bus_csi0_clk.common,
835 	&bus_csi1_clk.common,
836 	&bus_hdmi0_clk.common,
837 	&bus_hdmi1_clk.common,
838 	&bus_de_clk.common,
839 	&bus_tve0_clk.common,
840 	&bus_tve1_clk.common,
841 	&bus_tve_top_clk.common,
842 	&bus_gmac_clk.common,
843 	&bus_gpu_clk.common,
844 	&bus_tvd0_clk.common,
845 	&bus_tvd1_clk.common,
846 	&bus_tvd2_clk.common,
847 	&bus_tvd3_clk.common,
848 	&bus_tvd_top_clk.common,
849 	&bus_tcon_lcd0_clk.common,
850 	&bus_tcon_lcd1_clk.common,
851 	&bus_tcon_tv0_clk.common,
852 	&bus_tcon_tv1_clk.common,
853 	&bus_tcon_top_clk.common,
854 	&bus_codec_clk.common,
855 	&bus_spdif_clk.common,
856 	&bus_ac97_clk.common,
857 	&bus_pio_clk.common,
858 	&bus_ir0_clk.common,
859 	&bus_ir1_clk.common,
860 	&bus_ths_clk.common,
861 	&bus_keypad_clk.common,
862 	&bus_i2s0_clk.common,
863 	&bus_i2s1_clk.common,
864 	&bus_i2s2_clk.common,
865 	&bus_i2c0_clk.common,
866 	&bus_i2c1_clk.common,
867 	&bus_i2c2_clk.common,
868 	&bus_i2c3_clk.common,
869 	&bus_can_clk.common,
870 	&bus_scr_clk.common,
871 	&bus_ps20_clk.common,
872 	&bus_ps21_clk.common,
873 	&bus_i2c4_clk.common,
874 	&bus_uart0_clk.common,
875 	&bus_uart1_clk.common,
876 	&bus_uart2_clk.common,
877 	&bus_uart3_clk.common,
878 	&bus_uart4_clk.common,
879 	&bus_uart5_clk.common,
880 	&bus_uart6_clk.common,
881 	&bus_uart7_clk.common,
882 	&bus_dbg_clk.common,
883 	&ths_clk.common,
884 	&nand_clk.common,
885 	&mmc0_clk.common,
886 	&mmc1_clk.common,
887 	&mmc2_clk.common,
888 	&mmc3_clk.common,
889 	&ts_clk.common,
890 	&ce_clk.common,
891 	&spi0_clk.common,
892 	&spi1_clk.common,
893 	&spi2_clk.common,
894 	&spi3_clk.common,
895 	&i2s0_clk.common,
896 	&i2s1_clk.common,
897 	&i2s2_clk.common,
898 	&ac97_clk.common,
899 	&spdif_clk.common,
900 	&keypad_clk.common,
901 	&sata_clk.common,
902 	&usb_phy0_clk.common,
903 	&usb_phy1_clk.common,
904 	&usb_phy2_clk.common,
905 	&usb_ohci0_clk.common,
906 	&usb_ohci1_clk.common,
907 	&usb_ohci2_clk.common,
908 	&ir0_clk.common,
909 	&ir1_clk.common,
910 	&dram_clk.common,
911 	&dram_ve_clk.common,
912 	&dram_csi0_clk.common,
913 	&dram_csi1_clk.common,
914 	&dram_ts_clk.common,
915 	&dram_tvd_clk.common,
916 	&dram_mp_clk.common,
917 	&dram_deinterlace_clk.common,
918 	&de_clk.common,
919 	&mp_clk.common,
920 	&tcon_lcd0_clk.common,
921 	&tcon_lcd1_clk.common,
922 	&tcon_tv0_clk.common,
923 	&tcon_tv1_clk.common,
924 	&deinterlace_clk.common,
925 	&csi1_mclk_clk.common,
926 	&csi_sclk_clk.common,
927 	&csi0_mclk_clk.common,
928 	&ve_clk.common,
929 	&codec_clk.common,
930 	&avs_clk.common,
931 	&hdmi_clk.common,
932 	&hdmi_slow_clk.common,
933 	&mbus_clk.common,
934 	&dsi_dphy_clk.common,
935 	&tve0_clk.common,
936 	&tve1_clk.common,
937 	&tvd0_clk.common,
938 	&tvd1_clk.common,
939 	&tvd2_clk.common,
940 	&tvd3_clk.common,
941 	&gpu_clk.common,
942 	&outa_clk.common,
943 	&outb_clk.common,
944 };
945 
946 /* Fixed Factor clocks */
947 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
948 
949 /* We hardcode the divider to 4 for now */
950 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
951 			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
952 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
953 			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
954 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
955 			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
956 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
957 			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
958 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
959 			"pll-periph0", 1, 2, 0);
960 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
961 			"pll-periph1", 1, 2, 0);
962 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
963 			"pll-video0", 1, 2, 0);
964 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
965 			"pll-video1", 1, 2, 0);
966 
967 static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
968 	.hws	= {
969 		[CLK_OSC_12M]		= &osc12M_clk.hw,
970 		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
971 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
972 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
973 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
974 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
975 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
976 		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
977 		[CLK_PLL_VIDEO0_2X]	= &pll_video0_2x_clk.hw,
978 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
979 		[CLK_PLL_DDR0]		= &pll_ddr0_clk.common.hw,
980 		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
981 		[CLK_PLL_PERIPH0_SATA]	= &pll_periph0_sata_clk.common.hw,
982 		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
983 		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
984 		[CLK_PLL_PERIPH1_2X]	= &pll_periph1_2x_clk.hw,
985 		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
986 		[CLK_PLL_VIDEO1_2X]	= &pll_video1_2x_clk.hw,
987 		[CLK_PLL_SATA]		= &pll_sata_clk.common.hw,
988 		[CLK_PLL_SATA_OUT]	= &pll_sata_out_clk.common.hw,
989 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
990 		[CLK_PLL_MIPI]		= &pll_mipi_clk.common.hw,
991 		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
992 		[CLK_PLL_DDR1]		= &pll_ddr1_clk.common.hw,
993 		[CLK_CPU]		= &cpu_clk.common.hw,
994 		[CLK_AXI]		= &axi_clk.common.hw,
995 		[CLK_AHB1]		= &ahb1_clk.common.hw,
996 		[CLK_APB1]		= &apb1_clk.common.hw,
997 		[CLK_APB2]		= &apb2_clk.common.hw,
998 		[CLK_BUS_MIPI_DSI]	= &bus_mipi_dsi_clk.common.hw,
999 		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
1000 		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
1001 		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
1002 		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
1003 		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
1004 		[CLK_BUS_MMC3]		= &bus_mmc3_clk.common.hw,
1005 		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
1006 		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
1007 		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
1008 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
1009 		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
1010 		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
1011 		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
1012 		[CLK_BUS_SPI2]		= &bus_spi2_clk.common.hw,
1013 		[CLK_BUS_SPI3]		= &bus_spi3_clk.common.hw,
1014 		[CLK_BUS_SATA]		= &bus_sata_clk.common.hw,
1015 		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
1016 		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
1017 		[CLK_BUS_EHCI1]		= &bus_ehci1_clk.common.hw,
1018 		[CLK_BUS_EHCI2]		= &bus_ehci2_clk.common.hw,
1019 		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
1020 		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
1021 		[CLK_BUS_OHCI2]		= &bus_ohci2_clk.common.hw,
1022 		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
1023 		[CLK_BUS_MP]		= &bus_mp_clk.common.hw,
1024 		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
1025 		[CLK_BUS_CSI0]		= &bus_csi0_clk.common.hw,
1026 		[CLK_BUS_CSI1]		= &bus_csi1_clk.common.hw,
1027 		[CLK_BUS_HDMI0]		= &bus_hdmi0_clk.common.hw,
1028 		[CLK_BUS_HDMI1]		= &bus_hdmi1_clk.common.hw,
1029 		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
1030 		[CLK_BUS_TVE0]		= &bus_tve0_clk.common.hw,
1031 		[CLK_BUS_TVE1]		= &bus_tve1_clk.common.hw,
1032 		[CLK_BUS_TVE_TOP]	= &bus_tve_top_clk.common.hw,
1033 		[CLK_BUS_GMAC]		= &bus_gmac_clk.common.hw,
1034 		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
1035 		[CLK_BUS_TVD0]		= &bus_tvd0_clk.common.hw,
1036 		[CLK_BUS_TVD1]		= &bus_tvd1_clk.common.hw,
1037 		[CLK_BUS_TVD2]		= &bus_tvd2_clk.common.hw,
1038 		[CLK_BUS_TVD3]		= &bus_tvd3_clk.common.hw,
1039 		[CLK_BUS_TVD_TOP]	= &bus_tvd_top_clk.common.hw,
1040 		[CLK_BUS_TCON_LCD0]	= &bus_tcon_lcd0_clk.common.hw,
1041 		[CLK_BUS_TCON_LCD1]	= &bus_tcon_lcd1_clk.common.hw,
1042 		[CLK_BUS_TCON_TV0]	= &bus_tcon_tv0_clk.common.hw,
1043 		[CLK_BUS_TCON_TV1]	= &bus_tcon_tv1_clk.common.hw,
1044 		[CLK_BUS_TCON_TOP]	= &bus_tcon_top_clk.common.hw,
1045 		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
1046 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
1047 		[CLK_BUS_AC97]		= &bus_ac97_clk.common.hw,
1048 		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
1049 		[CLK_BUS_IR0]		= &bus_ir0_clk.common.hw,
1050 		[CLK_BUS_IR1]		= &bus_ir1_clk.common.hw,
1051 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
1052 		[CLK_BUS_KEYPAD]	= &bus_keypad_clk.common.hw,
1053 		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
1054 		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
1055 		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
1056 		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
1057 		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
1058 		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
1059 		[CLK_BUS_I2C3]		= &bus_i2c3_clk.common.hw,
1060 		[CLK_BUS_CAN]		= &bus_can_clk.common.hw,
1061 		[CLK_BUS_SCR]		= &bus_scr_clk.common.hw,
1062 		[CLK_BUS_PS20]		= &bus_ps20_clk.common.hw,
1063 		[CLK_BUS_PS21]		= &bus_ps21_clk.common.hw,
1064 		[CLK_BUS_I2C4]		= &bus_i2c4_clk.common.hw,
1065 		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
1066 		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
1067 		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
1068 		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
1069 		[CLK_BUS_UART4]		= &bus_uart4_clk.common.hw,
1070 		[CLK_BUS_UART5]		= &bus_uart5_clk.common.hw,
1071 		[CLK_BUS_UART6]		= &bus_uart6_clk.common.hw,
1072 		[CLK_BUS_UART7]		= &bus_uart7_clk.common.hw,
1073 		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
1074 		[CLK_THS]		= &ths_clk.common.hw,
1075 		[CLK_NAND]		= &nand_clk.common.hw,
1076 		[CLK_MMC0]		= &mmc0_clk.common.hw,
1077 		[CLK_MMC1]		= &mmc1_clk.common.hw,
1078 		[CLK_MMC2]		= &mmc2_clk.common.hw,
1079 		[CLK_MMC3]		= &mmc3_clk.common.hw,
1080 		[CLK_TS]		= &ts_clk.common.hw,
1081 		[CLK_CE]		= &ce_clk.common.hw,
1082 		[CLK_SPI0]		= &spi0_clk.common.hw,
1083 		[CLK_SPI1]		= &spi1_clk.common.hw,
1084 		[CLK_SPI2]		= &spi2_clk.common.hw,
1085 		[CLK_SPI3]		= &spi3_clk.common.hw,
1086 		[CLK_I2S0]		= &i2s0_clk.common.hw,
1087 		[CLK_I2S1]		= &i2s1_clk.common.hw,
1088 		[CLK_I2S2]		= &i2s2_clk.common.hw,
1089 		[CLK_AC97]		= &ac97_clk.common.hw,
1090 		[CLK_SPDIF]		= &spdif_clk.common.hw,
1091 		[CLK_KEYPAD]		= &keypad_clk.common.hw,
1092 		[CLK_SATA]		= &sata_clk.common.hw,
1093 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
1094 		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
1095 		[CLK_USB_PHY2]		= &usb_phy2_clk.common.hw,
1096 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
1097 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
1098 		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,
1099 		[CLK_IR0]		= &ir0_clk.common.hw,
1100 		[CLK_IR1]		= &ir1_clk.common.hw,
1101 		[CLK_DRAM]		= &dram_clk.common.hw,
1102 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
1103 		[CLK_DRAM_CSI0]		= &dram_csi0_clk.common.hw,
1104 		[CLK_DRAM_CSI1]		= &dram_csi1_clk.common.hw,
1105 		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
1106 		[CLK_DRAM_TVD]		= &dram_tvd_clk.common.hw,
1107 		[CLK_DRAM_MP]		= &dram_mp_clk.common.hw,
1108 		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
1109 		[CLK_DE]		= &de_clk.common.hw,
1110 		[CLK_MP]		= &mp_clk.common.hw,
1111 		[CLK_TCON_LCD0]		= &tcon_lcd0_clk.common.hw,
1112 		[CLK_TCON_LCD1]		= &tcon_lcd1_clk.common.hw,
1113 		[CLK_TCON_TV0]		= &tcon_tv0_clk.common.hw,
1114 		[CLK_TCON_TV1]		= &tcon_tv1_clk.common.hw,
1115 		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
1116 		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,
1117 		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
1118 		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,
1119 		[CLK_VE]		= &ve_clk.common.hw,
1120 		[CLK_CODEC]		= &codec_clk.common.hw,
1121 		[CLK_AVS]		= &avs_clk.common.hw,
1122 		[CLK_HDMI]		= &hdmi_clk.common.hw,
1123 		[CLK_HDMI_SLOW]		= &hdmi_slow_clk.common.hw,
1124 		[CLK_MBUS]		= &mbus_clk.common.hw,
1125 		[CLK_DSI_DPHY]		= &dsi_dphy_clk.common.hw,
1126 		[CLK_TVE0]		= &tve0_clk.common.hw,
1127 		[CLK_TVE1]		= &tve1_clk.common.hw,
1128 		[CLK_TVD0]		= &tvd0_clk.common.hw,
1129 		[CLK_TVD1]		= &tvd1_clk.common.hw,
1130 		[CLK_TVD2]		= &tvd2_clk.common.hw,
1131 		[CLK_TVD3]		= &tvd3_clk.common.hw,
1132 		[CLK_GPU]		= &gpu_clk.common.hw,
1133 		[CLK_OUTA]		= &outa_clk.common.hw,
1134 		[CLK_OUTB]		= &outb_clk.common.hw,
1135 	},
1136 	.num	= CLK_NUMBER,
1137 };
1138 
1139 static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
1140 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
1141 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
1142 	[RST_USB_PHY2]		=  { 0x0cc, BIT(2) },
1143 
1144 	[RST_DRAM]		=  { 0x0f4, BIT(31) },
1145 	[RST_MBUS]		=  { 0x0fc, BIT(31) },
1146 
1147 	[RST_BUS_MIPI_DSI]	=  { 0x2c0, BIT(1) },
1148 	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
1149 	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
1150 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
1151 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
1152 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
1153 	[RST_BUS_MMC3]		=  { 0x2c0, BIT(11) },
1154 	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
1155 	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
1156 	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
1157 	[RST_BUS_TS]		=  { 0x2c0, BIT(18) },
1158 	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
1159 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
1160 	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
1161 	[RST_BUS_SPI2]		=  { 0x2c0, BIT(22) },
1162 	[RST_BUS_SPI3]		=  { 0x2c0, BIT(23) },
1163 	[RST_BUS_SATA]		=  { 0x2c0, BIT(24) },
1164 	[RST_BUS_OTG]		=  { 0x2c0, BIT(25) },
1165 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(26) },
1166 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(27) },
1167 	[RST_BUS_EHCI2]		=  { 0x2c0, BIT(28) },
1168 	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(29) },
1169 	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(30) },
1170 	[RST_BUS_OHCI2]		=  { 0x2c0, BIT(31) },
1171 
1172 	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
1173 	[RST_BUS_MP]		=  { 0x2c4, BIT(2) },
1174 	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
1175 	[RST_BUS_CSI0]		=  { 0x2c4, BIT(8) },
1176 	[RST_BUS_CSI1]		=  { 0x2c4, BIT(9) },
1177 	[RST_BUS_HDMI0]		=  { 0x2c4, BIT(10) },
1178 	[RST_BUS_HDMI1]		=  { 0x2c4, BIT(11) },
1179 	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
1180 	[RST_BUS_TVE0]		=  { 0x2c4, BIT(13) },
1181 	[RST_BUS_TVE1]		=  { 0x2c4, BIT(14) },
1182 	[RST_BUS_TVE_TOP]	=  { 0x2c4, BIT(15) },
1183 	[RST_BUS_GMAC]		=  { 0x2c4, BIT(17) },
1184 	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
1185 	[RST_BUS_TVD0]		=  { 0x2c4, BIT(21) },
1186 	[RST_BUS_TVD1]		=  { 0x2c4, BIT(22) },
1187 	[RST_BUS_TVD2]		=  { 0x2c4, BIT(23) },
1188 	[RST_BUS_TVD3]		=  { 0x2c4, BIT(24) },
1189 	[RST_BUS_TVD_TOP]	=  { 0x2c4, BIT(25) },
1190 	[RST_BUS_TCON_LCD0]	=  { 0x2c4, BIT(26) },
1191 	[RST_BUS_TCON_LCD1]	=  { 0x2c4, BIT(27) },
1192 	[RST_BUS_TCON_TV0]	=  { 0x2c4, BIT(28) },
1193 	[RST_BUS_TCON_TV1]	=  { 0x2c4, BIT(29) },
1194 	[RST_BUS_TCON_TOP]	=  { 0x2c4, BIT(30) },
1195 	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
1196 
1197 	[RST_BUS_LVDS]		=  { 0x2c8, BIT(0) },
1198 
1199 	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
1200 	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
1201 	[RST_BUS_AC97]		=  { 0x2d0, BIT(2) },
1202 	[RST_BUS_IR0]		=  { 0x2d0, BIT(6) },
1203 	[RST_BUS_IR1]		=  { 0x2d0, BIT(7) },
1204 	[RST_BUS_THS]		=  { 0x2d0, BIT(8) },
1205 	[RST_BUS_KEYPAD]	=  { 0x2d0, BIT(10) },
1206 	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
1207 	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
1208 	[RST_BUS_I2S2]		=  { 0x2d0, BIT(14) },
1209 
1210 	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
1211 	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
1212 	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
1213 	[RST_BUS_I2C3]		=  { 0x2d8, BIT(3) },
1214 	[RST_BUS_CAN]		=  { 0x2d8, BIT(4) },
1215 	[RST_BUS_SCR]		=  { 0x2d8, BIT(5) },
1216 	[RST_BUS_PS20]		=  { 0x2d8, BIT(6) },
1217 	[RST_BUS_PS21]		=  { 0x2d8, BIT(7) },
1218 	[RST_BUS_I2C4]		=  { 0x2d8, BIT(15) },
1219 	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
1220 	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
1221 	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
1222 	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
1223 	[RST_BUS_UART4]		=  { 0x2d8, BIT(20) },
1224 	[RST_BUS_UART5]		=  { 0x2d8, BIT(21) },
1225 	[RST_BUS_UART6]		=  { 0x2d8, BIT(22) },
1226 	[RST_BUS_UART7]		=  { 0x2d8, BIT(23) },
1227 };
1228 
1229 static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
1230 	.ccu_clks	= sun8i_r40_ccu_clks,
1231 	.num_ccu_clks	= ARRAY_SIZE(sun8i_r40_ccu_clks),
1232 
1233 	.hw_clks	= &sun8i_r40_hw_clks,
1234 
1235 	.resets		= sun8i_r40_ccu_resets,
1236 	.num_resets	= ARRAY_SIZE(sun8i_r40_ccu_resets),
1237 };
1238 
1239 static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
1240 	.common	= &pll_cpu_clk.common,
1241 	/* copy from pll_cpu_clk */
1242 	.enable	= BIT(31),
1243 	.lock	= BIT(28),
1244 };
1245 
1246 static struct ccu_mux_nb sun8i_r40_cpu_nb = {
1247 	.common		= &cpu_clk.common,
1248 	.cm		= &cpu_clk.mux,
1249 	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
1250 	.bypass_index	= 1, /* index of 24 MHz oscillator */
1251 };
1252 
1253 static void __init sun8i_r40_ccu_setup(struct device_node *node)
1254 {
1255 	void __iomem *reg;
1256 	u32 val;
1257 
1258 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1259 	if (IS_ERR(reg)) {
1260 		pr_err("%s: Could not map the clock registers\n",
1261 		       of_node_full_name(node));
1262 		return;
1263 	}
1264 
1265 	/* Force the PLL-Audio-1x divider to 4 */
1266 	val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
1267 	val &= ~GENMASK(19, 16);
1268 	writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
1269 
1270 	/* Force PLL-MIPI to MIPI mode */
1271 	val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
1272 	val &= ~BIT(16);
1273 	writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
1274 
1275 	/* Force OHCI 12M parent to 12M divided from 48M */
1276 	val = readl(reg + SUN8I_R40_USB_CLK_REG);
1277 	val &= ~GENMASK(25, 20);
1278 	writel(val, reg + SUN8I_R40_USB_CLK_REG);
1279 
1280 	sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc);
1281 
1282 	/* Gate then ungate PLL CPU after any rate changes */
1283 	ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
1284 
1285 	/* Reparent CPU during PLL CPU rate changes */
1286 	ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1287 				  &sun8i_r40_cpu_nb);
1288 }
1289 CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu",
1290 	       sun8i_r40_ccu_setup);
1291