1 /* 2 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 18 #include "ccu_common.h" 19 #include "ccu_reset.h" 20 21 #include "ccu_div.h" 22 #include "ccu_gate.h" 23 #include "ccu_mp.h" 24 #include "ccu_mult.h" 25 #include "ccu_nk.h" 26 #include "ccu_nkm.h" 27 #include "ccu_nkmp.h" 28 #include "ccu_nm.h" 29 #include "ccu_phase.h" 30 31 #include "ccu-sun8i-r40.h" 32 33 /* TODO: The result of N*K is required to be in [10, 88] range. */ 34 static struct ccu_nkmp pll_cpu_clk = { 35 .enable = BIT(31), 36 .lock = BIT(28), 37 .n = _SUNXI_CCU_MULT(8, 5), 38 .k = _SUNXI_CCU_MULT(4, 2), 39 .m = _SUNXI_CCU_DIV(0, 2), 40 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 41 .common = { 42 .reg = 0x000, 43 .hw.init = CLK_HW_INIT("pll-cpu", 44 "osc24M", 45 &ccu_nkmp_ops, 46 CLK_SET_RATE_UNGATE), 47 }, 48 }; 49 50 /* 51 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 52 * the base (2x, 4x and 8x), and one variable divider (the one true 53 * pll audio). 54 * 55 * We don't have any need for the variable divider for now, so we just 56 * hardcode it to match with the clock names 57 */ 58 #define SUN8I_R40_PLL_AUDIO_REG 0x008 59 60 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 61 "osc24M", 0x008, 62 8, 7, /* N */ 63 0, 5, /* M */ 64 BIT(31), /* gate */ 65 BIT(28), /* lock */ 66 CLK_SET_RATE_UNGATE); 67 68 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", 69 "osc24M", 0x0010, 70 192000000, /* Minimum rate */ 71 1008000000, /* Maximum rate */ 72 8, 7, /* N */ 73 0, 4, /* M */ 74 BIT(24), /* frac enable */ 75 BIT(25), /* frac select */ 76 270000000, /* frac rate 0 */ 77 297000000, /* frac rate 1 */ 78 BIT(31), /* gate */ 79 BIT(28), /* lock */ 80 CLK_SET_RATE_UNGATE); 81 82 /* TODO: The result of N/M is required to be in [8, 25] range. */ 83 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 84 "osc24M", 0x0018, 85 8, 7, /* N */ 86 0, 4, /* M */ 87 BIT(24), /* frac enable */ 88 BIT(25), /* frac select */ 89 270000000, /* frac rate 0 */ 90 297000000, /* frac rate 1 */ 91 BIT(31), /* gate */ 92 BIT(28), /* lock */ 93 CLK_SET_RATE_UNGATE); 94 95 /* TODO: The result of N*K is required to be in [10, 77] range. */ 96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 97 "osc24M", 0x020, 98 8, 5, /* N */ 99 4, 2, /* K */ 100 0, 2, /* M */ 101 BIT(31), /* gate */ 102 BIT(28), /* lock */ 103 CLK_SET_RATE_UNGATE); 104 105 /* TODO: The result of N*K is required to be in [21, 58] range. */ 106 static struct ccu_nk pll_periph0_clk = { 107 .enable = BIT(31), 108 .lock = BIT(28), 109 .n = _SUNXI_CCU_MULT(8, 5), 110 .k = _SUNXI_CCU_MULT(4, 2), 111 .fixed_post_div = 2, 112 .common = { 113 .reg = 0x028, 114 .features = CCU_FEATURE_FIXED_POSTDIV, 115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 116 &ccu_nk_ops, 117 CLK_SET_RATE_UNGATE), 118 }, 119 }; 120 121 static struct ccu_div pll_periph0_sata_clk = { 122 .enable = BIT(24), 123 .div = _SUNXI_CCU_DIV(0, 2), 124 /* 125 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula 126 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is 127 * 6/2 = 3. 128 */ 129 .fixed_post_div = 3, 130 .common = { 131 .reg = 0x028, 132 .features = CCU_FEATURE_FIXED_POSTDIV, 133 .hw.init = CLK_HW_INIT("pll-periph0-sata", 134 "pll-periph0", 135 &ccu_div_ops, 0), 136 }, 137 }; 138 139 /* TODO: The result of N*K is required to be in [21, 58] range. */ 140 static struct ccu_nk pll_periph1_clk = { 141 .enable = BIT(31), 142 .lock = BIT(28), 143 .n = _SUNXI_CCU_MULT(8, 5), 144 .k = _SUNXI_CCU_MULT(4, 2), 145 .fixed_post_div = 2, 146 .common = { 147 .reg = 0x02c, 148 .features = CCU_FEATURE_FIXED_POSTDIV, 149 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 150 &ccu_nk_ops, 151 CLK_SET_RATE_UNGATE), 152 }, 153 }; 154 155 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", 156 "osc24M", 0x030, 157 192000000, /* Minimum rate */ 158 1008000000, /* Maximum rate */ 159 8, 7, /* N */ 160 0, 4, /* M */ 161 BIT(24), /* frac enable */ 162 BIT(25), /* frac select */ 163 270000000, /* frac rate 0 */ 164 297000000, /* frac rate 1 */ 165 BIT(31), /* gate */ 166 BIT(28), /* lock */ 167 CLK_SET_RATE_UNGATE); 168 169 static struct ccu_nkm pll_sata_clk = { 170 .enable = BIT(31), 171 .lock = BIT(28), 172 .n = _SUNXI_CCU_MULT(8, 5), 173 .k = _SUNXI_CCU_MULT(4, 2), 174 .m = _SUNXI_CCU_DIV(0, 2), 175 .fixed_post_div = 6, 176 .common = { 177 .reg = 0x034, 178 .features = CCU_FEATURE_FIXED_POSTDIV, 179 .hw.init = CLK_HW_INIT("pll-sata", "osc24M", 180 &ccu_nkm_ops, 181 CLK_SET_RATE_UNGATE), 182 }, 183 }; 184 185 static const char * const pll_sata_out_parents[] = { "pll-sata", 186 "pll-periph0-sata" }; 187 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out", 188 pll_sata_out_parents, 0x034, 189 30, 1, /* mux */ 190 BIT(14), /* gate */ 191 CLK_SET_RATE_PARENT); 192 193 /* TODO: The result of N/M is required to be in [8, 25] range. */ 194 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 195 "osc24M", 0x038, 196 8, 7, /* N */ 197 0, 4, /* M */ 198 BIT(24), /* frac enable */ 199 BIT(25), /* frac select */ 200 270000000, /* frac rate 0 */ 201 297000000, /* frac rate 1 */ 202 BIT(31), /* gate */ 203 BIT(28), /* lock */ 204 CLK_SET_RATE_UNGATE); 205 206 /* 207 * The MIPI PLL has 2 modes: "MIPI" and "HDMI". 208 * 209 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an 210 * integer / fractional clock with switchable multipliers and dividers. 211 * This is not supported here. We hardcode the PLL to MIPI mode. 212 * 213 * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3, 214 * which cannot be implemented now. 215 */ 216 #define SUN8I_R40_PLL_MIPI_REG 0x040 217 218 static const char * const pll_mipi_parents[] = { "pll-video0" }; 219 static struct ccu_nkm pll_mipi_clk = { 220 .enable = BIT(31) | BIT(23) | BIT(22), 221 .lock = BIT(28), 222 .n = _SUNXI_CCU_MULT(8, 4), 223 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 224 .m = _SUNXI_CCU_DIV(0, 4), 225 .mux = _SUNXI_CCU_MUX(21, 1), 226 .common = { 227 .reg = 0x040, 228 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi", 229 pll_mipi_parents, 230 &ccu_nkm_ops, 231 CLK_SET_RATE_UNGATE) 232 }, 233 }; 234 235 /* TODO: The result of N/M is required to be in [8, 25] range. */ 236 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 237 "osc24M", 0x048, 238 8, 7, /* N */ 239 0, 4, /* M */ 240 BIT(24), /* frac enable */ 241 BIT(25), /* frac select */ 242 270000000, /* frac rate 0 */ 243 297000000, /* frac rate 1 */ 244 BIT(31), /* gate */ 245 BIT(28), /* lock */ 246 CLK_SET_RATE_UNGATE); 247 248 /* TODO: The N factor is required to be in [16, 75] range. */ 249 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 250 "osc24M", 0x04c, 251 8, 7, /* N */ 252 0, 2, /* M */ 253 BIT(31), /* gate */ 254 BIT(28), /* lock */ 255 CLK_SET_RATE_UNGATE); 256 257 static const char * const cpu_parents[] = { "osc32k", "osc24M", 258 "pll-cpu", "pll-cpu" }; 259 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 260 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); 261 262 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0); 263 264 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 265 "axi", "pll-periph0" }; 266 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 267 { .index = 3, .shift = 6, .width = 2 }, 268 }; 269 static struct ccu_div ahb1_clk = { 270 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 271 272 .mux = { 273 .shift = 12, 274 .width = 2, 275 276 .var_predivs = ahb1_predivs, 277 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 278 }, 279 280 .common = { 281 .reg = 0x054, 282 .features = CCU_FEATURE_VARIABLE_PREDIV, 283 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 284 ahb1_parents, 285 &ccu_div_ops, 286 0), 287 }, 288 }; 289 290 static struct clk_div_table apb1_div_table[] = { 291 { .val = 0, .div = 2 }, 292 { .val = 1, .div = 2 }, 293 { .val = 2, .div = 4 }, 294 { .val = 3, .div = 8 }, 295 { /* Sentinel */ }, 296 }; 297 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 298 0x054, 8, 2, apb1_div_table, 0); 299 300 static const char * const apb2_parents[] = { "osc32k", "osc24M", 301 "pll-periph0-2x", 302 "pll-periph0-2x" }; 303 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 304 0, 5, /* M */ 305 16, 2, /* P */ 306 24, 2, /* mux */ 307 0); 308 309 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 310 0x060, BIT(1), 0); 311 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 312 0x060, BIT(5), 0); 313 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 314 0x060, BIT(6), 0); 315 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 316 0x060, BIT(8), 0); 317 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 318 0x060, BIT(9), 0); 319 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 320 0x060, BIT(10), 0); 321 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1", 322 0x060, BIT(11), 0); 323 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 324 0x060, BIT(13), 0); 325 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 326 0x060, BIT(14), 0); 327 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1", 328 0x060, BIT(17), 0); 329 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", 330 0x060, BIT(18), 0); 331 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 332 0x060, BIT(19), 0); 333 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 334 0x060, BIT(20), 0); 335 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 336 0x060, BIT(21), 0); 337 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1", 338 0x060, BIT(22), 0); 339 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1", 340 0x060, BIT(23), 0); 341 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1", 342 0x060, BIT(24), 0); 343 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 344 0x060, BIT(25), 0); 345 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 346 0x060, BIT(26), 0); 347 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1", 348 0x060, BIT(27), 0); 349 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1", 350 0x060, BIT(28), 0); 351 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 352 0x060, BIT(29), 0); 353 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1", 354 0x060, BIT(30), 0); 355 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1", 356 0x060, BIT(31), 0); 357 358 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 359 0x064, BIT(0), 0); 360 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1", 361 0x064, BIT(2), 0); 362 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", 363 0x064, BIT(5), 0); 364 static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1", 365 0x064, BIT(8), 0); 366 static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1", 367 0x064, BIT(9), 0); 368 static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1", 369 0x064, BIT(10), 0); 370 static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1", 371 0x064, BIT(11), 0); 372 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 373 0x064, BIT(12), 0); 374 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1", 375 0x064, BIT(13), 0); 376 static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1", 377 0x064, BIT(14), 0); 378 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1", 379 0x064, BIT(15), 0); 380 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1", 381 0x064, BIT(17), 0); 382 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 383 0x064, BIT(20), 0); 384 static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1", 385 0x064, BIT(21), 0); 386 static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1", 387 0x064, BIT(22), 0); 388 static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1", 389 0x064, BIT(23), 0); 390 static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1", 391 0x064, BIT(24), 0); 392 static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1", 393 0x064, BIT(25), 0); 394 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1", 395 0x064, BIT(26), 0); 396 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1", 397 0x064, BIT(27), 0); 398 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1", 399 0x064, BIT(28), 0); 400 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1", 401 0x064, BIT(29), 0); 402 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1", 403 0x064, BIT(30), 0); 404 405 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 406 0x068, BIT(0), 0); 407 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 408 0x068, BIT(1), 0); 409 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1", 410 0x068, BIT(2), 0); 411 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 412 0x068, BIT(5), 0); 413 static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1", 414 0x068, BIT(6), 0); 415 static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1", 416 0x068, BIT(7), 0); 417 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 418 0x068, BIT(8), 0); 419 static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1", 420 0x068, BIT(10), 0); 421 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 422 0x068, BIT(12), 0); 423 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 424 0x068, BIT(13), 0); 425 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 426 0x068, BIT(14), 0); 427 428 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 429 0x06c, BIT(0), 0); 430 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 431 0x06c, BIT(1), 0); 432 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 433 0x06c, BIT(2), 0); 434 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 435 0x06c, BIT(3), 0); 436 /* 437 * In datasheet here's "Reserved", however the gate exists in BSP soucre 438 * code. 439 */ 440 static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2", 441 0x06c, BIT(4), 0); 442 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 443 0x06c, BIT(5), 0); 444 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2", 445 0x06c, BIT(6), 0); 446 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2", 447 0x06c, BIT(7), 0); 448 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 449 0x06c, BIT(15), 0); 450 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 451 0x06c, BIT(16), 0); 452 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 453 0x06c, BIT(17), 0); 454 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 455 0x06c, BIT(18), 0); 456 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 457 0x06c, BIT(19), 0); 458 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 459 0x06c, BIT(20), 0); 460 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 461 0x06c, BIT(21), 0); 462 static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2", 463 0x06c, BIT(22), 0); 464 static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2", 465 0x06c, BIT(23), 0); 466 467 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 468 0x070, BIT(7), 0); 469 470 static const char * const ths_parents[] = { "osc24M" }; 471 static struct ccu_div ths_clk = { 472 .enable = BIT(31), 473 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 474 .mux = _SUNXI_CCU_MUX(24, 2), 475 .common = { 476 .reg = 0x074, 477 .hw.init = CLK_HW_INIT_PARENTS("ths", 478 ths_parents, 479 &ccu_div_ops, 480 0), 481 }, 482 }; 483 484 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 485 "pll-periph1" }; 486 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 487 0, 4, /* M */ 488 16, 2, /* P */ 489 24, 2, /* mux */ 490 BIT(31), /* gate */ 491 0); 492 493 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 494 0, 4, /* M */ 495 16, 2, /* P */ 496 24, 2, /* mux */ 497 BIT(31), /* gate */ 498 0); 499 500 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 501 0, 4, /* M */ 502 16, 2, /* P */ 503 24, 2, /* mux */ 504 BIT(31), /* gate */ 505 0); 506 507 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 508 0, 4, /* M */ 509 16, 2, /* P */ 510 24, 2, /* mux */ 511 BIT(31), /* gate */ 512 0); 513 514 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094, 515 0, 4, /* M */ 516 16, 2, /* P */ 517 24, 2, /* mux */ 518 BIT(31), /* gate */ 519 0); 520 521 static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; 522 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, 523 0, 4, /* M */ 524 16, 2, /* P */ 525 24, 4, /* mux */ 526 BIT(31), /* gate */ 527 0); 528 529 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x", 530 "pll-periph1-2x" }; 531 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c, 532 0, 4, /* M */ 533 16, 2, /* P */ 534 24, 2, /* mux */ 535 BIT(31), /* gate */ 536 0); 537 538 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 539 0, 4, /* M */ 540 16, 2, /* P */ 541 24, 2, /* mux */ 542 BIT(31), /* gate */ 543 0); 544 545 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 546 0, 4, /* M */ 547 16, 2, /* P */ 548 24, 2, /* mux */ 549 BIT(31), /* gate */ 550 0); 551 552 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8, 553 0, 4, /* M */ 554 16, 2, /* P */ 555 24, 2, /* mux */ 556 BIT(31), /* gate */ 557 0); 558 559 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac, 560 0, 4, /* M */ 561 16, 2, /* P */ 562 24, 2, /* mux */ 563 BIT(31), /* gate */ 564 0); 565 566 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 567 "pll-audio-2x", "pll-audio" }; 568 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 569 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 570 571 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 572 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 573 574 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, 575 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 576 577 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents, 578 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 579 580 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents, 581 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 582 583 static const char * const keypad_parents[] = { "osc24M", "osc32k" }; 584 static const u8 keypad_table[] = { 0, 2 }; 585 static struct ccu_mp keypad_clk = { 586 .enable = BIT(31), 587 .m = _SUNXI_CCU_DIV(0, 5), 588 .p = _SUNXI_CCU_DIV(16, 2), 589 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table), 590 .common = { 591 .reg = 0x0c4, 592 .hw.init = CLK_HW_INIT_PARENTS("keypad", 593 keypad_parents, 594 &ccu_mp_ops, 595 0), 596 } 597 }; 598 599 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" }; 600 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents, 601 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT); 602 603 /* 604 * There are 3 OHCI 12M clock source selection bits in this register. 605 * We will force them to 0 (12M divided from 48M). 606 */ 607 #define SUN8I_R40_USB_CLK_REG 0x0cc 608 609 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 610 0x0cc, BIT(8), 0); 611 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 612 0x0cc, BIT(9), 0); 613 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 614 0x0cc, BIT(10), 0); 615 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 616 0x0cc, BIT(16), 0); 617 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 618 0x0cc, BIT(17), 0); 619 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 620 0x0cc, BIT(18), 0); 621 622 static const char * const ir_parents[] = { "osc24M", "pll-periph0", 623 "pll-periph1", "osc32k" }; 624 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0, 625 0, 4, /* M */ 626 16, 2, /* P */ 627 24, 2, /* mux */ 628 BIT(31), /* gate */ 629 0); 630 631 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4, 632 0, 4, /* M */ 633 16, 2, /* P */ 634 24, 2, /* mux */ 635 BIT(31), /* gate */ 636 0); 637 638 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; 639 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 640 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL); 641 642 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 643 0x100, BIT(0), 0); 644 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram", 645 0x100, BIT(1), 0); 646 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram", 647 0x100, BIT(2), 0); 648 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 649 0x100, BIT(3), 0); 650 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram", 651 0x100, BIT(4), 0); 652 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram", 653 0x100, BIT(5), 0); 654 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 655 0x100, BIT(6), 0); 656 657 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; 658 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 659 0x104, 0, 4, 24, 3, BIT(31), 660 CLK_SET_RATE_PARENT); 661 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents, 662 0x108, 0, 4, 24, 3, BIT(31), 0); 663 664 static const char * const tcon_parents[] = { "pll-video0", "pll-video1", 665 "pll-video0-2x", "pll-video1-2x", 666 "pll-mipi" }; 667 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents, 668 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT); 669 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents, 670 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT); 671 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents, 672 0x118, 0, 4, 24, 3, BIT(31), 673 CLK_SET_RATE_PARENT); 674 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents, 675 0x11c, 0, 4, 24, 3, BIT(31), 676 CLK_SET_RATE_PARENT); 677 678 static const char * const deinterlace_parents[] = { "pll-periph0", 679 "pll-periph1" }; 680 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", 681 deinterlace_parents, 0x124, 0, 4, 24, 3, 682 BIT(31), 0); 683 684 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", 685 "pll-periph1" }; 686 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents, 687 0x130, 0, 5, 8, 3, BIT(15), 0); 688 689 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; 690 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 691 0x134, 16, 4, 24, 3, BIT(31), 0); 692 693 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 694 0x134, 0, 5, 8, 3, BIT(15), 0); 695 696 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 697 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); 698 699 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 700 0x140, BIT(31), CLK_SET_RATE_PARENT); 701 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 702 0x144, BIT(31), 0); 703 704 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; 705 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 706 0x150, 0, 4, 24, 2, BIT(31), 707 CLK_SET_RATE_PARENT); 708 709 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 710 0x154, BIT(31), 0); 711 712 /* 713 * In the SoC's user manual, the P factor is mentioned, but not used in 714 * the frequency formula. 715 * 716 * Here the factor is included, according to the BSP kernel source, 717 * which contains the P factor of this clock. 718 */ 719 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 720 "pll-ddr0" }; 721 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, 722 0, 4, /* M */ 723 16, 2, /* P */ 724 24, 2, /* mux */ 725 BIT(31), /* gate */ 726 CLK_IS_CRITICAL); 727 728 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1", 729 "pll-periph0" }; 730 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, 731 0x168, 0, 4, 8, 2, BIT(15), 0); 732 733 static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents, 734 0x180, 0, 4, 24, 3, BIT(31), 0); 735 static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents, 736 0x184, 0, 4, 24, 3, BIT(31), 0); 737 738 static const char * const tvd_parents[] = { "pll-video0", "pll-video1", 739 "pll-video0-2x", "pll-video1-2x" }; 740 static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents, 741 0x188, 0, 4, 24, 3, BIT(31), 0); 742 static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents, 743 0x18c, 0, 4, 24, 3, BIT(31), 0); 744 static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents, 745 0x190, 0, 4, 24, 3, BIT(31), 0); 746 static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents, 747 0x194, 0, 4, 24, 3, BIT(31), 0); 748 749 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 750 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 751 752 static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" }; 753 static const struct ccu_mux_fixed_prediv out_predivs[] = { 754 { .index = 0, .div = 750, }, 755 }; 756 757 static struct ccu_mp outa_clk = { 758 .enable = BIT(31), 759 .m = _SUNXI_CCU_DIV(8, 5), 760 .p = _SUNXI_CCU_DIV(20, 2), 761 .mux = { 762 .shift = 24, 763 .width = 2, 764 .fixed_predivs = out_predivs, 765 .n_predivs = ARRAY_SIZE(out_predivs), 766 }, 767 .common = { 768 .reg = 0x1f0, 769 .features = CCU_FEATURE_FIXED_PREDIV, 770 .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents, 771 &ccu_mp_ops, 0), 772 } 773 }; 774 775 static struct ccu_mp outb_clk = { 776 .enable = BIT(31), 777 .m = _SUNXI_CCU_DIV(8, 5), 778 .p = _SUNXI_CCU_DIV(20, 2), 779 .mux = { 780 .shift = 24, 781 .width = 2, 782 .fixed_predivs = out_predivs, 783 .n_predivs = ARRAY_SIZE(out_predivs), 784 }, 785 .common = { 786 .reg = 0x1f4, 787 .features = CCU_FEATURE_FIXED_PREDIV, 788 .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents, 789 &ccu_mp_ops, 0), 790 } 791 }; 792 793 static struct ccu_common *sun8i_r40_ccu_clks[] = { 794 &pll_cpu_clk.common, 795 &pll_audio_base_clk.common, 796 &pll_video0_clk.common, 797 &pll_ve_clk.common, 798 &pll_ddr0_clk.common, 799 &pll_periph0_clk.common, 800 &pll_periph0_sata_clk.common, 801 &pll_periph1_clk.common, 802 &pll_video1_clk.common, 803 &pll_sata_clk.common, 804 &pll_sata_out_clk.common, 805 &pll_gpu_clk.common, 806 &pll_mipi_clk.common, 807 &pll_de_clk.common, 808 &pll_ddr1_clk.common, 809 &cpu_clk.common, 810 &axi_clk.common, 811 &ahb1_clk.common, 812 &apb1_clk.common, 813 &apb2_clk.common, 814 &bus_mipi_dsi_clk.common, 815 &bus_ce_clk.common, 816 &bus_dma_clk.common, 817 &bus_mmc0_clk.common, 818 &bus_mmc1_clk.common, 819 &bus_mmc2_clk.common, 820 &bus_mmc3_clk.common, 821 &bus_nand_clk.common, 822 &bus_dram_clk.common, 823 &bus_emac_clk.common, 824 &bus_ts_clk.common, 825 &bus_hstimer_clk.common, 826 &bus_spi0_clk.common, 827 &bus_spi1_clk.common, 828 &bus_spi2_clk.common, 829 &bus_spi3_clk.common, 830 &bus_sata_clk.common, 831 &bus_otg_clk.common, 832 &bus_ehci0_clk.common, 833 &bus_ehci1_clk.common, 834 &bus_ehci2_clk.common, 835 &bus_ohci0_clk.common, 836 &bus_ohci1_clk.common, 837 &bus_ohci2_clk.common, 838 &bus_ve_clk.common, 839 &bus_mp_clk.common, 840 &bus_deinterlace_clk.common, 841 &bus_csi0_clk.common, 842 &bus_csi1_clk.common, 843 &bus_hdmi0_clk.common, 844 &bus_hdmi1_clk.common, 845 &bus_de_clk.common, 846 &bus_tve0_clk.common, 847 &bus_tve1_clk.common, 848 &bus_tve_top_clk.common, 849 &bus_gmac_clk.common, 850 &bus_gpu_clk.common, 851 &bus_tvd0_clk.common, 852 &bus_tvd1_clk.common, 853 &bus_tvd2_clk.common, 854 &bus_tvd3_clk.common, 855 &bus_tvd_top_clk.common, 856 &bus_tcon_lcd0_clk.common, 857 &bus_tcon_lcd1_clk.common, 858 &bus_tcon_tv0_clk.common, 859 &bus_tcon_tv1_clk.common, 860 &bus_tcon_top_clk.common, 861 &bus_codec_clk.common, 862 &bus_spdif_clk.common, 863 &bus_ac97_clk.common, 864 &bus_pio_clk.common, 865 &bus_ir0_clk.common, 866 &bus_ir1_clk.common, 867 &bus_ths_clk.common, 868 &bus_keypad_clk.common, 869 &bus_i2s0_clk.common, 870 &bus_i2s1_clk.common, 871 &bus_i2s2_clk.common, 872 &bus_i2c0_clk.common, 873 &bus_i2c1_clk.common, 874 &bus_i2c2_clk.common, 875 &bus_i2c3_clk.common, 876 &bus_can_clk.common, 877 &bus_scr_clk.common, 878 &bus_ps20_clk.common, 879 &bus_ps21_clk.common, 880 &bus_i2c4_clk.common, 881 &bus_uart0_clk.common, 882 &bus_uart1_clk.common, 883 &bus_uart2_clk.common, 884 &bus_uart3_clk.common, 885 &bus_uart4_clk.common, 886 &bus_uart5_clk.common, 887 &bus_uart6_clk.common, 888 &bus_uart7_clk.common, 889 &bus_dbg_clk.common, 890 &ths_clk.common, 891 &nand_clk.common, 892 &mmc0_clk.common, 893 &mmc1_clk.common, 894 &mmc2_clk.common, 895 &mmc3_clk.common, 896 &ts_clk.common, 897 &ce_clk.common, 898 &spi0_clk.common, 899 &spi1_clk.common, 900 &spi2_clk.common, 901 &spi3_clk.common, 902 &i2s0_clk.common, 903 &i2s1_clk.common, 904 &i2s2_clk.common, 905 &ac97_clk.common, 906 &spdif_clk.common, 907 &keypad_clk.common, 908 &sata_clk.common, 909 &usb_phy0_clk.common, 910 &usb_phy1_clk.common, 911 &usb_phy2_clk.common, 912 &usb_ohci0_clk.common, 913 &usb_ohci1_clk.common, 914 &usb_ohci2_clk.common, 915 &ir0_clk.common, 916 &ir1_clk.common, 917 &dram_clk.common, 918 &dram_ve_clk.common, 919 &dram_csi0_clk.common, 920 &dram_csi1_clk.common, 921 &dram_ts_clk.common, 922 &dram_tvd_clk.common, 923 &dram_mp_clk.common, 924 &dram_deinterlace_clk.common, 925 &de_clk.common, 926 &mp_clk.common, 927 &tcon_lcd0_clk.common, 928 &tcon_lcd1_clk.common, 929 &tcon_tv0_clk.common, 930 &tcon_tv1_clk.common, 931 &deinterlace_clk.common, 932 &csi1_mclk_clk.common, 933 &csi_sclk_clk.common, 934 &csi0_mclk_clk.common, 935 &ve_clk.common, 936 &codec_clk.common, 937 &avs_clk.common, 938 &hdmi_clk.common, 939 &hdmi_slow_clk.common, 940 &mbus_clk.common, 941 &dsi_dphy_clk.common, 942 &tve0_clk.common, 943 &tve1_clk.common, 944 &tvd0_clk.common, 945 &tvd1_clk.common, 946 &tvd2_clk.common, 947 &tvd3_clk.common, 948 &gpu_clk.common, 949 &outa_clk.common, 950 &outb_clk.common, 951 }; 952 953 /* Fixed Factor clocks */ 954 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0); 955 956 /* We hardcode the divider to 4 for now */ 957 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 958 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 959 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 960 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 961 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 962 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 963 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 964 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 965 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", 966 "pll-periph0", 1, 2, 0); 967 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", 968 "pll-periph1", 1, 2, 0); 969 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", 970 "pll-video0", 1, 2, 0); 971 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x", 972 "pll-video1", 1, 2, 0); 973 974 static struct clk_hw_onecell_data sun8i_r40_hw_clks = { 975 .hws = { 976 [CLK_OSC_12M] = &osc12M_clk.hw, 977 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 978 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 979 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 980 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 981 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 982 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 983 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 984 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, 985 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 986 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 987 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 988 [CLK_PLL_PERIPH0_SATA] = &pll_periph0_sata_clk.common.hw, 989 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 990 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 991 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 992 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 993 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw, 994 [CLK_PLL_SATA] = &pll_sata_clk.common.hw, 995 [CLK_PLL_SATA_OUT] = &pll_sata_out_clk.common.hw, 996 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 997 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 998 [CLK_PLL_DE] = &pll_de_clk.common.hw, 999 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 1000 [CLK_CPU] = &cpu_clk.common.hw, 1001 [CLK_AXI] = &axi_clk.common.hw, 1002 [CLK_AHB1] = &ahb1_clk.common.hw, 1003 [CLK_APB1] = &apb1_clk.common.hw, 1004 [CLK_APB2] = &apb2_clk.common.hw, 1005 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 1006 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 1007 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 1008 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 1009 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 1010 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 1011 [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw, 1012 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 1013 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 1014 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 1015 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 1016 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 1017 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 1018 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 1019 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, 1020 [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw, 1021 [CLK_BUS_SATA] = &bus_sata_clk.common.hw, 1022 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 1023 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 1024 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 1025 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw, 1026 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 1027 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 1028 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw, 1029 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 1030 [CLK_BUS_MP] = &bus_mp_clk.common.hw, 1031 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 1032 [CLK_BUS_CSI0] = &bus_csi0_clk.common.hw, 1033 [CLK_BUS_CSI1] = &bus_csi1_clk.common.hw, 1034 [CLK_BUS_HDMI0] = &bus_hdmi0_clk.common.hw, 1035 [CLK_BUS_HDMI1] = &bus_hdmi1_clk.common.hw, 1036 [CLK_BUS_DE] = &bus_de_clk.common.hw, 1037 [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw, 1038 [CLK_BUS_TVE1] = &bus_tve1_clk.common.hw, 1039 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw, 1040 [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw, 1041 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 1042 [CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw, 1043 [CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw, 1044 [CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw, 1045 [CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw, 1046 [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw, 1047 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, 1048 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw, 1049 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, 1050 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw, 1051 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw, 1052 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 1053 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 1054 [CLK_BUS_AC97] = &bus_ac97_clk.common.hw, 1055 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 1056 [CLK_BUS_IR0] = &bus_ir0_clk.common.hw, 1057 [CLK_BUS_IR1] = &bus_ir1_clk.common.hw, 1058 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 1059 [CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw, 1060 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 1061 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 1062 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 1063 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 1064 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 1065 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 1066 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 1067 [CLK_BUS_CAN] = &bus_can_clk.common.hw, 1068 [CLK_BUS_SCR] = &bus_scr_clk.common.hw, 1069 [CLK_BUS_PS20] = &bus_ps20_clk.common.hw, 1070 [CLK_BUS_PS21] = &bus_ps21_clk.common.hw, 1071 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, 1072 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 1073 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 1074 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 1075 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 1076 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 1077 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, 1078 [CLK_BUS_UART6] = &bus_uart6_clk.common.hw, 1079 [CLK_BUS_UART7] = &bus_uart7_clk.common.hw, 1080 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 1081 [CLK_THS] = &ths_clk.common.hw, 1082 [CLK_NAND] = &nand_clk.common.hw, 1083 [CLK_MMC0] = &mmc0_clk.common.hw, 1084 [CLK_MMC1] = &mmc1_clk.common.hw, 1085 [CLK_MMC2] = &mmc2_clk.common.hw, 1086 [CLK_MMC3] = &mmc3_clk.common.hw, 1087 [CLK_TS] = &ts_clk.common.hw, 1088 [CLK_CE] = &ce_clk.common.hw, 1089 [CLK_SPI0] = &spi0_clk.common.hw, 1090 [CLK_SPI1] = &spi1_clk.common.hw, 1091 [CLK_SPI2] = &spi2_clk.common.hw, 1092 [CLK_SPI3] = &spi3_clk.common.hw, 1093 [CLK_I2S0] = &i2s0_clk.common.hw, 1094 [CLK_I2S1] = &i2s1_clk.common.hw, 1095 [CLK_I2S2] = &i2s2_clk.common.hw, 1096 [CLK_AC97] = &ac97_clk.common.hw, 1097 [CLK_SPDIF] = &spdif_clk.common.hw, 1098 [CLK_KEYPAD] = &keypad_clk.common.hw, 1099 [CLK_SATA] = &sata_clk.common.hw, 1100 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 1101 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 1102 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw, 1103 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 1104 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 1105 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, 1106 [CLK_IR0] = &ir0_clk.common.hw, 1107 [CLK_IR1] = &ir1_clk.common.hw, 1108 [CLK_DRAM] = &dram_clk.common.hw, 1109 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 1110 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw, 1111 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw, 1112 [CLK_DRAM_TS] = &dram_ts_clk.common.hw, 1113 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw, 1114 [CLK_DRAM_MP] = &dram_mp_clk.common.hw, 1115 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, 1116 [CLK_DE] = &de_clk.common.hw, 1117 [CLK_MP] = &mp_clk.common.hw, 1118 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, 1119 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, 1120 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw, 1121 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw, 1122 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 1123 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 1124 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 1125 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 1126 [CLK_VE] = &ve_clk.common.hw, 1127 [CLK_CODEC] = &codec_clk.common.hw, 1128 [CLK_AVS] = &avs_clk.common.hw, 1129 [CLK_HDMI] = &hdmi_clk.common.hw, 1130 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 1131 [CLK_MBUS] = &mbus_clk.common.hw, 1132 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, 1133 [CLK_TVE0] = &tve0_clk.common.hw, 1134 [CLK_TVE1] = &tve1_clk.common.hw, 1135 [CLK_TVD0] = &tvd0_clk.common.hw, 1136 [CLK_TVD1] = &tvd1_clk.common.hw, 1137 [CLK_TVD2] = &tvd2_clk.common.hw, 1138 [CLK_TVD3] = &tvd3_clk.common.hw, 1139 [CLK_GPU] = &gpu_clk.common.hw, 1140 [CLK_OUTA] = &outa_clk.common.hw, 1141 [CLK_OUTB] = &outb_clk.common.hw, 1142 }, 1143 .num = CLK_NUMBER, 1144 }; 1145 1146 static struct ccu_reset_map sun8i_r40_ccu_resets[] = { 1147 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 1148 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 1149 [RST_USB_PHY2] = { 0x0cc, BIT(2) }, 1150 1151 [RST_DRAM] = { 0x0f4, BIT(31) }, 1152 [RST_MBUS] = { 0x0fc, BIT(31) }, 1153 1154 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 1155 [RST_BUS_CE] = { 0x2c0, BIT(5) }, 1156 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 1157 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 1158 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 1159 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 1160 [RST_BUS_MMC3] = { 0x2c0, BIT(11) }, 1161 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 1162 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 1163 [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 1164 [RST_BUS_TS] = { 0x2c0, BIT(18) }, 1165 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 1166 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 1167 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 1168 [RST_BUS_SPI2] = { 0x2c0, BIT(22) }, 1169 [RST_BUS_SPI3] = { 0x2c0, BIT(23) }, 1170 [RST_BUS_SATA] = { 0x2c0, BIT(24) }, 1171 [RST_BUS_OTG] = { 0x2c0, BIT(25) }, 1172 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, 1173 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) }, 1174 [RST_BUS_EHCI2] = { 0x2c0, BIT(28) }, 1175 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, 1176 [RST_BUS_OHCI1] = { 0x2c0, BIT(30) }, 1177 [RST_BUS_OHCI2] = { 0x2c0, BIT(31) }, 1178 1179 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 1180 [RST_BUS_MP] = { 0x2c4, BIT(2) }, 1181 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, 1182 [RST_BUS_CSI0] = { 0x2c4, BIT(8) }, 1183 [RST_BUS_CSI1] = { 0x2c4, BIT(9) }, 1184 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, 1185 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, 1186 [RST_BUS_DE] = { 0x2c4, BIT(12) }, 1187 [RST_BUS_TVE0] = { 0x2c4, BIT(13) }, 1188 [RST_BUS_TVE1] = { 0x2c4, BIT(14) }, 1189 [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) }, 1190 [RST_BUS_GMAC] = { 0x2c4, BIT(17) }, 1191 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 1192 [RST_BUS_TVD0] = { 0x2c4, BIT(21) }, 1193 [RST_BUS_TVD1] = { 0x2c4, BIT(22) }, 1194 [RST_BUS_TVD2] = { 0x2c4, BIT(23) }, 1195 [RST_BUS_TVD3] = { 0x2c4, BIT(24) }, 1196 [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) }, 1197 [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) }, 1198 [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) }, 1199 [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) }, 1200 [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) }, 1201 [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) }, 1202 [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 1203 1204 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 1205 1206 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 1207 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, 1208 [RST_BUS_AC97] = { 0x2d0, BIT(2) }, 1209 [RST_BUS_IR0] = { 0x2d0, BIT(6) }, 1210 [RST_BUS_IR1] = { 0x2d0, BIT(7) }, 1211 [RST_BUS_THS] = { 0x2d0, BIT(8) }, 1212 [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) }, 1213 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 1214 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 1215 [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, 1216 1217 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 1218 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 1219 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 1220 [RST_BUS_I2C3] = { 0x2d8, BIT(3) }, 1221 [RST_BUS_CAN] = { 0x2d8, BIT(4) }, 1222 [RST_BUS_SCR] = { 0x2d8, BIT(5) }, 1223 [RST_BUS_PS20] = { 0x2d8, BIT(6) }, 1224 [RST_BUS_PS21] = { 0x2d8, BIT(7) }, 1225 [RST_BUS_I2C4] = { 0x2d8, BIT(15) }, 1226 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 1227 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 1228 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 1229 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 1230 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 1231 [RST_BUS_UART5] = { 0x2d8, BIT(21) }, 1232 [RST_BUS_UART6] = { 0x2d8, BIT(22) }, 1233 [RST_BUS_UART7] = { 0x2d8, BIT(23) }, 1234 }; 1235 1236 static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = { 1237 .ccu_clks = sun8i_r40_ccu_clks, 1238 .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks), 1239 1240 .hw_clks = &sun8i_r40_hw_clks, 1241 1242 .resets = sun8i_r40_ccu_resets, 1243 .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets), 1244 }; 1245 1246 static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = { 1247 .common = &pll_cpu_clk.common, 1248 /* copy from pll_cpu_clk */ 1249 .enable = BIT(31), 1250 .lock = BIT(28), 1251 }; 1252 1253 static struct ccu_mux_nb sun8i_r40_cpu_nb = { 1254 .common = &cpu_clk.common, 1255 .cm = &cpu_clk.mux, 1256 .delay_us = 1, /* > 8 clock cycles at 24 MHz */ 1257 .bypass_index = 1, /* index of 24 MHz oscillator */ 1258 }; 1259 1260 /* 1261 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the 1262 * GMAC configuration register. 1263 * Only this register is allowed to be written, in order to 1264 * prevent overriding critical clock configuration. 1265 */ 1266 1267 #define SUN8I_R40_GMAC_CFG_REG 0x164 1268 static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev, 1269 unsigned int reg) 1270 { 1271 if (reg == SUN8I_R40_GMAC_CFG_REG) 1272 return true; 1273 return false; 1274 } 1275 1276 static struct regmap_config sun8i_r40_ccu_regmap_config = { 1277 .reg_bits = 32, 1278 .val_bits = 32, 1279 .reg_stride = 4, 1280 .max_register = 0x320, /* PLL_LOCK_CTRL_REG */ 1281 1282 /* other devices have no business accessing other registers */ 1283 .readable_reg = sun8i_r40_ccu_regmap_accessible_reg, 1284 .writeable_reg = sun8i_r40_ccu_regmap_accessible_reg, 1285 }; 1286 1287 #define SUN8I_R40_SYS_32K_CLK_REG 0x310 1288 #define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16) 1289 1290 static int sun8i_r40_ccu_probe(struct platform_device *pdev) 1291 { 1292 struct resource *res; 1293 struct regmap *regmap; 1294 void __iomem *reg; 1295 u32 val; 1296 int ret; 1297 1298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1299 reg = devm_ioremap_resource(&pdev->dev, res); 1300 if (IS_ERR(reg)) 1301 return PTR_ERR(reg); 1302 1303 /* Force the PLL-Audio-1x divider to 4 */ 1304 val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); 1305 val &= ~GENMASK(19, 16); 1306 writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); 1307 1308 /* Force PLL-MIPI to MIPI mode */ 1309 val = readl(reg + SUN8I_R40_PLL_MIPI_REG); 1310 val &= ~BIT(16); 1311 writel(val, reg + SUN8I_R40_PLL_MIPI_REG); 1312 1313 /* Force OHCI 12M parent to 12M divided from 48M */ 1314 val = readl(reg + SUN8I_R40_USB_CLK_REG); 1315 val &= ~GENMASK(25, 20); 1316 writel(val, reg + SUN8I_R40_USB_CLK_REG); 1317 1318 /* 1319 * Force SYS 32k (otherwise known as LOSC throughout the CCU) 1320 * clock parent to LOSC output from RTC module instead of the 1321 * CCU's internal RC oscillator divided output. 1322 */ 1323 writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8), 1324 reg + SUN8I_R40_SYS_32K_CLK_REG); 1325 1326 regmap = devm_regmap_init_mmio(&pdev->dev, reg, 1327 &sun8i_r40_ccu_regmap_config); 1328 if (IS_ERR(regmap)) 1329 return PTR_ERR(regmap); 1330 1331 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc); 1332 if (ret) 1333 return ret; 1334 1335 /* Gate then ungate PLL CPU after any rate changes */ 1336 ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb); 1337 1338 /* Reparent CPU during PLL CPU rate changes */ 1339 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, 1340 &sun8i_r40_cpu_nb); 1341 1342 return 0; 1343 } 1344 1345 static const struct of_device_id sun8i_r40_ccu_ids[] = { 1346 { .compatible = "allwinner,sun8i-r40-ccu" }, 1347 { } 1348 }; 1349 1350 static struct platform_driver sun8i_r40_ccu_driver = { 1351 .probe = sun8i_r40_ccu_probe, 1352 .driver = { 1353 .name = "sun8i-r40-ccu", 1354 .of_match_table = sun8i_r40_ccu_ids, 1355 }, 1356 }; 1357 builtin_platform_driver(sun8i_r40_ccu_driver); 1358