1 /*
2  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include <linux/clk-provider.h>
15 #include <linux/io.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 
19 #include "ccu_common.h"
20 #include "ccu_reset.h"
21 
22 #include "ccu_div.h"
23 #include "ccu_gate.h"
24 #include "ccu_mp.h"
25 #include "ccu_mult.h"
26 #include "ccu_nk.h"
27 #include "ccu_nkm.h"
28 #include "ccu_nkmp.h"
29 #include "ccu_nm.h"
30 #include "ccu_phase.h"
31 
32 #include "ccu-sun8i-r40.h"
33 
34 /* TODO: The result of N*K is required to be in [10, 88] range. */
35 static struct ccu_nkmp pll_cpu_clk = {
36 	.enable		= BIT(31),
37 	.lock		= BIT(28),
38 	.n		= _SUNXI_CCU_MULT(8, 5),
39 	.k		= _SUNXI_CCU_MULT(4, 2),
40 	.m		= _SUNXI_CCU_DIV(0, 2),
41 	.p		= _SUNXI_CCU_DIV_MAX(16, 2, 4),
42 	.common		= {
43 		.reg		= 0x000,
44 		.hw.init	= CLK_HW_INIT("pll-cpu",
45 					      "osc24M",
46 					      &ccu_nkmp_ops,
47 					      CLK_SET_RATE_UNGATE),
48 	},
49 };
50 
51 /*
52  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
53  * the base (2x, 4x and 8x), and one variable divider (the one true
54  * pll audio).
55  *
56  * We don't have any need for the variable divider for now, so we just
57  * hardcode it to match with the clock names
58  */
59 #define SUN8I_R40_PLL_AUDIO_REG	0x008
60 
61 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
62 				   "osc24M", 0x008,
63 				   8, 7,	/* N */
64 				   0, 5,	/* M */
65 				   BIT(31),	/* gate */
66 				   BIT(28),	/* lock */
67 				   CLK_SET_RATE_UNGATE);
68 
69 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
70 						"osc24M", 0x0010,
71 						192000000,  /* Minimum rate */
72 						1008000000, /* Maximum rate */
73 						8, 7,       /* N */
74 						0, 4,       /* M */
75 						BIT(24),    /* frac enable */
76 						BIT(25),    /* frac select */
77 						270000000,  /* frac rate 0 */
78 						297000000,  /* frac rate 1 */
79 						BIT(31),    /* gate */
80 						BIT(28),    /* lock */
81 						CLK_SET_RATE_UNGATE);
82 
83 /* TODO: The result of N/M is required to be in [8, 25] range. */
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
85 					"osc24M", 0x0018,
86 					8, 7,		/* N */
87 					0, 4,		/* M */
88 					BIT(24),	/* frac enable */
89 					BIT(25),	/* frac select */
90 					270000000,	/* frac rate 0 */
91 					297000000,	/* frac rate 1 */
92 					BIT(31),	/* gate */
93 					BIT(28),	/* lock */
94 					CLK_SET_RATE_UNGATE);
95 
96 /* TODO: The result of N*K is required to be in [10, 77] range. */
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
98 				    "osc24M", 0x020,
99 				    8, 5,	/* N */
100 				    4, 2,	/* K */
101 				    0, 2,	/* M */
102 				    BIT(31),	/* gate */
103 				    BIT(28),	/* lock */
104 				    CLK_SET_RATE_UNGATE);
105 
106 /* TODO: The result of N*K is required to be in [21, 58] range. */
107 static struct ccu_nk pll_periph0_clk = {
108 	.enable		= BIT(31),
109 	.lock		= BIT(28),
110 	.n		= _SUNXI_CCU_MULT(8, 5),
111 	.k		= _SUNXI_CCU_MULT(4, 2),
112 	.fixed_post_div	= 2,
113 	.common		= {
114 		.reg		= 0x028,
115 		.features	= CCU_FEATURE_FIXED_POSTDIV,
116 		.hw.init	= CLK_HW_INIT("pll-periph0", "osc24M",
117 					      &ccu_nk_ops,
118 					      CLK_SET_RATE_UNGATE),
119 	},
120 };
121 
122 static struct ccu_div pll_periph0_sata_clk = {
123 	.enable		= BIT(24),
124 	.div		= _SUNXI_CCU_DIV(0, 2),
125 	/*
126 	 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
127 	 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
128 	 * 6/2 = 3.
129 	 */
130 	.fixed_post_div	= 3,
131 	.common		= {
132 		.reg		= 0x028,
133 		.features	= CCU_FEATURE_FIXED_POSTDIV,
134 		.hw.init	= CLK_HW_INIT("pll-periph0-sata",
135 					      "pll-periph0",
136 					      &ccu_div_ops, 0),
137 	},
138 };
139 
140 /* TODO: The result of N*K is required to be in [21, 58] range. */
141 static struct ccu_nk pll_periph1_clk = {
142 	.enable		= BIT(31),
143 	.lock		= BIT(28),
144 	.n		= _SUNXI_CCU_MULT(8, 5),
145 	.k		= _SUNXI_CCU_MULT(4, 2),
146 	.fixed_post_div	= 2,
147 	.common		= {
148 		.reg		= 0x02c,
149 		.features	= CCU_FEATURE_FIXED_POSTDIV,
150 		.hw.init	= CLK_HW_INIT("pll-periph1", "osc24M",
151 					      &ccu_nk_ops,
152 					      CLK_SET_RATE_UNGATE),
153 	},
154 };
155 
156 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
157 						"osc24M", 0x030,
158 						192000000,  /* Minimum rate */
159 						1008000000, /* Maximum rate */
160 						8, 7,       /* N */
161 						0, 4,       /* M */
162 						BIT(24),    /* frac enable */
163 						BIT(25),    /* frac select */
164 						270000000,  /* frac rate 0 */
165 						297000000,  /* frac rate 1 */
166 						BIT(31),    /* gate */
167 						BIT(28),    /* lock */
168 						CLK_SET_RATE_UNGATE);
169 
170 static struct ccu_nkm pll_sata_clk = {
171 	.enable		= BIT(31),
172 	.lock		= BIT(28),
173 	.n		= _SUNXI_CCU_MULT(8, 5),
174 	.k		= _SUNXI_CCU_MULT(4, 2),
175 	.m		= _SUNXI_CCU_DIV(0, 2),
176 	.fixed_post_div	= 6,
177 	.common		= {
178 		.reg		= 0x034,
179 		.features	= CCU_FEATURE_FIXED_POSTDIV,
180 		.hw.init	= CLK_HW_INIT("pll-sata", "osc24M",
181 					      &ccu_nkm_ops,
182 					      CLK_SET_RATE_UNGATE),
183 	},
184 };
185 
186 static const char * const pll_sata_out_parents[] = { "pll-sata",
187 						     "pll-periph0-sata" };
188 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
189 			       pll_sata_out_parents, 0x034,
190 			       30, 1,	/* mux */
191 			       BIT(14),	/* gate */
192 			       CLK_SET_RATE_PARENT);
193 
194 /* TODO: The result of N/M is required to be in [8, 25] range. */
195 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
196 					"osc24M", 0x038,
197 					8, 7,		/* N */
198 					0, 4,		/* M */
199 					BIT(24),	/* frac enable */
200 					BIT(25),	/* frac select */
201 					270000000,	/* frac rate 0 */
202 					297000000,	/* frac rate 1 */
203 					BIT(31),	/* gate */
204 					BIT(28),	/* lock */
205 					CLK_SET_RATE_UNGATE);
206 
207 /*
208  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
209  *
210  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
211  * integer / fractional clock with switchable multipliers and dividers.
212  * This is not supported here. We hardcode the PLL to MIPI mode.
213  *
214  * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
215  * which cannot be implemented now.
216  */
217 #define SUN8I_R40_PLL_MIPI_REG	0x040
218 
219 static const char * const pll_mipi_parents[] = { "pll-video0" };
220 static struct ccu_nkm pll_mipi_clk = {
221 	.enable	= BIT(31) | BIT(23) | BIT(22),
222 	.lock	= BIT(28),
223 	.n	= _SUNXI_CCU_MULT(8, 4),
224 	.k	= _SUNXI_CCU_MULT_MIN(4, 2, 2),
225 	.m	= _SUNXI_CCU_DIV(0, 4),
226 	.mux	= _SUNXI_CCU_MUX(21, 1),
227 	.common	= {
228 		.reg		= 0x040,
229 		.hw.init	= CLK_HW_INIT_PARENTS("pll-mipi",
230 						      pll_mipi_parents,
231 						      &ccu_nkm_ops,
232 						      CLK_SET_RATE_UNGATE)
233 	},
234 };
235 
236 /* TODO: The result of N/M is required to be in [8, 25] range. */
237 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
238 					"osc24M", 0x048,
239 					8, 7,		/* N */
240 					0, 4,		/* M */
241 					BIT(24),	/* frac enable */
242 					BIT(25),	/* frac select */
243 					270000000,	/* frac rate 0 */
244 					297000000,	/* frac rate 1 */
245 					BIT(31),	/* gate */
246 					BIT(28),	/* lock */
247 					CLK_SET_RATE_UNGATE);
248 
249 /* TODO: The N factor is required to be in [16, 75] range. */
250 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
251 				   "osc24M", 0x04c,
252 				   8, 7,	/* N */
253 				   0, 2,	/* M */
254 				   BIT(31),	/* gate */
255 				   BIT(28),	/* lock */
256 				   CLK_SET_RATE_UNGATE);
257 
258 static const char * const cpu_parents[] = { "osc32k", "osc24M",
259 					     "pll-cpu", "pll-cpu" };
260 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
261 		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
262 
263 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
264 
265 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
266 					     "axi", "pll-periph0" };
267 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
268 	{ .index = 3, .shift = 6, .width = 2 },
269 };
270 static struct ccu_div ahb1_clk = {
271 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
272 
273 	.mux		= {
274 		.shift	= 12,
275 		.width	= 2,
276 
277 		.var_predivs	= ahb1_predivs,
278 		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
279 	},
280 
281 	.common		= {
282 		.reg		= 0x054,
283 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
284 		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
285 						      ahb1_parents,
286 						      &ccu_div_ops,
287 						      0),
288 	},
289 };
290 
291 static struct clk_div_table apb1_div_table[] = {
292 	{ .val = 0, .div = 2 },
293 	{ .val = 1, .div = 2 },
294 	{ .val = 2, .div = 4 },
295 	{ .val = 3, .div = 8 },
296 	{ /* Sentinel */ },
297 };
298 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
299 			   0x054, 8, 2, apb1_div_table, 0);
300 
301 static const char * const apb2_parents[] = { "osc32k", "osc24M",
302 					     "pll-periph0-2x",
303 					     "pll-periph0-2x" };
304 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
305 			     0, 5,	/* M */
306 			     16, 2,	/* P */
307 			     24, 2,	/* mux */
308 			     0);
309 
310 static SUNXI_CCU_GATE(bus_mipi_dsi_clk,	"bus-mipi-dsi",	"ahb1",
311 		      0x060, BIT(1), 0);
312 static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
313 		      0x060, BIT(5), 0);
314 static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
315 		      0x060, BIT(6), 0);
316 static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
317 		      0x060, BIT(8), 0);
318 static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
319 		      0x060, BIT(9), 0);
320 static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
321 		      0x060, BIT(10), 0);
322 static SUNXI_CCU_GATE(bus_mmc3_clk,	"bus-mmc3",	"ahb1",
323 		      0x060, BIT(11), 0);
324 static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
325 		      0x060, BIT(13), 0);
326 static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
327 		      0x060, BIT(14), 0);
328 static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb1",
329 		      0x060, BIT(17), 0);
330 static SUNXI_CCU_GATE(bus_ts_clk,	"bus-ts",	"ahb1",
331 		      0x060, BIT(18), 0);
332 static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
333 		      0x060, BIT(19), 0);
334 static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
335 		      0x060, BIT(20), 0);
336 static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
337 		      0x060, BIT(21), 0);
338 static SUNXI_CCU_GATE(bus_spi2_clk,	"bus-spi2",	"ahb1",
339 		      0x060, BIT(22), 0);
340 static SUNXI_CCU_GATE(bus_spi3_clk,	"bus-spi3",	"ahb1",
341 		      0x060, BIT(23), 0);
342 static SUNXI_CCU_GATE(bus_sata_clk,	"bus-sata",	"ahb1",
343 		      0x060, BIT(24), 0);
344 static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
345 		      0x060, BIT(25), 0);
346 static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
347 		      0x060, BIT(26), 0);
348 static SUNXI_CCU_GATE(bus_ehci1_clk,	"bus-ehci1",	"ahb1",
349 		      0x060, BIT(27), 0);
350 static SUNXI_CCU_GATE(bus_ehci2_clk,	"bus-ehci2",	"ahb1",
351 		      0x060, BIT(28), 0);
352 static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
353 		      0x060, BIT(29), 0);
354 static SUNXI_CCU_GATE(bus_ohci1_clk,	"bus-ohci1",	"ahb1",
355 		      0x060, BIT(30), 0);
356 static SUNXI_CCU_GATE(bus_ohci2_clk,	"bus-ohci2",	"ahb1",
357 		      0x060, BIT(31), 0);
358 
359 static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
360 		      0x064, BIT(0), 0);
361 static SUNXI_CCU_GATE(bus_mp_clk,	"bus-mp",	"ahb1",
362 		      0x064, BIT(2), 0);
363 static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb1",
364 		      0x064, BIT(5), 0);
365 static SUNXI_CCU_GATE(bus_csi0_clk,	"bus-csi0",	"ahb1",
366 		      0x064, BIT(8), 0);
367 static SUNXI_CCU_GATE(bus_csi1_clk,	"bus-csi1",	"ahb1",
368 		      0x064, BIT(9), 0);
369 static SUNXI_CCU_GATE(bus_hdmi0_clk,	"bus-hdmi0",	"ahb1",
370 		      0x064, BIT(10), 0);
371 static SUNXI_CCU_GATE(bus_hdmi1_clk,	"bus-hdmi1",	"ahb1",
372 		      0x064, BIT(11), 0);
373 static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
374 		      0x064, BIT(12), 0);
375 static SUNXI_CCU_GATE(bus_tve0_clk,	"bus-tve0",	"ahb1",
376 		      0x064, BIT(13), 0);
377 static SUNXI_CCU_GATE(bus_tve1_clk,	"bus-tve1",	"ahb1",
378 		      0x064, BIT(14), 0);
379 static SUNXI_CCU_GATE(bus_tve_top_clk,	"bus-tve-top",	"ahb1",
380 		      0x064, BIT(15), 0);
381 static SUNXI_CCU_GATE(bus_gmac_clk,	"bus-gmac",	"ahb1",
382 		      0x064, BIT(17), 0);
383 static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
384 		      0x064, BIT(20), 0);
385 static SUNXI_CCU_GATE(bus_tvd0_clk,	"bus-tvd0",	"ahb1",
386 		      0x064, BIT(21), 0);
387 static SUNXI_CCU_GATE(bus_tvd1_clk,	"bus-tvd1",	"ahb1",
388 		      0x064, BIT(22), 0);
389 static SUNXI_CCU_GATE(bus_tvd2_clk,	"bus-tvd2",	"ahb1",
390 		      0x064, BIT(23), 0);
391 static SUNXI_CCU_GATE(bus_tvd3_clk,	"bus-tvd3",	"ahb1",
392 		      0x064, BIT(24), 0);
393 static SUNXI_CCU_GATE(bus_tvd_top_clk,	"bus-tvd-top",	"ahb1",
394 		      0x064, BIT(25), 0);
395 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk,	"bus-tcon-lcd0",	"ahb1",
396 		      0x064, BIT(26), 0);
397 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk,	"bus-tcon-lcd1",	"ahb1",
398 		      0x064, BIT(27), 0);
399 static SUNXI_CCU_GATE(bus_tcon_tv0_clk,	"bus-tcon-tv0",	"ahb1",
400 		      0x064, BIT(28), 0);
401 static SUNXI_CCU_GATE(bus_tcon_tv1_clk,	"bus-tcon-tv1",	"ahb1",
402 		      0x064, BIT(29), 0);
403 static SUNXI_CCU_GATE(bus_tcon_top_clk,	"bus-tcon-top",	"ahb1",
404 		      0x064, BIT(30), 0);
405 
406 static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
407 		      0x068, BIT(0), 0);
408 static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb1",
409 		      0x068, BIT(1), 0);
410 static SUNXI_CCU_GATE(bus_ac97_clk,	"bus-ac97",	"apb1",
411 		      0x068, BIT(2), 0);
412 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
413 		      0x068, BIT(5), 0);
414 static SUNXI_CCU_GATE(bus_ir0_clk,	"bus-ir0",	"apb1",
415 		      0x068, BIT(6), 0);
416 static SUNXI_CCU_GATE(bus_ir1_clk,	"bus-ir1",	"apb1",
417 		      0x068, BIT(7), 0);
418 static SUNXI_CCU_GATE(bus_ths_clk,	"bus-ths",	"apb1",
419 		      0x068, BIT(8), 0);
420 static SUNXI_CCU_GATE(bus_keypad_clk,	"bus-keypad",	"apb1",
421 		      0x068, BIT(10), 0);
422 static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
423 		      0x068, BIT(12), 0);
424 static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
425 		      0x068, BIT(13), 0);
426 static SUNXI_CCU_GATE(bus_i2s2_clk,	"bus-i2s2",	"apb1",
427 		      0x068, BIT(14), 0);
428 
429 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
430 		      0x06c, BIT(0), 0);
431 static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
432 		      0x06c, BIT(1), 0);
433 static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
434 		      0x06c, BIT(2), 0);
435 static SUNXI_CCU_GATE(bus_i2c3_clk,	"bus-i2c3",	"apb2",
436 		      0x06c, BIT(3), 0);
437 /*
438  * In datasheet here's "Reserved", however the gate exists in BSP soucre
439  * code.
440  */
441 static SUNXI_CCU_GATE(bus_can_clk,	"bus-can",	"apb2",
442 		      0x06c, BIT(4), 0);
443 static SUNXI_CCU_GATE(bus_scr_clk,	"bus-scr",	"apb2",
444 		      0x06c, BIT(5), 0);
445 static SUNXI_CCU_GATE(bus_ps20_clk,	"bus-ps20",	"apb2",
446 		      0x06c, BIT(6), 0);
447 static SUNXI_CCU_GATE(bus_ps21_clk,	"bus-ps21",	"apb2",
448 		      0x06c, BIT(7), 0);
449 static SUNXI_CCU_GATE(bus_i2c4_clk,	"bus-i2c4",	"apb2",
450 		      0x06c, BIT(15), 0);
451 static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
452 		      0x06c, BIT(16), 0);
453 static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
454 		      0x06c, BIT(17), 0);
455 static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
456 		      0x06c, BIT(18), 0);
457 static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
458 		      0x06c, BIT(19), 0);
459 static SUNXI_CCU_GATE(bus_uart4_clk,	"bus-uart4",	"apb2",
460 		      0x06c, BIT(20), 0);
461 static SUNXI_CCU_GATE(bus_uart5_clk,	"bus-uart5",	"apb2",
462 		      0x06c, BIT(21), 0);
463 static SUNXI_CCU_GATE(bus_uart6_clk,	"bus-uart6",	"apb2",
464 		      0x06c, BIT(22), 0);
465 static SUNXI_CCU_GATE(bus_uart7_clk,	"bus-uart7",	"apb2",
466 		      0x06c, BIT(23), 0);
467 
468 static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
469 		      0x070, BIT(7), 0);
470 
471 static const char * const ths_parents[] = { "osc24M" };
472 static struct ccu_div ths_clk = {
473 	.enable	= BIT(31),
474 	.div	= _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
475 	.mux	= _SUNXI_CCU_MUX(24, 2),
476 	.common	= {
477 		.reg		= 0x074,
478 		.hw.init	= CLK_HW_INIT_PARENTS("ths",
479 						      ths_parents,
480 						      &ccu_div_ops,
481 						      0),
482 	},
483 };
484 
485 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
486 						     "pll-periph1" };
487 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
488 				  0, 4,		/* M */
489 				  16, 2,	/* P */
490 				  24, 2,	/* mux */
491 				  BIT(31),	/* gate */
492 				  0);
493 
494 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
495 				  0, 4,		/* M */
496 				  16, 2,	/* P */
497 				  24, 2,	/* mux */
498 				  BIT(31),	/* gate */
499 				  0);
500 
501 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
502 				  0, 4,		/* M */
503 				  16, 2,	/* P */
504 				  24, 2,	/* mux */
505 				  BIT(31),	/* gate */
506 				  0);
507 
508 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
509 				  0, 4,		/* M */
510 				  16, 2,	/* P */
511 				  24, 2,	/* mux */
512 				  BIT(31),	/* gate */
513 				  0);
514 
515 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
516 				  0, 4,		/* M */
517 				  16, 2,	/* P */
518 				  24, 2,	/* mux */
519 				  BIT(31),	/* gate */
520 				  0);
521 
522 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
523 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
524 				  0, 4,		/* M */
525 				  16, 2,	/* P */
526 				  24, 4,	/* mux */
527 				  BIT(31),	/* gate */
528 				  0);
529 
530 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
531 					   "pll-periph1-2x" };
532 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
533 				  0, 4,		/* M */
534 				  16, 2,	/* P */
535 				  24, 2,	/* mux */
536 				  BIT(31),	/* gate */
537 				  0);
538 
539 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
540 				  0, 4,		/* M */
541 				  16, 2,	/* P */
542 				  24, 2,	/* mux */
543 				  BIT(31),	/* gate */
544 				  0);
545 
546 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
547 				  0, 4,		/* M */
548 				  16, 2,	/* P */
549 				  24, 2,	/* mux */
550 				  BIT(31),	/* gate */
551 				  0);
552 
553 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
554 				  0, 4,		/* M */
555 				  16, 2,	/* P */
556 				  24, 2,	/* mux */
557 				  BIT(31),	/* gate */
558 				  0);
559 
560 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
561 				  0, 4,		/* M */
562 				  16, 2,	/* P */
563 				  24, 2,	/* mux */
564 				  BIT(31),	/* gate */
565 				  0);
566 
567 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
568 					    "pll-audio-2x", "pll-audio" };
569 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
570 			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
571 
572 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
573 			       0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
574 
575 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
576 			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
577 
578 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
579 			       0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
580 
581 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
582 			       0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
583 
584 static const char * const keypad_parents[] = { "osc24M", "osc32k" };
585 static const u8 keypad_table[] = { 0, 2 };
586 static struct ccu_mp keypad_clk = {
587 	.enable	= BIT(31),
588 	.m	= _SUNXI_CCU_DIV(0, 5),
589 	.p	= _SUNXI_CCU_DIV(16, 2),
590 	.mux	= _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
591 	.common	= {
592 		.reg		= 0x0c4,
593 		.hw.init	= CLK_HW_INIT_PARENTS("keypad",
594 						      keypad_parents,
595 						      &ccu_mp_ops,
596 						      0),
597 	}
598 };
599 
600 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
601 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
602 			       0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
603 
604 /*
605  * There are 3 OHCI 12M clock source selection bits in this register.
606  * We will force them to 0 (12M divided from 48M).
607  */
608 #define SUN8I_R40_USB_CLK_REG	0x0cc
609 
610 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
611 		      0x0cc, BIT(8), 0);
612 static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
613 		      0x0cc, BIT(9), 0);
614 static SUNXI_CCU_GATE(usb_phy2_clk,	"usb-phy2",	"osc24M",
615 		      0x0cc, BIT(10), 0);
616 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc12M",
617 		      0x0cc, BIT(16), 0);
618 static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"osc12M",
619 		      0x0cc, BIT(17), 0);
620 static SUNXI_CCU_GATE(usb_ohci2_clk,	"usb-ohci2",	"osc12M",
621 		      0x0cc, BIT(18), 0);
622 
623 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
624 					   "pll-periph1", "osc32k" };
625 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
626 				  0, 4,		/* M */
627 				  16, 2,	/* P */
628 				  24, 2,	/* mux */
629 				  BIT(31),	/* gate */
630 				  0);
631 
632 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
633 				  0, 4,		/* M */
634 				  16, 2,	/* P */
635 				  24, 2,	/* mux */
636 				  BIT(31),	/* gate */
637 				  0);
638 
639 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
640 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
641 			    0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
642 
643 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
644 		      0x100, BIT(0), 0);
645 static SUNXI_CCU_GATE(dram_csi0_clk,	"dram-csi0",	"dram",
646 		      0x100, BIT(1), 0);
647 static SUNXI_CCU_GATE(dram_csi1_clk,	"dram-csi1",	"dram",
648 		      0x100, BIT(2), 0);
649 static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
650 		      0x100, BIT(3), 0);
651 static SUNXI_CCU_GATE(dram_tvd_clk,	"dram-tvd",	"dram",
652 		      0x100, BIT(4), 0);
653 static SUNXI_CCU_GATE(dram_mp_clk,	"dram-mp",	"dram",
654 		      0x100, BIT(5), 0);
655 static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",	"dram",
656 		      0x100, BIT(6), 0);
657 
658 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
659 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
660 				 0x104, 0, 4, 24, 3, BIT(31),
661 				 CLK_SET_RATE_PARENT);
662 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
663 				 0x108, 0, 4, 24, 3, BIT(31), 0);
664 
665 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
666 					     "pll-video0-2x", "pll-video1-2x",
667 					     "pll-mipi" };
668 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
669 			       0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
670 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
671 			       0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
672 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
673 				 0x118, 0, 4, 24, 3, BIT(31),
674 				 CLK_SET_RATE_PARENT);
675 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
676 				 0x11c, 0, 4, 24, 3, BIT(31),
677 				 CLK_SET_RATE_PARENT);
678 
679 static const char * const deinterlace_parents[] = { "pll-periph0",
680 						    "pll-periph1" };
681 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
682 				 deinterlace_parents, 0x124, 0, 4, 24, 3,
683 				 BIT(31), 0);
684 
685 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
686 						 "pll-periph1" };
687 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
688 				 0x130, 0, 5, 8, 3, BIT(15), 0);
689 
690 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
691 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
692 				 0x134, 16, 4, 24, 3, BIT(31), 0);
693 
694 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
695 				 0x134, 0, 5, 8, 3, BIT(15), 0);
696 
697 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
698 			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
699 
700 static SUNXI_CCU_GATE(codec_clk,	"codec",	"pll-audio",
701 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
702 static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
703 		      0x144, BIT(31), 0);
704 
705 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
706 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
707 				 0x150, 0, 4, 24, 2, BIT(31),
708 				 CLK_SET_RATE_PARENT);
709 
710 static SUNXI_CCU_GATE(hdmi_slow_clk,	"hdmi-slow",	"osc24M",
711 		      0x154, BIT(31), 0);
712 
713 /*
714  * In the SoC's user manual, the P factor is mentioned, but not used in
715  * the frequency formula.
716  *
717  * Here the factor is included, according to the BSP kernel source,
718  * which contains the P factor of this clock.
719  */
720 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
721 					     "pll-ddr0" };
722 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
723 				  0, 4,		/* M */
724 				  16, 2,	/* P */
725 				  24, 2,	/* mux */
726 				  BIT(31),	/* gate */
727 				  CLK_IS_CRITICAL);
728 
729 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
730 						 "pll-periph0" };
731 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
732 				 0x168, 0, 4, 8, 2, BIT(15), 0);
733 
734 static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
735 				 0x180, 0, 4, 24, 3, BIT(31), 0);
736 static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
737 				 0x184, 0, 4, 24, 3, BIT(31), 0);
738 
739 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
740 					    "pll-video0-2x", "pll-video1-2x" };
741 static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
742 				 0x188, 0, 4, 24, 3, BIT(31), 0);
743 static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
744 				 0x18c, 0, 4, 24, 3, BIT(31), 0);
745 static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
746 				 0x190, 0, 4, 24, 3, BIT(31), 0);
747 static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
748 				 0x194, 0, 4, 24, 3, BIT(31), 0);
749 
750 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
751 			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
752 
753 static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
754 static const struct ccu_mux_fixed_prediv out_predivs[] = {
755 	{ .index = 0, .div = 750, },
756 };
757 
758 static struct ccu_mp outa_clk = {
759 	.enable	= BIT(31),
760 	.m	= _SUNXI_CCU_DIV(8, 5),
761 	.p	= _SUNXI_CCU_DIV(20, 2),
762 	.mux	= {
763 		.shift		= 24,
764 		.width		= 2,
765 		.fixed_predivs	= out_predivs,
766 		.n_predivs	= ARRAY_SIZE(out_predivs),
767 	},
768 	.common	= {
769 		.reg		= 0x1f0,
770 		.features	= CCU_FEATURE_FIXED_PREDIV,
771 		.hw.init	= CLK_HW_INIT_PARENTS("outa", out_parents,
772 						      &ccu_mp_ops, 0),
773 	}
774 };
775 
776 static struct ccu_mp outb_clk = {
777 	.enable	= BIT(31),
778 	.m	= _SUNXI_CCU_DIV(8, 5),
779 	.p	= _SUNXI_CCU_DIV(20, 2),
780 	.mux	= {
781 		.shift		= 24,
782 		.width		= 2,
783 		.fixed_predivs	= out_predivs,
784 		.n_predivs	= ARRAY_SIZE(out_predivs),
785 	},
786 	.common	= {
787 		.reg		= 0x1f4,
788 		.features	= CCU_FEATURE_FIXED_PREDIV,
789 		.hw.init	= CLK_HW_INIT_PARENTS("outb", out_parents,
790 						      &ccu_mp_ops, 0),
791 	}
792 };
793 
794 static struct ccu_common *sun8i_r40_ccu_clks[] = {
795 	&pll_cpu_clk.common,
796 	&pll_audio_base_clk.common,
797 	&pll_video0_clk.common,
798 	&pll_ve_clk.common,
799 	&pll_ddr0_clk.common,
800 	&pll_periph0_clk.common,
801 	&pll_periph0_sata_clk.common,
802 	&pll_periph1_clk.common,
803 	&pll_video1_clk.common,
804 	&pll_sata_clk.common,
805 	&pll_sata_out_clk.common,
806 	&pll_gpu_clk.common,
807 	&pll_mipi_clk.common,
808 	&pll_de_clk.common,
809 	&pll_ddr1_clk.common,
810 	&cpu_clk.common,
811 	&axi_clk.common,
812 	&ahb1_clk.common,
813 	&apb1_clk.common,
814 	&apb2_clk.common,
815 	&bus_mipi_dsi_clk.common,
816 	&bus_ce_clk.common,
817 	&bus_dma_clk.common,
818 	&bus_mmc0_clk.common,
819 	&bus_mmc1_clk.common,
820 	&bus_mmc2_clk.common,
821 	&bus_mmc3_clk.common,
822 	&bus_nand_clk.common,
823 	&bus_dram_clk.common,
824 	&bus_emac_clk.common,
825 	&bus_ts_clk.common,
826 	&bus_hstimer_clk.common,
827 	&bus_spi0_clk.common,
828 	&bus_spi1_clk.common,
829 	&bus_spi2_clk.common,
830 	&bus_spi3_clk.common,
831 	&bus_sata_clk.common,
832 	&bus_otg_clk.common,
833 	&bus_ehci0_clk.common,
834 	&bus_ehci1_clk.common,
835 	&bus_ehci2_clk.common,
836 	&bus_ohci0_clk.common,
837 	&bus_ohci1_clk.common,
838 	&bus_ohci2_clk.common,
839 	&bus_ve_clk.common,
840 	&bus_mp_clk.common,
841 	&bus_deinterlace_clk.common,
842 	&bus_csi0_clk.common,
843 	&bus_csi1_clk.common,
844 	&bus_hdmi0_clk.common,
845 	&bus_hdmi1_clk.common,
846 	&bus_de_clk.common,
847 	&bus_tve0_clk.common,
848 	&bus_tve1_clk.common,
849 	&bus_tve_top_clk.common,
850 	&bus_gmac_clk.common,
851 	&bus_gpu_clk.common,
852 	&bus_tvd0_clk.common,
853 	&bus_tvd1_clk.common,
854 	&bus_tvd2_clk.common,
855 	&bus_tvd3_clk.common,
856 	&bus_tvd_top_clk.common,
857 	&bus_tcon_lcd0_clk.common,
858 	&bus_tcon_lcd1_clk.common,
859 	&bus_tcon_tv0_clk.common,
860 	&bus_tcon_tv1_clk.common,
861 	&bus_tcon_top_clk.common,
862 	&bus_codec_clk.common,
863 	&bus_spdif_clk.common,
864 	&bus_ac97_clk.common,
865 	&bus_pio_clk.common,
866 	&bus_ir0_clk.common,
867 	&bus_ir1_clk.common,
868 	&bus_ths_clk.common,
869 	&bus_keypad_clk.common,
870 	&bus_i2s0_clk.common,
871 	&bus_i2s1_clk.common,
872 	&bus_i2s2_clk.common,
873 	&bus_i2c0_clk.common,
874 	&bus_i2c1_clk.common,
875 	&bus_i2c2_clk.common,
876 	&bus_i2c3_clk.common,
877 	&bus_can_clk.common,
878 	&bus_scr_clk.common,
879 	&bus_ps20_clk.common,
880 	&bus_ps21_clk.common,
881 	&bus_i2c4_clk.common,
882 	&bus_uart0_clk.common,
883 	&bus_uart1_clk.common,
884 	&bus_uart2_clk.common,
885 	&bus_uart3_clk.common,
886 	&bus_uart4_clk.common,
887 	&bus_uart5_clk.common,
888 	&bus_uart6_clk.common,
889 	&bus_uart7_clk.common,
890 	&bus_dbg_clk.common,
891 	&ths_clk.common,
892 	&nand_clk.common,
893 	&mmc0_clk.common,
894 	&mmc1_clk.common,
895 	&mmc2_clk.common,
896 	&mmc3_clk.common,
897 	&ts_clk.common,
898 	&ce_clk.common,
899 	&spi0_clk.common,
900 	&spi1_clk.common,
901 	&spi2_clk.common,
902 	&spi3_clk.common,
903 	&i2s0_clk.common,
904 	&i2s1_clk.common,
905 	&i2s2_clk.common,
906 	&ac97_clk.common,
907 	&spdif_clk.common,
908 	&keypad_clk.common,
909 	&sata_clk.common,
910 	&usb_phy0_clk.common,
911 	&usb_phy1_clk.common,
912 	&usb_phy2_clk.common,
913 	&usb_ohci0_clk.common,
914 	&usb_ohci1_clk.common,
915 	&usb_ohci2_clk.common,
916 	&ir0_clk.common,
917 	&ir1_clk.common,
918 	&dram_clk.common,
919 	&dram_ve_clk.common,
920 	&dram_csi0_clk.common,
921 	&dram_csi1_clk.common,
922 	&dram_ts_clk.common,
923 	&dram_tvd_clk.common,
924 	&dram_mp_clk.common,
925 	&dram_deinterlace_clk.common,
926 	&de_clk.common,
927 	&mp_clk.common,
928 	&tcon_lcd0_clk.common,
929 	&tcon_lcd1_clk.common,
930 	&tcon_tv0_clk.common,
931 	&tcon_tv1_clk.common,
932 	&deinterlace_clk.common,
933 	&csi1_mclk_clk.common,
934 	&csi_sclk_clk.common,
935 	&csi0_mclk_clk.common,
936 	&ve_clk.common,
937 	&codec_clk.common,
938 	&avs_clk.common,
939 	&hdmi_clk.common,
940 	&hdmi_slow_clk.common,
941 	&mbus_clk.common,
942 	&dsi_dphy_clk.common,
943 	&tve0_clk.common,
944 	&tve1_clk.common,
945 	&tvd0_clk.common,
946 	&tvd1_clk.common,
947 	&tvd2_clk.common,
948 	&tvd3_clk.common,
949 	&gpu_clk.common,
950 	&outa_clk.common,
951 	&outb_clk.common,
952 };
953 
954 /* Fixed Factor clocks */
955 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
956 
957 /* We hardcode the divider to 4 for now */
958 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
959 			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
960 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
961 			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
962 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
963 			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
964 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
965 			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
966 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
967 			"pll-periph0", 1, 2, 0);
968 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
969 			"pll-periph1", 1, 2, 0);
970 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
971 			"pll-video0", 1, 2, 0);
972 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
973 			"pll-video1", 1, 2, 0);
974 
975 static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
976 	.hws	= {
977 		[CLK_OSC_12M]		= &osc12M_clk.hw,
978 		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
979 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
980 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
981 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
982 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
983 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
984 		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
985 		[CLK_PLL_VIDEO0_2X]	= &pll_video0_2x_clk.hw,
986 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
987 		[CLK_PLL_DDR0]		= &pll_ddr0_clk.common.hw,
988 		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
989 		[CLK_PLL_PERIPH0_SATA]	= &pll_periph0_sata_clk.common.hw,
990 		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
991 		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
992 		[CLK_PLL_PERIPH1_2X]	= &pll_periph1_2x_clk.hw,
993 		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
994 		[CLK_PLL_VIDEO1_2X]	= &pll_video1_2x_clk.hw,
995 		[CLK_PLL_SATA]		= &pll_sata_clk.common.hw,
996 		[CLK_PLL_SATA_OUT]	= &pll_sata_out_clk.common.hw,
997 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
998 		[CLK_PLL_MIPI]		= &pll_mipi_clk.common.hw,
999 		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
1000 		[CLK_PLL_DDR1]		= &pll_ddr1_clk.common.hw,
1001 		[CLK_CPU]		= &cpu_clk.common.hw,
1002 		[CLK_AXI]		= &axi_clk.common.hw,
1003 		[CLK_AHB1]		= &ahb1_clk.common.hw,
1004 		[CLK_APB1]		= &apb1_clk.common.hw,
1005 		[CLK_APB2]		= &apb2_clk.common.hw,
1006 		[CLK_BUS_MIPI_DSI]	= &bus_mipi_dsi_clk.common.hw,
1007 		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
1008 		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
1009 		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
1010 		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
1011 		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
1012 		[CLK_BUS_MMC3]		= &bus_mmc3_clk.common.hw,
1013 		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
1014 		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
1015 		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
1016 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
1017 		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
1018 		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
1019 		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
1020 		[CLK_BUS_SPI2]		= &bus_spi2_clk.common.hw,
1021 		[CLK_BUS_SPI3]		= &bus_spi3_clk.common.hw,
1022 		[CLK_BUS_SATA]		= &bus_sata_clk.common.hw,
1023 		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
1024 		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
1025 		[CLK_BUS_EHCI1]		= &bus_ehci1_clk.common.hw,
1026 		[CLK_BUS_EHCI2]		= &bus_ehci2_clk.common.hw,
1027 		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
1028 		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
1029 		[CLK_BUS_OHCI2]		= &bus_ohci2_clk.common.hw,
1030 		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
1031 		[CLK_BUS_MP]		= &bus_mp_clk.common.hw,
1032 		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
1033 		[CLK_BUS_CSI0]		= &bus_csi0_clk.common.hw,
1034 		[CLK_BUS_CSI1]		= &bus_csi1_clk.common.hw,
1035 		[CLK_BUS_HDMI0]		= &bus_hdmi0_clk.common.hw,
1036 		[CLK_BUS_HDMI1]		= &bus_hdmi1_clk.common.hw,
1037 		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
1038 		[CLK_BUS_TVE0]		= &bus_tve0_clk.common.hw,
1039 		[CLK_BUS_TVE1]		= &bus_tve1_clk.common.hw,
1040 		[CLK_BUS_TVE_TOP]	= &bus_tve_top_clk.common.hw,
1041 		[CLK_BUS_GMAC]		= &bus_gmac_clk.common.hw,
1042 		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
1043 		[CLK_BUS_TVD0]		= &bus_tvd0_clk.common.hw,
1044 		[CLK_BUS_TVD1]		= &bus_tvd1_clk.common.hw,
1045 		[CLK_BUS_TVD2]		= &bus_tvd2_clk.common.hw,
1046 		[CLK_BUS_TVD3]		= &bus_tvd3_clk.common.hw,
1047 		[CLK_BUS_TVD_TOP]	= &bus_tvd_top_clk.common.hw,
1048 		[CLK_BUS_TCON_LCD0]	= &bus_tcon_lcd0_clk.common.hw,
1049 		[CLK_BUS_TCON_LCD1]	= &bus_tcon_lcd1_clk.common.hw,
1050 		[CLK_BUS_TCON_TV0]	= &bus_tcon_tv0_clk.common.hw,
1051 		[CLK_BUS_TCON_TV1]	= &bus_tcon_tv1_clk.common.hw,
1052 		[CLK_BUS_TCON_TOP]	= &bus_tcon_top_clk.common.hw,
1053 		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
1054 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
1055 		[CLK_BUS_AC97]		= &bus_ac97_clk.common.hw,
1056 		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
1057 		[CLK_BUS_IR0]		= &bus_ir0_clk.common.hw,
1058 		[CLK_BUS_IR1]		= &bus_ir1_clk.common.hw,
1059 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
1060 		[CLK_BUS_KEYPAD]	= &bus_keypad_clk.common.hw,
1061 		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
1062 		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
1063 		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
1064 		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
1065 		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
1066 		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
1067 		[CLK_BUS_I2C3]		= &bus_i2c3_clk.common.hw,
1068 		[CLK_BUS_CAN]		= &bus_can_clk.common.hw,
1069 		[CLK_BUS_SCR]		= &bus_scr_clk.common.hw,
1070 		[CLK_BUS_PS20]		= &bus_ps20_clk.common.hw,
1071 		[CLK_BUS_PS21]		= &bus_ps21_clk.common.hw,
1072 		[CLK_BUS_I2C4]		= &bus_i2c4_clk.common.hw,
1073 		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
1074 		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
1075 		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
1076 		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
1077 		[CLK_BUS_UART4]		= &bus_uart4_clk.common.hw,
1078 		[CLK_BUS_UART5]		= &bus_uart5_clk.common.hw,
1079 		[CLK_BUS_UART6]		= &bus_uart6_clk.common.hw,
1080 		[CLK_BUS_UART7]		= &bus_uart7_clk.common.hw,
1081 		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
1082 		[CLK_THS]		= &ths_clk.common.hw,
1083 		[CLK_NAND]		= &nand_clk.common.hw,
1084 		[CLK_MMC0]		= &mmc0_clk.common.hw,
1085 		[CLK_MMC1]		= &mmc1_clk.common.hw,
1086 		[CLK_MMC2]		= &mmc2_clk.common.hw,
1087 		[CLK_MMC3]		= &mmc3_clk.common.hw,
1088 		[CLK_TS]		= &ts_clk.common.hw,
1089 		[CLK_CE]		= &ce_clk.common.hw,
1090 		[CLK_SPI0]		= &spi0_clk.common.hw,
1091 		[CLK_SPI1]		= &spi1_clk.common.hw,
1092 		[CLK_SPI2]		= &spi2_clk.common.hw,
1093 		[CLK_SPI3]		= &spi3_clk.common.hw,
1094 		[CLK_I2S0]		= &i2s0_clk.common.hw,
1095 		[CLK_I2S1]		= &i2s1_clk.common.hw,
1096 		[CLK_I2S2]		= &i2s2_clk.common.hw,
1097 		[CLK_AC97]		= &ac97_clk.common.hw,
1098 		[CLK_SPDIF]		= &spdif_clk.common.hw,
1099 		[CLK_KEYPAD]		= &keypad_clk.common.hw,
1100 		[CLK_SATA]		= &sata_clk.common.hw,
1101 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
1102 		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
1103 		[CLK_USB_PHY2]		= &usb_phy2_clk.common.hw,
1104 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
1105 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
1106 		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,
1107 		[CLK_IR0]		= &ir0_clk.common.hw,
1108 		[CLK_IR1]		= &ir1_clk.common.hw,
1109 		[CLK_DRAM]		= &dram_clk.common.hw,
1110 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
1111 		[CLK_DRAM_CSI0]		= &dram_csi0_clk.common.hw,
1112 		[CLK_DRAM_CSI1]		= &dram_csi1_clk.common.hw,
1113 		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
1114 		[CLK_DRAM_TVD]		= &dram_tvd_clk.common.hw,
1115 		[CLK_DRAM_MP]		= &dram_mp_clk.common.hw,
1116 		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
1117 		[CLK_DE]		= &de_clk.common.hw,
1118 		[CLK_MP]		= &mp_clk.common.hw,
1119 		[CLK_TCON_LCD0]		= &tcon_lcd0_clk.common.hw,
1120 		[CLK_TCON_LCD1]		= &tcon_lcd1_clk.common.hw,
1121 		[CLK_TCON_TV0]		= &tcon_tv0_clk.common.hw,
1122 		[CLK_TCON_TV1]		= &tcon_tv1_clk.common.hw,
1123 		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
1124 		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,
1125 		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
1126 		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,
1127 		[CLK_VE]		= &ve_clk.common.hw,
1128 		[CLK_CODEC]		= &codec_clk.common.hw,
1129 		[CLK_AVS]		= &avs_clk.common.hw,
1130 		[CLK_HDMI]		= &hdmi_clk.common.hw,
1131 		[CLK_HDMI_SLOW]		= &hdmi_slow_clk.common.hw,
1132 		[CLK_MBUS]		= &mbus_clk.common.hw,
1133 		[CLK_DSI_DPHY]		= &dsi_dphy_clk.common.hw,
1134 		[CLK_TVE0]		= &tve0_clk.common.hw,
1135 		[CLK_TVE1]		= &tve1_clk.common.hw,
1136 		[CLK_TVD0]		= &tvd0_clk.common.hw,
1137 		[CLK_TVD1]		= &tvd1_clk.common.hw,
1138 		[CLK_TVD2]		= &tvd2_clk.common.hw,
1139 		[CLK_TVD3]		= &tvd3_clk.common.hw,
1140 		[CLK_GPU]		= &gpu_clk.common.hw,
1141 		[CLK_OUTA]		= &outa_clk.common.hw,
1142 		[CLK_OUTB]		= &outb_clk.common.hw,
1143 	},
1144 	.num	= CLK_NUMBER,
1145 };
1146 
1147 static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
1148 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
1149 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
1150 	[RST_USB_PHY2]		=  { 0x0cc, BIT(2) },
1151 
1152 	[RST_DRAM]		=  { 0x0f4, BIT(31) },
1153 	[RST_MBUS]		=  { 0x0fc, BIT(31) },
1154 
1155 	[RST_BUS_MIPI_DSI]	=  { 0x2c0, BIT(1) },
1156 	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
1157 	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
1158 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
1159 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
1160 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
1161 	[RST_BUS_MMC3]		=  { 0x2c0, BIT(11) },
1162 	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
1163 	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
1164 	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
1165 	[RST_BUS_TS]		=  { 0x2c0, BIT(18) },
1166 	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
1167 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
1168 	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
1169 	[RST_BUS_SPI2]		=  { 0x2c0, BIT(22) },
1170 	[RST_BUS_SPI3]		=  { 0x2c0, BIT(23) },
1171 	[RST_BUS_SATA]		=  { 0x2c0, BIT(24) },
1172 	[RST_BUS_OTG]		=  { 0x2c0, BIT(25) },
1173 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(26) },
1174 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(27) },
1175 	[RST_BUS_EHCI2]		=  { 0x2c0, BIT(28) },
1176 	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(29) },
1177 	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(30) },
1178 	[RST_BUS_OHCI2]		=  { 0x2c0, BIT(31) },
1179 
1180 	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
1181 	[RST_BUS_MP]		=  { 0x2c4, BIT(2) },
1182 	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
1183 	[RST_BUS_CSI0]		=  { 0x2c4, BIT(8) },
1184 	[RST_BUS_CSI1]		=  { 0x2c4, BIT(9) },
1185 	[RST_BUS_HDMI0]		=  { 0x2c4, BIT(10) },
1186 	[RST_BUS_HDMI1]		=  { 0x2c4, BIT(11) },
1187 	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
1188 	[RST_BUS_TVE0]		=  { 0x2c4, BIT(13) },
1189 	[RST_BUS_TVE1]		=  { 0x2c4, BIT(14) },
1190 	[RST_BUS_TVE_TOP]	=  { 0x2c4, BIT(15) },
1191 	[RST_BUS_GMAC]		=  { 0x2c4, BIT(17) },
1192 	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
1193 	[RST_BUS_TVD0]		=  { 0x2c4, BIT(21) },
1194 	[RST_BUS_TVD1]		=  { 0x2c4, BIT(22) },
1195 	[RST_BUS_TVD2]		=  { 0x2c4, BIT(23) },
1196 	[RST_BUS_TVD3]		=  { 0x2c4, BIT(24) },
1197 	[RST_BUS_TVD_TOP]	=  { 0x2c4, BIT(25) },
1198 	[RST_BUS_TCON_LCD0]	=  { 0x2c4, BIT(26) },
1199 	[RST_BUS_TCON_LCD1]	=  { 0x2c4, BIT(27) },
1200 	[RST_BUS_TCON_TV0]	=  { 0x2c4, BIT(28) },
1201 	[RST_BUS_TCON_TV1]	=  { 0x2c4, BIT(29) },
1202 	[RST_BUS_TCON_TOP]	=  { 0x2c4, BIT(30) },
1203 	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
1204 
1205 	[RST_BUS_LVDS]		=  { 0x2c8, BIT(0) },
1206 
1207 	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
1208 	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
1209 	[RST_BUS_AC97]		=  { 0x2d0, BIT(2) },
1210 	[RST_BUS_IR0]		=  { 0x2d0, BIT(6) },
1211 	[RST_BUS_IR1]		=  { 0x2d0, BIT(7) },
1212 	[RST_BUS_THS]		=  { 0x2d0, BIT(8) },
1213 	[RST_BUS_KEYPAD]	=  { 0x2d0, BIT(10) },
1214 	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
1215 	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
1216 	[RST_BUS_I2S2]		=  { 0x2d0, BIT(14) },
1217 
1218 	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
1219 	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
1220 	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
1221 	[RST_BUS_I2C3]		=  { 0x2d8, BIT(3) },
1222 	[RST_BUS_CAN]		=  { 0x2d8, BIT(4) },
1223 	[RST_BUS_SCR]		=  { 0x2d8, BIT(5) },
1224 	[RST_BUS_PS20]		=  { 0x2d8, BIT(6) },
1225 	[RST_BUS_PS21]		=  { 0x2d8, BIT(7) },
1226 	[RST_BUS_I2C4]		=  { 0x2d8, BIT(15) },
1227 	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
1228 	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
1229 	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
1230 	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
1231 	[RST_BUS_UART4]		=  { 0x2d8, BIT(20) },
1232 	[RST_BUS_UART5]		=  { 0x2d8, BIT(21) },
1233 	[RST_BUS_UART6]		=  { 0x2d8, BIT(22) },
1234 	[RST_BUS_UART7]		=  { 0x2d8, BIT(23) },
1235 };
1236 
1237 static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
1238 	.ccu_clks	= sun8i_r40_ccu_clks,
1239 	.num_ccu_clks	= ARRAY_SIZE(sun8i_r40_ccu_clks),
1240 
1241 	.hw_clks	= &sun8i_r40_hw_clks,
1242 
1243 	.resets		= sun8i_r40_ccu_resets,
1244 	.num_resets	= ARRAY_SIZE(sun8i_r40_ccu_resets),
1245 };
1246 
1247 static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
1248 	.common	= &pll_cpu_clk.common,
1249 	/* copy from pll_cpu_clk */
1250 	.enable	= BIT(31),
1251 	.lock	= BIT(28),
1252 };
1253 
1254 static struct ccu_mux_nb sun8i_r40_cpu_nb = {
1255 	.common		= &cpu_clk.common,
1256 	.cm		= &cpu_clk.mux,
1257 	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
1258 	.bypass_index	= 1, /* index of 24 MHz oscillator */
1259 };
1260 
1261 /*
1262  * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1263  * GMAC configuration register.
1264  * Only this register is allowed to be written, in order to
1265  * prevent overriding critical clock configuration.
1266  */
1267 
1268 #define SUN8I_R40_GMAC_CFG_REG 0x164
1269 static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
1270 						unsigned int reg)
1271 {
1272 	if (reg == SUN8I_R40_GMAC_CFG_REG)
1273 		return true;
1274 	return false;
1275 }
1276 
1277 static struct regmap_config sun8i_r40_ccu_regmap_config = {
1278 	.reg_bits	= 32,
1279 	.val_bits	= 32,
1280 	.reg_stride	= 4,
1281 	.max_register	= 0x320, /* PLL_LOCK_CTRL_REG */
1282 
1283 	/* other devices have no business accessing other registers */
1284 	.readable_reg	= sun8i_r40_ccu_regmap_accessible_reg,
1285 	.writeable_reg	= sun8i_r40_ccu_regmap_accessible_reg,
1286 };
1287 
1288 #define SUN8I_R40_SYS_32K_CLK_REG 0x310
1289 #define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
1290 
1291 static int sun8i_r40_ccu_probe(struct platform_device *pdev)
1292 {
1293 	struct resource *res;
1294 	struct regmap *regmap;
1295 	void __iomem *reg;
1296 	u32 val;
1297 	int ret;
1298 
1299 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 	reg = devm_ioremap_resource(&pdev->dev, res);
1301 	if (IS_ERR(reg))
1302 		return PTR_ERR(reg);
1303 
1304 	/* Force the PLL-Audio-1x divider to 4 */
1305 	val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
1306 	val &= ~GENMASK(19, 16);
1307 	writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
1308 
1309 	/* Force PLL-MIPI to MIPI mode */
1310 	val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
1311 	val &= ~BIT(16);
1312 	writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
1313 
1314 	/* Force OHCI 12M parent to 12M divided from 48M */
1315 	val = readl(reg + SUN8I_R40_USB_CLK_REG);
1316 	val &= ~GENMASK(25, 20);
1317 	writel(val, reg + SUN8I_R40_USB_CLK_REG);
1318 
1319 	/*
1320 	 * Force SYS 32k (otherwise known as LOSC throughout the CCU)
1321 	 * clock parent to LOSC output from RTC module instead of the
1322 	 * CCU's internal RC oscillator divided output.
1323 	 */
1324 	writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
1325 	       reg + SUN8I_R40_SYS_32K_CLK_REG);
1326 
1327 	regmap = devm_regmap_init_mmio(&pdev->dev, reg,
1328 				       &sun8i_r40_ccu_regmap_config);
1329 	if (IS_ERR(regmap))
1330 		return PTR_ERR(regmap);
1331 
1332 	ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
1333 	if (ret)
1334 		return ret;
1335 
1336 	/* Gate then ungate PLL CPU after any rate changes */
1337 	ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
1338 
1339 	/* Reparent CPU during PLL CPU rate changes */
1340 	ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1341 				  &sun8i_r40_cpu_nb);
1342 
1343 	return 0;
1344 }
1345 
1346 static const struct of_device_id sun8i_r40_ccu_ids[] = {
1347 	{ .compatible = "allwinner,sun8i-r40-ccu" },
1348 	{ }
1349 };
1350 
1351 static struct platform_driver sun8i_r40_ccu_driver = {
1352 	.probe	= sun8i_r40_ccu_probe,
1353 	.driver	= {
1354 		.name	= "sun8i-r40-ccu",
1355 		.of_match_table	= sun8i_r40_ccu_ids,
1356 	},
1357 };
1358 builtin_platform_driver(sun8i_r40_ccu_driver);
1359