1 /* 2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 18 #include "ccu_common.h" 19 #include "ccu_reset.h" 20 21 #include "ccu_div.h" 22 #include "ccu_gate.h" 23 #include "ccu_mp.h" 24 #include "ccu_nm.h" 25 26 #include "ccu-sun8i-r.h" 27 28 static const char * const ar100_parents[] = { "osc32k", "osc24M", 29 "pll-periph0", "iosc" }; 30 31 static struct ccu_div ar100_clk = { 32 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 33 34 .mux = { 35 .shift = 16, 36 .width = 2, 37 38 .variable_prediv = { 39 .index = 2, 40 .shift = 8, 41 .width = 5, 42 }, 43 }, 44 45 .common = { 46 .reg = 0x00, 47 .features = CCU_FEATURE_VARIABLE_PREDIV, 48 .hw.init = CLK_HW_INIT_PARENTS("ar100", 49 ar100_parents, 50 &ccu_div_ops, 51 0), 52 }, 53 }; 54 55 static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0); 56 57 static struct ccu_div apb0_clk = { 58 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 59 60 .common = { 61 .reg = 0x0c, 62 .hw.init = CLK_HW_INIT("apb0", 63 "ahb0", 64 &ccu_div_ops, 65 0), 66 }, 67 }; 68 69 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", 70 0x28, BIT(0), 0); 71 static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", 72 0x28, BIT(1), 0); 73 static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", 74 0x28, BIT(2), 0); 75 static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", 76 0x28, BIT(3), 0); 77 static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", 78 0x28, BIT(4), 0); 79 static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", 80 0x28, BIT(6), 0); 81 static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", 82 0x28, BIT(7), 0); 83 84 static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" }; 85 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", 86 r_mod0_default_parents, 0x54, 87 0, 4, /* M */ 88 16, 2, /* P */ 89 24, 2, /* mux */ 90 BIT(31), /* gate */ 91 0); 92 93 static struct ccu_common *sun8i_h3_r_ccu_clks[] = { 94 &ar100_clk.common, 95 &apb0_clk.common, 96 &apb0_pio_clk.common, 97 &apb0_ir_clk.common, 98 &apb0_timer_clk.common, 99 &apb0_uart_clk.common, 100 &apb0_i2c_clk.common, 101 &apb0_twd_clk.common, 102 &ir_clk.common, 103 }; 104 105 static struct ccu_common *sun50i_a64_r_ccu_clks[] = { 106 &ar100_clk.common, 107 &apb0_clk.common, 108 &apb0_pio_clk.common, 109 &apb0_ir_clk.common, 110 &apb0_timer_clk.common, 111 &apb0_rsb_clk.common, 112 &apb0_uart_clk.common, 113 &apb0_i2c_clk.common, 114 &apb0_twd_clk.common, 115 &ir_clk.common, 116 }; 117 118 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { 119 .hws = { 120 [CLK_AR100] = &ar100_clk.common.hw, 121 [CLK_AHB0] = &ahb0_clk.hw, 122 [CLK_APB0] = &apb0_clk.common.hw, 123 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 124 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 125 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 126 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 127 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 128 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 129 [CLK_IR] = &ir_clk.common.hw, 130 }, 131 .num = CLK_NUMBER, 132 }; 133 134 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { 135 .hws = { 136 [CLK_AR100] = &ar100_clk.common.hw, 137 [CLK_AHB0] = &ahb0_clk.hw, 138 [CLK_APB0] = &apb0_clk.common.hw, 139 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 140 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 141 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 142 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 143 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 144 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 145 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 146 [CLK_IR] = &ir_clk.common.hw, 147 }, 148 .num = CLK_NUMBER, 149 }; 150 151 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { 152 [RST_APB0_IR] = { 0xb0, BIT(1) }, 153 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 154 [RST_APB0_UART] = { 0xb0, BIT(4) }, 155 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 156 }; 157 158 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { 159 [RST_APB0_IR] = { 0xb0, BIT(1) }, 160 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 161 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 162 [RST_APB0_UART] = { 0xb0, BIT(4) }, 163 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 164 }; 165 166 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { 167 .ccu_clks = sun8i_h3_r_ccu_clks, 168 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), 169 170 .hw_clks = &sun8i_h3_r_hw_clks, 171 172 .resets = sun8i_h3_r_ccu_resets, 173 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), 174 }; 175 176 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { 177 .ccu_clks = sun50i_a64_r_ccu_clks, 178 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), 179 180 .hw_clks = &sun50i_a64_r_hw_clks, 181 182 .resets = sun50i_a64_r_ccu_resets, 183 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), 184 }; 185 186 static void __init sunxi_r_ccu_init(struct device_node *node, 187 const struct sunxi_ccu_desc *desc) 188 { 189 void __iomem *reg; 190 191 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 192 if (IS_ERR(reg)) { 193 pr_err("%s: Could not map the clock registers\n", 194 of_node_full_name(node)); 195 return; 196 } 197 198 sunxi_ccu_probe(node, reg, desc); 199 } 200 201 static void __init sun8i_h3_r_ccu_setup(struct device_node *node) 202 { 203 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); 204 } 205 CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", 206 sun8i_h3_r_ccu_setup); 207 208 static void __init sun50i_a64_r_ccu_setup(struct device_node *node) 209 { 210 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); 211 } 212 CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", 213 sun50i_a64_r_ccu_setup); 214